TEXAS INSTRUMENTS TAS5026A Technical data
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查询TAS5026A供应商
TM
Data M anua
January 2004 DAV Digital Audio/Speaker
SLES068A
IMPORTANT NOTICE
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Products Applications
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DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
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Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
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Copyright 2004, Texas Instruments Incorporated
Contents
Contents
Section Page
1 Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Functional Block Diagram 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Terminal Assignments 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terminal Functions 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Architecture Overview 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Clock and Serial Data Interface 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection 7. . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 Clock Master/Slave Mode (M_S) 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Clock Master Mode 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 Clock Slave Mode 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5 PLL Filter 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6 DCLK 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.7 Serial Data Interface 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Reset, Power Down, and Status 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Reset—RESET 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Power Down—PDN 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 General Status Registers 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4 Error Status Register 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Signal Processing 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Volume Control 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Mute 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 Automute 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.4 Individual Channel Mute 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.5 De-Emphasis Filter 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Pulse Width Modulator (PWM) 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 Clipping Indicator 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.2 Error Recovery 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.3 Individual Channel Error Recovery 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.4 PWM DC-Offset Correction 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.5 Interchannel Delay 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.6 PWM/H-Bridge and Discrete H-Bridge Driver Interface 22. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 I2C Serial Control Interface 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 Single-Byte Write 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2 Multiple-Byte Write 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3 Single-Byte Read 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4 Multiple-Byte Read 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Serial Control Interface Register Definitions 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 General Status Register (0x00) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Error Status Register (0x01) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 System Control Register 0 (0x02) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 System Control Register 1 (0x03) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Error Recovery Register (0x04) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Automute Delay Register (0x05) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 DC-Offset Control Registers (0x06−0x0B) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
February 2003—Revised January 2004 SLES068A
iii
List of Illustrations
3.8 Interchannel Delay Registers (0x0C−0x11) 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Individual Channel Mute Register (0x19) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 System Procedures for Initialization, Changing Data Rates, and Switching Between Master
and Slave Modes 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 System Initialization 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Data Sample Rate 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Changing Between Master and Slave Modes 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Specifications 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Absolute Maximum Ratings Over Operating Temperature Ranges 37. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Recommended Operating Conditions 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Electrical Characteristics Over Recommended Operating Conditions 37. . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 Static Digital Specifications Over Recommended Operating Conditions 37. . . . . . . . . . . . . .
5.3.2 Digital Interpolation Filter and PWM Modulator Over Recommended
Operating Conditions (Fs = 48 kHz) 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 TAS5026A/TAS5110 System Performance Measured at the Speaker
Terminals Over Recommended Operating Conditions (Fs = 48 kHz) 38. . . . . . . . . . . . . . . .
5.4 Switching Characteristics 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.1 Command Sequence Timing 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 Serial Audio Port 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
5.4.3 Serial Control Port—I
6 Application Information 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Serial Audio Interface Clock Master and Slave Interface Configuration 48. . . . . . . . . . . . . . . . . . . . . . . .
6.1.1 Slave Configuration 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2 Master Configuration 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Mechanical Data 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A—Volume Table 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C Operation 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations
Figure Title Page
2−1 Crystal Circuit 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 External PLL Loop Filter 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 I2S 64-Fs Format 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 I2S 48-Fs Format 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Left-Justified 64-Fs Format 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Left-Justified 48-Fs Format 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 Right-Justified 64-Fs Format 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Right-Justified 48-Fs Format 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 DSP Format 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 Attenuation Curve 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 De-Emphasis Filter Characteristics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 PWM Outputs and H-Bridge Driven in BTL Configuration 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−13 Typical I2C Sequence 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 Single-Byte Write Transfer 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−15 Multiple-Byte Write Transfer 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−16 Single-Byte Read 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
February 2003—Revised January 2004SLES068A
List of Tables
2−17 Multiple-Byte Read 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 RESET
4−2 Extending the I2C Write Interval Following Low-to-High Transition of RESET Terminal 32. . . . . . . . . . . . . . . . .
4−3 Changing the Data Sample Rate Using the DBSPD Terminal 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Changing the Data Sample Rate Using the I2C33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Changing the Data Sample Rate With an Unstable MCLK_IN Using the DBSPD Terminal 34. . . . . . . . . . . . . .
4−6 Changing the Data Sample Rate With an Unstable MCLK_IN Using the I2C35. . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Changing Between Master and Slave Clock Modes 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 RESET Timing 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 Power-Down and Power-Up Timing—RESET Preceding PDN 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−3 Power-Down and Power-Up Timing—RESET Following PDN 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4 Error Recovery Timing 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−5 Mute Timing 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−6 Right-Justified, I2S, Left-Justified Serial-Protocol Timing 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−7 Right, Left, and I2S Serial-Mode Timing Requirement 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8 Serial Audio Ports Master-Mode Timing 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9 DSP Serial-Port Timing 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10 DSP Serial-Port Expanded Timing 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 DSP Absolute Timing 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 SCL and SDA Timing 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 Start and Stop Conditions Timing 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Typical TAS5026A Application 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 TAS5026A Serial Audio Port—Slave-Mode Connection Diagram 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 TAS5026A Serial Audio Port—Master-Mode Connection Diagram 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
During System Initialization 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
Table Title Page
2−1 Normal-Speed, Double-Speed, and Quad-Speed Operation 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Master and Slave Clock Modes 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 LRCLK and MCLK_IN Rates 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 DCLK 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Supported Word Lengths 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Device Outputs During Reset 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 Values Set During Reset 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Device Outputs During Power Down 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Volume Register 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 De-Emphasis Filter Characteristics 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 Device Outputs During Error Recovery 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 I2C Register Map 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 General Status Register (Read Only) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Error Status Register 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 System Control Register 0 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 System Control Register 1 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Error Recovery Register 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
February 2003—Revised January 2004 SLES068A
v
List of Tables
3−7 Automute Delay Register 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 DC-Offset Control Registers 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Six Interchannel Delay Registers 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 Individual Channel Mute Register 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
February 2003—Revised January 2004SLES068A
1 Introduction
The TAS5026A is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse-width
modulator (PWM) based on Equibit technology. Combined with a TI PurePath Digital audio amplifier power
stage, these devices use noise-shaping and sophisticated error correction algorithms to achieve high power
efficiency and high-performance digital audio reproduction. The TAS5026A is designed to drive up to six digital
power devices to provide six channels of digital audio amplification. The digital power devices can be six
conventional monolithic power stages (such as T AS5110) or six discrete differential power stages using gate
drivers and MOSFETs.
The TAS5026A has six independent volume controls and mute. The device operates in AD mode. This
all-digital audio system contains only two analog components in the signal chain—an LC low-pass filter at each
speaker terminal and can provide up to 96-dB SNR at the speaker terminals. The T AS5026A has a wide variety
of serial input options including right justified (16, 20, or 24 bit), I2S (16, 20, or 24 bit) left justified, or DSP
(16-bit) data formats. The device is fully compatible with AES standard sampling rates of 44.1 kHz, 48 kHz,
88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz including de-emphasis for 44.1-kHz and 48-kHz sample rates. The
TAS5026A was designed for home theater applications such as DVD minicomponent systems, home theater
in a box (HTIB), DVD receiver, A/V receiver, or TV sets.
1.1 Features
• TI PurePath Digital Audio Amplifier
• High Quality Audio
− 96-dB SNR
− <0.1% THD+N
• Six-Channel Volume Control
− Patented Soft Volume
− Patented Soft Mute
• 16-, 20-, or 24-Bit Input Data
• Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz
• Supports Master and Slave Modes
• 3.3-V Power Supply Operation
• Economical 64-Pin TQFP Package
• Digital De-Emphasis: 32 kHz, 44.1 kHz, and 48 kHz
• Clock Oscillator Circuit for Master Modes
• Low Jitter Internal PLL
• Soft Volume and Mute Update
Introduction
Equibit and PurePath Digital are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
SLES068A—February 2003—Revised January 2004 TAS5026A
1
Introduction
1.2 Functional Block Diagram
AVDD_PLL
AVSS_PLL
VREGA_CAP
VREGB_CAP
VREGC_CAP
DVDD_RCL
DVSS_RCL
DVDD_PWM
DVSS_PWM
MCLK_IN
XTAL_OUT
XTAL_IN
DBSPD
M_S
PLL_FLT_OUT
PLL_FLT_RET
SCLK
LRCLK
MCLKOUT
SDIN1
SDIN2
SDIN3
DM_SEL1
DM_SEL2
SDA
SCL
CSO
RESET
PDN
CLIP
MUTE
ERR_RCVRY
Clock,
PLL
and
Serial
Data
I/F
Serial
Control
I/F
Reset,
Pwr Dwn
and
Status
Power Supply
Signal
Processing
Auto Mute
De-Emphasis
Soft Volume
Error Recovery
Soft Mute
Clip Detect
PWM
Section
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
PWM Ch.
Output Control
PWM_AP_1
PWM_AM_1
VALID_1
PWM_AP_2
PWM_AM_2
VALID_2
PWM AP_3
PWM AM_3
VALID_3
PWM_AP_4
PWM_AM_4
VALID_4
PWM_AP_5
PWM_AM_5
VALID_5
PWM_AP_6
PWM_AM_6
VALID_6
2
SLES068A—February 2003—Revised January 2004TAS5026A
1.3 Terminal Assignments
1
NC
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MCLK_IN
AVDD_PLL
PLL_FLT_OUT
PLL_FLT_RET
AVSS_PLL
DVSS1
RST
ERR_RCVRY
MUTE
PDN
SDA
SCL
CS0
DVSS1
PAG PACKAGE
(TOP VIEW)
AVDD_OSC
XTL_IN
XTL_OUT
AVSS_OSC
DVSS
PWM_AP_1
PWM_AM_1
VALID_1
PWM_AP_2
PWM_AM_2
VALID_2
PWM_AP_3
PWM_AM_3
VALID_3NCNC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17
18 19 21 22 23 24 25 26 27 28 29 30 31 32
20
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Introduction
DVDD_RCL
DVSS_RCL
NC
DVDD_PWM
DVSS_PWM
PWM_AP_4
PWM_AM_4
VALID_4
PWM_AP_5
PWM_AM_5
VALID_5
PWM_AP_6
PWM_AM_6
VALID_6
NC
NC
CLIP
DBSPD
SDIN1
SDIN2
SCLK
SDIN3
MCLK_OUT
DVDD
LRCLK
NC
DVSS1
M_S
DVSS1
DEM_SEL2
DEM_SEL1
DVSS1
SLES068A—February 2003—Revised January 2004 TAS5026A
3
Introduction
FUNCTION
†
DESCRIPTION
1.4 Ordering Information
T AS
5026A PAG
Texas Instruments
Audio Solutions
Device Number
Package Type
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C TAS5026APAG
PLASTIC 64-PIN TQFP
(PAG)
1.5 Terminal Functions
TERMINAL
NAME NO.
AVDD_OSC 64 P Analog power supply for internal oscillator cells
AVDD_PLL 3 P 3.3-V analog power supply for PLL
AVSS_OSC 61 O Analog ground for internal oscillator cells
AVSS_PLL 6 P Analog ground for PLL
CLIP 18 O Digital clipping indicator, active low
CS0 15 I I2C device address select. This is an active high pin.
DBSPD 17 I Sample rate is double speed (88.2 kHz or 96 kHz), active high
DM_SEL1 29 I De-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz
DM_SEL2 28 I De-emphasis select bit 2, 10 = 48 kHz, 11 = undefined (none)
DVDD_PWM 45 P 3.3-V digital power supply for PWM
DVDD_RCL 48 P 3.3-V digital power supply for re-clocker
DVDD 25 P 3.3-V digital power supply for digital core and most of I/O buffers
DVSS 60 I Voltage regulator enable, active low
DVSS_PWM 44 P Digital ground for PWM
DVSS_RCL 47 P Digital ground for re-clocker
DVSS1 8, 26,
ERR_RCVRY 10 I Error recovery, active low
LRCLK 24 I/O Serial audio data left/right clock (sampling rate clock) (input when M_S = 0; output when
M_S 30 I Master/slave mode input signal (master = 1, slave = 0)
MCLK_IN 2 I MCLK input, slave mode
MCLK_OUT 22 O MCLK output buffered system clock output M_S = 1; otherwise set to 0
MUTE 11 I Mute input signal, active low
†
I = input; O = output; I/O = input/output; P = power
31, 32
P Digital ground for digital core and most of I/O buffers
M_S = 1)
4
SLES068A—February 2003—Revised January 2004TAS5026A
TERMINAL
FUNCTION
†
DESCRIPTION
NAME NO.
NC 1, 7,
PDN 12 I Power down. This signal is active low.
PLL_FLT_OUT 4 I PLL external filter
PLL_FLT_RET 5 I PLL external filter
PWM_AM_1 58 O PWM 1 output (differential -); {Positive H-bridge side}
PWM_AM_2 55 O PWM 2 output (differential -); {Positive H-bridge side}
PWM_AM_3 52 O PWM 3 output (differential -); {Positive H-bridge side}
PWM_AM_4 42 O PWM 4 output (differential -); {Positive H-bridge side}
PWM_AM_5 39 O PWM 5 output (differential -); {Positive H-bridge side}
PWM_AM_6 36 O PWM 6 output (differential -); {Positive H-bridge side}
PWM_AP_1 59 O PWM 1 output (differential +); {Positive H-bridge side}
PWM_AP_2 56 O PWM 2 output (differential +); {Positive H-bridge side}
PWM_AP_3 53 O PWM 3 output (differential +); {Positive H-bridge side}
PWM_AP_4 43 O PWM 4 output (differential +); {Positive H-bridge side}
PWM_AP_5 40 O PWM 5 output (differential +); {Positive H-bridge side}
PWM_AP_6 37 O PWM 6 output (differential +); {Positive H-bridge side}
RST 9 I System reset input. This signal is an active low.
SCL 14 I I2C clock signal
SCLK 23 I/O Serial audio data clock (master mode = output, slave mode = input)
SDA 13 I/O I2C data signal
SDIN1 19 I Serial audio data 1 input
SDIN2 20 I Serial audio data 2 input
SDIN3 21 I Serial audio data 3 input
VALID_1 57 O Output indicating validity of PWM outputs, channel 1, active high
VALID_2 54 O Output indicating validity of PWM outputs, channel 2, active high
VALID_3 51 O Output indicating validity of PWM outputs, channel 3, active high
VALID_4 41 O Output indicating validity of PWM outputs, channel 4, active high
VALID_5 38 O Output indicating validity of PWM outputs, channel 5, active high
VALID_6 35 O Output indicating validity of PWM outputs, channel 6, active high
XTL_IN 63 I Crystal or TTL level clock input
XTL_OUT 62 O Crystal output (not for external usage)
†
I = input; O = output; I/O = input/output; P = power
27, 33,
34, 36,
49, 50
— No connection
Introduction
SLES068A—February 2003—Revised January 2004 TAS5026A
5
Introduction
6
SLES068A—February 2003—Revised January 2004TAS5026A
2 Architecture Overview
The TAS5026A is composed of six functional elements:
• Clock, PLL, and serial data interface (I
• Reset/power-down circuitry
• Serial control interface (I2C)
• Signal processing unit
• Pulse-width modulator (PWM)
• Power supply
2.1 Clock and Serial Data Interface
The TAS5026A clock and serial data interface contain an input serial data slave and the clock master/ slave
interface. The serial data slave interface receives information from a digital source such as a DSP, S/PDIF
receiver, analog-to-digital converter (ADC), digital audio processor (DAP), or other serial bus master. The
serial data interface has three serial data inputs that can accept up to six channels of data at data sample rates
of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. The serial data interfaces support
left justified and right justified for 16-, 20-, and 24-bits. In addition, the serial data interface supports the DSP
protocol for 16 bits and the I
The TAS5026A can function as a receiver or a generator for the MCLK_IN (master clock), SCLK (shift clock),
and LRCLK (left/right clock) signals that control the flow of data on the three serial data interfaces. The
T AS5026A i s a clock master when it generates these clocks and is a clock slave when it receives these clocks.
The TAS5026A is a synchronous design that relies upon the master clock to provide a reference clock for all
of the device operations and communication via the I2C. When operating as a slave, this reference clock is
MCLK_IN. When operating as a master , the reference clock is either a TTL clock input t o X TAL_IN or a crystal
attached across XTAL_IN and XTAL_OUT.
2
S protocol for 24 bits.
Architecture Overview
2
S)
The clock and serial data interface has two control parameters: data sample rate and clock master or slave.
2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection
The data sample rate is selected through a terminal (DBSPD) or the serial control register 0 (X02). The data
sample rate control sets the frequencies of the SCLK and LRCLK in clock slave mode and the output
frequencies of SCLK and LRCLK in clock master mode. There are three data rates: normal speed, double
speed, and quad speed.
Normal-speed mode supports data rates of 32 kHz, 44.1 kHz, and 48 kHz. Normal speed is supported in the
master and slave modes. Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz.
Double speed is supported in master and slave modes. Quad-speed mode is used to support sampling rates
of 176.4 kHz and 192 kHz.
The PWM is placed in normal speed by setting the DBSPD terminal low or by setting the normal mode bits
in the system control register 0 (x02) through the serial control interface. The PWM is placed in double speed
mode by setting the DBSPD terminal high or by setting the double speed bits in the system control register.
Quad-speed mode is auto detected supported in slave mode and invoked using the I
in master mode. In slave mode, if the TAS5026A is not in double speed mode, quad-speed mode is
automatically detected when MCLK_IN is 128Fs. In master mode, the PWM is placed in quad-speed mode
by setting the quad-speed bit in the system control register through the serial control interface.
If the master clock is well behaved during the frequency transition (the high or low clock periods are not less
than 20 ns), then a simple speed selection is simply performed by setting the DBSPD terminal or the serial
control register.
When the sample rate is changed, the TAS5026A temporarily suspends processing, places the PWM outputs
in a hard mute (PWM P outputs low; PWM M outputs high, and all VALID signals low), resets all internal
processes, and suspends all I
noiselessly restarts the PWM output. The TAS5026A preserves all control register settings throughout this
sequence. If desired, the sample rate change can be performed while mute is active to provide a completely
silent transition. The timing of this control sequence is shown in Section 4.
2
C operations. The TAS5026A then performs a partial re-initialization and
2
C serial control interface
SLES068A—February 2003—Revised January 2004 TAS5026A
7
Architecture Overview
If the master clock input can encounter a high clock or low clock period of less than 20 ns while the data rates
are changing, then RESET
should be applied during this time There are two recommended control procedures
for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These
control sequences are shown in Section 4.
Table 2−1. Normal-Speed, Double-Speed, and Quad-Speed Operation
QUAD-SPEED CONTROL
REGISTER BIT
0 0 Master or slave Normal speed
0 1 Master or slave Double speed
1 0 Master or slave Quad speed
0 0 Slave Quad speed if MCLK_IN = 128 Fs
1 1 Master or slave Error
DBSPD TERMINAL OR
CONTROL REGISTER BIT
2.1.2 Clock Master/Slave Mode (M_S)
Clock master and slave mode can be invoked using the M_S (master slave) terminal.
This terminal specifies the default mode that is set immediately following a device RESET. The serial data
interface setting permits the clock generation mode to be changed during normal operation.
The transition to master mode occurs:
• Following a RESET when M_S terminal has a logic high applied
MODE SPEED SELECTION
The transition to slave mode occurs:
• Following a RESET when M_S terminal has a logic low applied
2.1.3 Clock Master Mode
When M_S = 1 following a RESET, the TAS5026A provides the master clock, SCLK, and LRCLK to the rest
of the system. In the master mode, the TAS5026A outputs the audio system clocks MCLK_OUT, SCLK, and
LRCLK.
The TAS5026A device generates these clocks plus its internal clocks from the internal phase-locked loop
(PLL). The reference clock for the PLL can be provided by either an external clock source (attached to
XT AL_IN) or a crystal (connected across terminals XTAL_IN and XTAL_OUT). The external source attached
to MCLK_IN is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the
data sample rate and the SCLK frequency of 48 times the data sample rate is not supported in the master
mode. The LRCLK frequency is the data sample rate.
2.1.3.1 Crystal Type and Circuit
In clock master mode the TAS5026A can derive the MCLKOUT, SCLK, and LRCLK from a crystal. In this case,
the TAS5026A uses a parallel-mode fundamental-mode crystal. This crystal is connected to the TAS5026A
as shown in Figure 2−1.
8
SLES068A—February 2003—Revised January 2004TAS5026A
TAS5026A
Architecture Overview
rd = Drive level control resistor − crystal vendor specified
CL = Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal)
CL = (C1 x C2 )/(C1 + C2 ) + CS (where CS = board stray capacitance ~ 3 pF)
Example: Vendor recommended CL = 18 pF, CS = 3 pF ≥ C1 = C2 = 2 x (18−3) = 30 pF
2.1.4 Clock Slave Mode
In the slave mode (M_S = 0), the master clock, LRCLK, and SCLK are inputs to the TAS5026A. The master
clock is supplied through the MCLK_IN terminal.
C
1
C
2
r
d
OSC
MACRO
XO
XI
AVSS
Figure 2−1. Crystal Circuit
As in the master mode, the TAS5026A device develops its internal timing from the internal phase-locked loop
(PLL). The reference clock for the PLL is provided by the input to the MCLK_IN terminal. This input is at a
frequency of 256 times (128 in quad mode) the input data rate. The SCLK frequency is 48 or 64 times the data
sample rate. The LRCLK frequency is the data sample rate. The TAS5026A does not require any specific
phase relationship between SRCLK and MCLK_IN, but there must be synchronization. The TAS5026A
monitors the relationship between MCLK, SCLK and LRCLK. The TAS5026A detects if any of the three clocks
are absent, if the LRCLK rate changes more than 10 MCLK cycles since the last device reset or clock error,
or if the MCLK frequency is changing substantially with respect to the PLL frequency.
When a clock error is detected, the TAS5026A performs a clock error management sequence.
The clock error management sequence temporarily suspends processing, places the PWM outputs in a hard
mute (PWM_P outputs are low; PWM_M outputs are high, and all VALID signals are low), resets all internal
processes, sets the volumes to mute, and suspends all I
2
C operations.
When the error condition is corrected, the TAS5026A exits the clock error sequence by performing a partial
re-initialization, noiselessly restarting the PWM output, and ramping the volume up to the level specified in
the volume control registers. This sequence is performed over a 60-ms interval. The TAS5026A preserves
all control register settings that were set prior to the clock interruption.
If a clock error occurs while the ERR_RCVRY
terminal is asserted (low), the TAS5026A performs the error
management sequence up to the unmute sequence. In this case, the volume remains at full attenuation with
the PWM output at a 50% duty cycle. The volume can be restored from this latched mute state by triggering
a mute/unmute sequence by asserting and releasing MUTE
either by using the terminal, the system control
register X01 D4, or the individual channel mute register D5−D0.
Alternatively, the TAS5026A can be prevented from entering the latched mute state following a clock error
when the ERR_RCVRY
terminal or the error recovery I2C command (register X03 bit D2) is active by writing
x7F to the individual error recovery register (x04) and a x84 to x1F (a feature enable register).
SLES068A—February 2003—Revised January 2004 TAS5026A
9
Architecture Overview
Table 2−2. Master and Slave Clock Modes
DESCRIPTION M_S DBSPD
Internal PLL, master, normal speed 1 0 8.192 - 2.048 32 8.192
Internal PLL, master, normal speed 1 0 11.2896 - 2.8224 44.1 11.2896
Internal PLL, master, normal speed 1 0 12.288 - 3.072 48 12.288
Internal PLL, master, double speed 1 1 - 22.5792
Internal PLL, master, double speed 1 1 - 24.576
Internal PLL, master, quad speed 1 0 - 22.5792 11.2896 176.4 22.5792
Internal PLL, master, quad speed 1 0 - 24.576 12.288 192 24.576
Internal PLL, slave, normal speed 0 0 - 8.192§ 2.0484 32 Digital GND
Internal PLL, slave, normal speed 0 0 - 11.2896
Internal PLL, slave, normal speed 0 0 - 12.288§ 3.072 48 Digital GND
Internal PLL, slave, double speed 0 1 - 22.5792 5.6448 88.2 Digital GND
Internal PLL, slave, double speed 0 1 - 24.576§ 6.144 96 Digital GND
Internal PLL, slave, quad speed
Internal PLL, slave, quad speed
†
A crystal oscillator is connected to XTL_IN.
‡
MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN_IN is provided.
§
External MCLK_IN connected to MCLK_IN_IN input
¶
SCLK and LRCLK are outputs when M_S = 1, and inputs when M_S = 0.
#
MCLK_OUT is driven low when M_S = 0.
||
Quad-speed mode is detected automatically.
||
||
0 0 - 22.5792
0 0 - 24.576§ 12.288 192 Digital GND
XTL_IN
(MHz)
k SCLK can be 48 or 64 times Fs
†
MCLK_IN
‡
(MHz)
SCLK
(MHz)
k
§
§
§
§
5.6448 88.2 22.5792
6.144 96 24.576
2.8224 44.1 Digital GND
11.2896 176 Digital GND
LRCLK
(kHz)
¶
MCLK_OUT
(MHz)
#
Table 2−3. LRCLK and MCLK_IN Rates
NORMAL SPEED (kHz) DOUBLE SPEED (kHz) QUAD SPEED (kHz)
LRCLK 1 Fs 32 44.1 48 1 Fs 64 88.2 96 1 Fs 176.4 192
MCLK_IN 256 Fs 8,192 11,289.6 12,288 256 Fs 16,384 22,579.2 24,576 128 Fs 22,579.2 24,576
2.1.5 PLL External Filter
A low jitter PLL produces the internal timing of the TAS5026A (when in master mode), the master clock, SCLK,
and LRCLK. Connections for the PLL external filter are provided through PLL_FL T_OUT and PLL_FLT_RET
as shown in Figure 2−2.
PLL_FLT_OUT
220 Ω
4.7 nF
TAS5026A
PLL_FLT_RET
Figure 2−2. PLL External Filter
47 nF
10
SLES068A—February 2003—Revised January 2004TAS5026A
2.1.6 DCLK
DCLK is the internal high frequency clock that is produced by the PLL circuitry from MCLK. The TAS5026A
uses the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode,
4 times MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I
registers, DCLK clock cycles are used to specify interchannel delay and to detect when the MCLK frequency
is drifting. Table 2−4 DCLK shows the relationship between Sample Rate, MCLK, and DCLK.
Table 2−4. DCLK
Architecture Overview
2
C addressable
Fs
(kHz)
32 8.1920 65.5360 15.3
44.1 11.2896 90.3168 11.1
48 12.2880 98.3040 10.2
88 22.5280 90.1120 11.1
96 24.5760 98.3040 10.2
192 49.1520 98.3040 10.2
2.1.7 Serial Data Interface
The TAS5026A operates as a slave only/receive only serial data interface in all modes. The TAS5026A has
three PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs.
The serial audio data is in MSB first; 2s complement format.
The serial data interfaces of the T AS5026A can be configured in right justified, I
This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample
rates. The serial data interface format is specified using the data interface control register . The supported word
lengths are shown in Table 2−5.
During normal operating conditions if the serial data interface settings change state, an error recovery
sequence is initiated.
DATA MODES
Right justified, MSB first 16 0 0 0
Right justified, MSB first 20 0 0 1
Right justified, MSB first 24 0 1 0
Left justified, MSB first 24 1 1 0
DSP frame 16 1 1 1
MCLK
(MHz)
DCLK
(MHz)
DCLK Period
(ns)
2
S, left-justified, or DSP modes.
Table 2−5. Supported Word Lengths
WORD
LENGTHS
I2S 16 0 1 1
I2S 20 1 0 0
I2S 24 1 0 1
MOD2 MOD1 MOD0
SLES068A—February 2003—Revised January 2004 TAS5026A
11
Architecture Overview
2.1.7.1 I2S Timing
I2S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for
the right channel. The LRCLK is low for the left channel and high for the right channel. A bit clock running at
48 or 64 times Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal
changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising
edge of the bit clock. The TAS5026A masks unused trailing data bit positions. Master mode only supports a
64 times Fs bit clock.
2-Channel I2S (Philips Format) Stereo Input
32 Clks
32 Clks
LRCLK (Note Reversed Phase) Left Channel
SCLK
MSB LSB
24-Bit Mode
23 22
20-Bit Mode
19 18
16-Bit Mode
9 8 5 4 1 0
5 4 1 0
1 015 14
Figure 2−3. I2S 64-Fs Format
2-Channel I2S Stereo Input/Output (24-Bit Transfer Word Size)
24 Clks
LRCLK
Left Channel
Right Channel
SCLK
MSB LSB
23 22
19 18 5 4 1 0
9 8 5 4 1 0
1 015 14
24 Clks
Right Channel
SCLK
MSB LSB
24-Bit Mode
22
23
20-Bit Mode
19 18
16-Bit Mode
20 19 8 7 2 1
16 15 1 0
12
11
13
4
517
1 015 14
4 3521
Figure 2−4. I2S 48-Fs Format
12
SCLK
MSB LSB
23 22
0
19 18 16 15 1 0
20 19 8 7 2 1
4
517
13
11
12
SLES068A—February 2003—Revised January 2004TAS5026A
1 015 14
4 3521
2.1.7.2 Left-Justified Timing
2-Channel Left-Justified Stereo Input
2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size)
Left-justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock
running at 48 or 64 times Fs is used to clock in the data. The first bit of data appears on the data lines at the
same time the LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock.
The TAS5026A masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.
Architecture Overview
32 Clks
LRCLK
Left Channel
SCLK
MSB LSB
24-Bit Mode
23 22
NOTE: All data presented in 2s complement form with MSB first.
9 8 5 4 1 0
Figure 2−5. Left-Justified 64-Fs Format
24 Clks
LRCLK
Left Channel
32 Clks
LRCLK
Right Channel
MSB LSB
23 22
9 8 5 4 1 0
24 Clks
Right Channel
SCLK
MSB LSB
24-Bit Mode
22 21
19 9 8 1 0
3 242023 22 21
Figure 2−6. Left-Justified 48-Fs Format
2.1.7.3 Right-Justified Timing
Right-justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock
running at 48 or 64 times Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock
periods (for 24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always
clocks the LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5026A masks unused leading data bit positions. Master mode only supports a 64 times Fs bit clock.
SLES068A—February 2003—Revised January 2004 TAS5026A
MSB LSB
19 9 8 1 0
5
3 2420235
13
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