TEXAS INSTRUMENTS TAS5026 Technical data

查询TAS5026供应商

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    

Data Manual

November 2002 DAV Digital Audio/Speaker

SLES041B

IMPORTANT NOTICE

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Copyright  2002, Texas Instruments Incorporated

Contents

Contents

Section Page

1 Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Architecture Overview 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Clock and Serial Data Interface 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection 6. . . . . . . . . . . . . . . . . . .

2.1.2 Clock Master/Slave Mode (M_S) 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 Clock Master Mode 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4 Clock Slave Mode 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5 PLL Filter 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.6 DCLK 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.7 Serial Data Interface 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Reset, Power Down, and Status 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Reset—RESET 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Power Down—PDN 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Status Registers 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Signal Processing 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Volume Control 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Mute 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 Auto Mute 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Individual Channel Mute 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.5 De-Emphasis Filter 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Pulse Width Modulator (PWM) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 Clipping Indicator 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.2 Error Recovery 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.3 Individual Channel Error Recovery 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.4 PWM DC-Offset Correction 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.5 Inter-Channel Delay 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.6 PWM/H-Bridge and Discrete H-Bridge Driver Interface 20. . . . . . . . . . . . . . . . . . . . . . .

2.5 I2C Serial Control Interface 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 Single Byte Write 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 Multiple Byte Write 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3 Single Byte Read 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4 Multiple Byte Read 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Serial Control Interface Register Definitions 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 General Status Register (x00) 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Error Status Register (x01) 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 System Control Register 0 (x02) 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 System Control Register 1 (x03) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Error Recovery Register (x04) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Automute Delay Register (x05) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 DC-Offset Control Registers (x06–x0B) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 Interchannel Delay Registers (x0C–x11) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

November 2002 SLES041B

iii

List of Illustrations

3.9 Individual Channel Mute Register (x19) 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 System Initialization 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Specifications 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Absolute Maximum Ratings Over Operating Temperature Ranges 29. . . . . . . . . . . . . . . . . . . . . . .

5.2 Recommended Operating Conditions 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Electrical Characteristics 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.1 Static Digital Specifications 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.2 Digital Interpolation Filter and PWM Modulator 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.3 TAS5026/TAS5100 System Performance Measured at the Speaker Terminals 30. . .

5.4 Switching Characteristics 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.1 Command Sequence Timing 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.2 Serial Audio Port 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.3 Serial Control Port—I2C Operation 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Application Information 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Serial Audio Interface Clock Master and Slave Interface Configuration 39. . . . . . . . . . . . . . . . . . .

6.1.1 Slave Configuration 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.2 Master Configuration 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Mechanical Data 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

2–1 Crystal Circuit 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 External PLL Loop Filter 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 I2S 64-Fs Format 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 I2S 48-Fs Format 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Left-Justified 64-Fs Format 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Left-Justified 48-Fs Format 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Right-Justified 64-Fs Format 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Right-Justified 48-Fs Format 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 DSP Format 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 Attenuation Curve 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 De-Emphasis Filter Characteristics 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 PWM Outputs and H-Bridge Driven in BTL Configuration 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 Typical I2C Sequence 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 Single Byte Write Transfer 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–15 Multiple Byte Write Transfer 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–16 Single Byte Read 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–17 Multiple Byte Read 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 RESET During System Initialization 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 RESET Timing 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Power-Down and Power-Up Timing—RESET Preceding PDN 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 Power-Down and Power-Up Timing—RESET Following PDN 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 Error Recovery Timing 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 Mute Timing 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

November 2002SLES041B

List of Tables

5–6 Right-Justified, IIS, Left-Justified Serial Protocol Timing 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 Right, Left, and IIS Serial Mode Timing Requirement 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–8 Serial Audio Ports Master Mode Timing 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 DSP Serial Port Timing 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 DSP Serial Port Expanded Timing 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11 DSP Absolute Timing 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12 SCL and SDA Timing 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13 Start and Stop Conditions Timing 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 Typical TAS5026 Application 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 TAS5026 Serial Audio Port—Slave Mode Connection Diagram 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 TAS5026 Serial Audio Port—Master Mode Connection Diagram 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2–1 Normal-Speed, Double-Speed, and Quad-Speed Operation 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Master and Slave Clock Modes 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 LRCLK, MCLK_IN, and External PLL Rates 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 DCLK 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Supported Word Lengths 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Device Outputs During Reset 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Values Set During Reset 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Device Outputs During Power Down 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 Volume Register 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 De-Emphasis Filter Characteristics 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 Device Outputs During Error Recovery 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 I2C Register Map 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 General Status Register (Read Only) 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Error Status Register 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 System Control Register 0 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 System Control Register 1 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Error Recovery Register 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 Automute Delay Register 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 DC-Offset Control Registers 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 Six Inter-Channel Delay Registers 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 Individual Channel Mute Register 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

November 2002 SLES041B

v

1 Introduction

The TAS5026 is an innovative, cost-effective, high-performance 24-bit six-channel digital pulse width
modulator (PWM) based on Equibit technology. Combined with a TI digital amplifier power stage, these
devices use noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and
high-performance digital audio reproduction. The T AS5026 is designed to drive up to six digital power devices
to provide six channels of digital audio amplification. The digital power devices can be six conventional
monolithic power stages (such as TAS5110) or six discrete differential power stages using gate drivers and
MOSFETs.

The T AS5026 has six independent volume controls and mute. It is designed to drive a digital amplifier power
stage (such as the T AS5182) in an H-bridge (bridge tied load) configuration. The device operates in AD mode.
This all-digital audio system contains only two analog components in the signal chain—an LC low-pass filter
at each speaker terminal and can provide up to 96-dB SNR at the speaker terminals. The T AS5026 has a wide
variety of serial input options including right justified (16, 20, or 24 bit), I2S (16, 20, or 24 bit) left justified, or
DSP (16-bit) data formats. The device is fully compatible with AES standard sampling rates of 44.1 kHz, 48
kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz including de-emphasis for 44.1-kHz and 48-kHz sample rates.
The TAS5026 was designed for home theater applications such as DVD minicomponent systems, home
theater in a box (HTIB), DVD receiver, A/V receiver, or TV sets.

1.1 Features

• True Digital Audio Amplifier

• High Quality Audio

– 96-dB SNR
– <0.1% THD+N

• Six-Channel Volume Control

– Patented Soft Volume
– Patented Soft Mute

• 16-, 20-, or 24-Bit Input Data

• Sampling Rates: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz

• Supports Master and Slave Modes

• 3.3-V Power Supply Operation

• Economical 64-Pin TQFP Package

• Digital De-Emphasis: 32 kHz, 44.1 kHz, and 48 kHz

• High Power Efficiency

• Clock Oscillator Circuit for Master Modes

• Low Jitter Internal PLL

• Soft Volume and Mute Update

• Excellent PSRR

Introduction

Equibit is a trademark of Texas Instruments Incorporated.

SLES041B—November 2002 TAS5026

1

Introduction

1.2 Functional Block Diagram

AVDD_PLL

AVSS_PLL

VREGA_CAP

VREGB_CAP

VREGC_CAP

DVDD_RCL

DVSS_RCL

DVDD_PWM

DVSS_PWM

MCLK_IN

XTAL_OUT

XTAL_IN

CSS
M_S

PLL_FLT_OUT

PLL_FLT_RET

SCLK

LRCLK

MCLKOUT

SDIN1
SDIN2
SDIN3

SDA
SCL

CSO

RESET

PDN

CLIP

MUTE

ERR_RCVY

Clock,

PLL
and

Serial

Data

I/F

Serial

Control

I/F

Reset,

Pwr Dwn

and

Status

Power Supply

Signal

Processing

Auto Mute

De-emphasis

Soft Volume

Error Recovery

Soft Mute

Clip Detect

PWM

Section

PWM Ch.

PWM Ch.

PWM Ch.

PWM Ch.

PWM Ch.

PWM Ch.

Output Control

PWM_AP_1
PWM_AM_1
Valid_1

PWM_AP_2
PWM_AM_2
Valid_2

PWM AP_3
PWM AM_3
Valid_3

PWM_AP_4
PWM_AM_4
Valid_4

PWM_AP_5
PWM_AM_5
Valid_5

PWM_AP_6
PWM_AM_6
Valid_6

2

SLES041B—November 2002TAS5026

1.3 Terminal Assignments

1

NC

NC

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

MCLK_IN

AVDD_PLL

PLL_FLT_OUT

PLL_FLT_RET

AVSS_PLL

DVSS1

RST

ERR_RCVY

MUTE

PDN
SDA

SCL
CS0

DVSS1

PAG PACKAGE

(TOP VIEW)

AVDD_OSC

XTL_IN

XTL_OUT

AVSS_OSC

DVSS

PWM_AP_1

PWM_AM_1

VALID_1

PWM_AP_2

PWM_AM_2

VALID_2

PWM_AP_3

PWM_AM_3

VALID_3NCNC

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17

18 19 21 22 23 24 25 26 27 28 29 30 31 32

20

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

Introduction

DVDD_RCL
DVSS_RCL
NC
DVDD_PWM
DVSS_PWM
PWM_AP_4
PWM_AM_4
VALID_4
PWM_AP_5
PWM_AM_5
VALID_5
PWM_AP_6
PWM_AM_6
VALID_6
NC
NC

CLIP

DBSPD

SDIN1

SDIN2

SCLK

SDIN3

MCLK_OUT

DVDD

LRCLK

NC

DVSS1

M_S

DVSS1

DEM_SEL2

DEM_SEL1

DVSS1

SLES041B—November 2002 TAS5026

3

Introduction

1.4 Ordering Information

T exas Instruments

Audio Solutions

Device Number

T emperature Range

Package T ype

T AS

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C TAS5026CPAG

–40°C to 85°C TAS5026IPAG

PLASTIC 64-PIN TQFP

(PAG)

5026 C PAG

1.5 Terminal Functions

TERMINAL

NAME NO.

AVDD_OSC 64 PWR Analog power supply for internal oscillator cells
AVDD_PLL 3 PWR 3.3-V analog power supply for PLL
AVSS_OSC 61 AOUT Analog ground for internal oscillator cells
AVSS_PLL 6 PWR Analog ground for PLL
CLIP 18 O Digital clipping indicator, active low
CS0 15 I I2C device address select. This is an active high pin.
DBSPD 17 I Sample rate is double speed (88.2 kHz or 96 kHz), active high
DM_SEL1 29 I De-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz
DM_SEL2 28 I De-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none)
DVDD_PWM 45 PWR 3.3-V digital power supply for PWM
DVDD_RCL 48 PWR 3.3-V digital power supply for re-clocker
DVDD 25 PWR 3.3-V digital power supply for digital core and most of I/O buffers
DVSS 60 I Voltage regulator enable, active low
DVSS_PWM 44 PWR Digital ground for PWM
DVSS_RCL 47 PWR Digital ground for re-clocker
DVSS1 8, 26,

31, 32
ERR_RCVY 10 I Error recovery, active low
LRCLK 24 I/O Serial audio data left / right clock (sampling rate clock) (input when M_S = 0; output when M_S

M_S 30 I Master/slave mode input signal (master = 1, slave = 0)
MCLK_IN 2 I MCLK input, slave mode
MCLK_OUT 22 O MCLK output buffered system clock output M_S = 1; otherwise set to 0

I/O

PWR Digital ground for digital core and most of I/O buffers

= 1)

DESCRIPTION

4

SLES041B—November 2002TAS5026

Introduction

TERMINAL

NAME

MUTE 11 I Mute input signal, active low
NC 1, 7,

PDN 12 I Power down. This signal is active low.
PLL_FLT_OUT 4 I PLL external filter
PLL_FLT_RET 5 I PLL external filter
PWM_AM_1 58 O PWM 1 output (differential -); {Positive H-bridge side}
PWM_AM_2 55 O PWM 2 output (differential -); {Positive H-bridge side}
PWM_AM_3 52 O PWM 3 output (differential -); {Positive H-bridge side}
PWM_AM_4 42 O PWM 4 output (differential -); {Positive H-bridge side}
PWM_AM_5 39 O PWM 5 output (differential -); {Positive H-bridge side}
PWM_AM_6 36 O PWM 6 output (differential -); {Positive H-bridge side}
PWM_AP_1 59 O PWM 1 output (differential +); {Positive H-bridge side}
PWM_AP_2 56 O PWM 2 output (differential +); {Positive H-bridge side}
PWM_AP_3 53 O PWM 3 output (differential +); {Positive H-bridge side}
PWM_AP_4 43 O PWM 4 output (differential +); {Positive H-bridge side}
PWM_AP_5 40 O PWM 5 output (differential +); {Positive H-bridge side}
PWM_AP_6 37 O PWM 6 output (differential +); {Positive H-bridge side}
RST 9 I System reset input. This signal is an active low.
SCL 14 I I2C clock signal
SCLK 23 I/O Serial audio data clock (master mode = output, slave mode = input)
SDA 13 I/O I2C data signal
SDIN1 19 I Serial audio data 1 input
SDIN2 20 I Serial audio data 2 input
SDIN3 21 I Serial audio data 3 input
VALID_1 57 O Output indicating validity of PWM outputs, channel 1, active high
VALID_2 54 O Output indicating validity of PWM outputs, channel 2, active high
VALID_3 51 O Output indicating validity of PWM outputs, channel 3, active high
VALID_4 41 O Output indicating validity of PWM outputs, channel 4, active high
VALID_5 38 O Output indicating validity of PWM outputs, channel 5, active high
VALID_6 35 O Output indicating validity of PWM outputs, channel 6, active high
XTL_IN 63 AIN Crystal or TTL level clock input
XTL_OUT 62 AOUT Crystal output (not for external usage)

NO.

No connection

27, 49,

50

DESCRIPTIONI/O

DESCRIPTIONI/O

SLES041B—November 2002 TAS5026

5

Architecture Overview

2 Architecture Overview

The T AS5026 is composed of six functional elements:

• Clock, PLL, and serial data interface (IIS)

• Reset/power down circuitry

• Serial control interface (IIC)

• Signal processing unit

• Pulse width modulator (PWM)

• Power supply

2.1 Clock and Serial Data Interface

The T AS5026 clock and serial data interface contains an input serial data slave and the clock master/ slave
interface.

The serial data slave interface receives information from a digital source such as a DSP, S/PDIF receiver,
analog-to-digital converter (ADC), digital audio processor (DAP) such as the TAS3103, or other serial bus
master at sample rates of for sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,176.4 kHz, and 192
kHz. The serial data interface has three serial data inputs that can accept up to six channels of data. The serial
data interfaces support left justified and right justified for 16-, 20-, and 24-bits. In addition, the serial data
interfaces support the DSP protocol for 16 bits and the I2S protocal for 24 bits. The received data is data
passed to the TAS5026 signal-processing unit.

The T AS5026 can function as a receiver or a generator for the MCLK_IN (master clock), SCLK (shift clock),
and LRCLK (left/right clock) signals that control the flow of data on the three serial data interfaces. The
T AS5026 is a clock master when it generates these clocks and is a clock slave when it receives these clocks.

The T AS5026 is a synchronous design that relies upon master clock to provide a reference clock for all of the
device operations. When operating as a slave, this reference clock is MCLK_IN. When operating as a master,
the reference clock is either TTL clock input to XT AL_IN or a crystal attached across XTAL_IN and XT AL_OUT .

If the master clock stops, the T AS5026 will perform a clock error recovery sequence. The clock error recovery
sequence temporarily suspends processing, places the PWM outputs in a hard mute (PWM_P outputs are
low; PWM_M outputs are high, and all VALID signals are low), resets all internal processes, sets the volumes
to mute, and suspends all I

When the master clock is resumed, the TAS5026 exits the clock error recovery sequence by performing a

4.3-ms partial re-initialization, noiselessly restarting the PWM output, and ramping the volume up to the level
specified in the volume control registers. The volume update is performed over a 43-ms. interval. The
TAS5026 preserves all control register settings that were set prior to the clock interruption.

If a clock error occurs while the ERR_RCVRY pin is asserted (LOW), the TAS5026 will perform the error
recovery sequence up to the unmute sequence. In this case, the volume remains at full attenuation with the
PWM output at a 50% duty cycle. The volume can be restored from this state by triggering a mute/unmute
sequence via the mute pin LOW then HIGH.

The clock and serial data interface has two control parameters: data sample rate and clock master or slave.

2

C operations.

2.1.1 Normal-Speed, Double-Speed, and Quad-Speed Selection

The sampling rate is selected through a pin (DBSPD) or the serial control register 0 (X02). When a sample
rate is selected, the system automatically performs an error recovery sequence and switches to the new
sampling rate. As shown in subsequent sections, the sample rate control sets the frequencies of the SCLK
and LRCLK in clock slave mode and the output frequencies of SCLK and LRCLK in clock master mode.

During the error recovery sequence, the T AS5026 temporarily suspends processing, places the PWM outputs
in a hard mute (PWM P outputs LOW; PWM M outputs HIGH, and all VALID signals LOW), resets all internal
processes, and suspends all I
noiselessly restarts the PWM output. The T AS5026 preserves all control register settings through out the error
recovery sequence.

6

2

C operations. The T AS5026 then performs a 4.3-ms partial re-initialization and

SLES041B—November 2002TAS5026

Architecture Overview

There are three data rates: normal speed, double speed, and quad speed.
Normal-speed mode supports data rates of 32 kHz, 44.1 kHz, and 48 kHz. Normal speed is supported in the

master and slave modes. The PWM is placed in normal speed by setting the DBSPD terminal low or by setting
the normal mode bits in the system control register through the serial control interface. Following this
operation, the PWM performs an error recovery sequence automatically and operates in the normal speed
mode.

Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz. Double speed is supported
in master and slave modes. The PWM is placed in double speed mode by setting the DBSPD terminal high
or by setting the double speed bits in the system control register through the serial control interface. Following
this operation, the PWM performs an error recovery sequence automatically and operate in double speed
mode.

Quad-speed mode is used to support sampling rates of 176.4 kHz and 192 kHz. Quad-speed mode is auto
detected supported in slave mode and invoked by control in master mode in slave mode, if the device is not
in double speed mode, quad-speed mode is automatically detected when MCLK_IN is 128Fs. In master mode,
the PWM is placed in quad-speed mode by setting the quad-speed bit in the system control register through
the serial control interface.

Table 2–1. Normal-Speed, Double-Speed, and Quad-Speed Operation

QUAD-SPEED CONTROL

REGISTER BIT

0 0 Master or slave Normal speed
0 1 Master or slave Double speed
1 0 Master or slave Quad speed
0 0 Slave Quad speed if MCLK_IN = 128Fs
1 1 Master or slave Error

DBSPD TERMINAL OR

CONTROL REGISTER BIT

MODE SPEED SELECTION

2.1.2 Clock Master/Slave Mode (M_S)

Clock master and slave mode can be invoked using the M_S (master slave) terminal.
This terminal specifies the default mode that is set immediately following a device RESET. The serial data

interface setting permits the clock generation mode to be changed during normal operation.
The transition to master mode occurs:

• Following a RESET when M_S terminal has a logic high applied
The transition to slave mode occurs:

• Following a RESET when M_S terminal has a logic low applied

2.1.3 Clock Master Mode

When M_S = 1 following a RESET, the T AS5026 provides the master clock, SCLK, and LRCLK to the rest of
the system. In the master mode, the TAS5026 outputs the audio system clocks MCLK_OUT, SCLK, and
LRCLK.

The T AS5026 device generates these clocks plus its internal clocks from the internal phase-locked loop (PLL).
The reference clock for the PLL can be provided by either an external clock source (attached to XT AL_IN) or
a crystal (connected across terminals XT AL_IN and XT AL_OUT). The external source attached to MCLK_IN
is 256 times (128 in quad mode) the data sample rate (Fs). The SCLK frequency is 64 times the data sample
rate and the SCLK frequency of 48 times the data sample rate is not supported in the master mode. The LRCLK
frequency is the data sample rate.

2.1.3.1 Crystal Type and Circuit

In clock master mode the T AS5026 can derive the MCLKOUT , SCLK, and LRCLK from a crystal. In this case,
the TAS5026 uses a parallel-mode fundamental-mode crystal. This crystal is connected to the TAS5026 as
shown in Figure 2–1.

SLES041B—November 2002 TAS5026

7

Architecture Overview

TAS5026

rd = Drive level control resistor – crystal vendor specified
CL = Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal)
CL = (C1 x C2 )/(C1 + C2 ) + CS (where CS = board stray capacitance ~ 3 pF)
Example: Vendor recommended CL = 18 pF, CS = 3 pF ≥ C1 = C2 = 2 x (18–3) = 30 pF

2.1.4 Clock Slave Mode

In the slave mode (M_S = 0), the master clock, LRCLK, and SCLK are inputs to the T AS5026. The master clock
is supplied through the MCLK_IN terminal.

C

1

C

2

r

d

OSC

MACRO

XO

XI

AVSS

Figure 2–1. Crystal Circuit

As in the master mode, the TAS5026 device developed its internal timing from internal phase-locked loop
(PLL). The reference clock for the PLL is provided by the input to the MCLK_IN terminal. This input is at a
frequency of 256 times (128 in quad mode) the input data rate. The SCLK frequency is 48 or 64 times the data
sample rate. The LRCLK frequency is the data sample rate. The T AS5026 does not require any specific phase
relationship between SRCLK and MCLK_IN, but there must be synchronization.

The TAS5026 monitors the relationship between MCLK, SCLK and LRCLK. The TAS5026 detects if any of
the three clocks are absent, if LRCLK rate changes more the ±10 MCLK cycles since the last device reset or
clock error recovery , or if MCLK frequency is changing substantially with respect to the PLL frequency . When
a clock error is detected the T AS5026 performs a clock error recovery sequence. If one or more of the clock
signals are absent, the TAS5026 is held with the outputs in hard mute until the clock is resumed. Once the
clock is resumed, the clock error recover sequence is completed.

NOTE:

The detection of a clock error causes the TAS5026 to perform an immediate hard mute and
suspension of all processes. This abrupt transition can produce a faint click as the outputs are
muted.

Since the clocks are removed when changing media or during input selection, it is possible to use this
knowledge to completely eliminate clicks in these conditions. In this case, the click is prevented by muting the
outputs by using the MUTE

terminal or the I2C /MUTE command 43 ms in advance of the clocks being

removed.
In the slave mode, MCLK_OUT is driven low.
Table 2–2 shows all the possible master and slave modes. When operating in quad mode (Fs = 176.4 kHz

or 192 kHz), the device works in slave mode only with MCLK_IN = 128 Fs.
Table 2–3 shows the clocks speed for normal, double and quad modes.

8

SLES041B—November 2002TAS5026

Architecture Overview

Table 2–2. Master and Slave Clock Modes

DESCRIPTION M_S DBSPD

Internal PLL, master, normal speed 1 0 8.192 - 2.048 32 8.192
Internal PLL, master, normal speed 1 0 11.2896 - 2.8224 44.1 11.2896
Internal PLL, master, normal speed 1 0 12.288 - 3.072 48 12.288
Internal PLL, master, double speed 1 1 - 22.5792
Internal PLL, master, double speed 1 1 - 24.576
Internal PLL, master, quad speed 1 0 - 22.5792 11.2896 176.4 22.5792
Internal PLL, master, quad speed 1 0 - 24.576 12.288 192 24.576
Internal PLL, slave, normal speed 0 0 - 8.192§ 2.0484 32 Digital GND
Internal PLL, slave, normal speed 0 0 - 11.2896
Internal PLL, slave, normal speed 0 0 - 12.288§ 3.072 48 Digital GND
Internal PLL, slave, double speed 0 1 - 22.5792 5.6448 88.2 Digital GND
Internal PLL, slave, double speed 0 1 - 24.576§ 6.144 96 Digital GND
Internal PLL, slave, quad speed
Internal PLL, slave, quad speed
External PLL, master, normal speed 1 0 - - 2.048 32 8.192
External PLL, master, normal speed 1 0 - - 2.8224 44.1 11.2896
External PLL, master, normal speed 1 0 - - 3.072 48 12.288
External PLL, master, double speed 1 1 - - 5.6448 88.2 22.5792
External PLL, master, double speed 1 1 - - 6.144 96 24.576
External PLL, master, quad speed 1 0 - - 11.2896 176.4 22.5792
External PLL, master, quad speed 1 0 - - 12.288 192 24.576
External PLL, slave, normal speed 0 0 - 8.192§ 2.0484 32 Digital GND
External PLL, slave, normal speed 0 0 - 11.2896
External PLL, slave, normal speed 0 0 - 12.288§ 3.072 48 Digital GND
External PLL, slave, double speed 0 1 - 22.5792 5.6448 88.2 Digital GND
External PLL, slave, double speed 0 1 - 24.576§ 6.144 96 Digital GND
External PLL, slave, quad speed
External PLL, slave, quad speed

†

A crystal oscillator is connected to XTL_IN.

‡

MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN_IN is provided.

§

External MCLK_IN connected to MCLK_IN_IN input

¶

SCLK and LRCLK are outputs when M_S=1, and inputs when M_S=0.

#

MCLK_OUT is driven low when M_S=0.

||

Quad-speed mode is detected automatically.

||
||

||
||

0 0 - 22.5792
0 0 - 24.576§ 12.288 192 Digital GND

0 0 - 22.5792
0 0 - 24.576§ 12.288 192 Digital GND

XTL_IN

(MHz)

k SCLK can be 48 or 64 times Fs

†

MCLK_IN

‡

(MHz)

SCLK

¶

(MHz)

§

§

§

§

§

§

5.6448 88.2 22.5792

6.144 96 24.576

2.8224 44.1 Digital GND

11.2896 176 Digital GND

2.8224 44.1 Digital GND

11.2896 176 Digital GND

LRCLK

(kHz)

¶

MCLK_OUT

(MHz)

#

Table 2–3. LRCLK, MCLK_IN, and External PLL Rates

NORMAL SPEED (kHz) DOUBLE SPEED (kHz) QUAD SPEED (kHz)

LRCLK 1FS 32 44.1 48 1FS 64 88.2 96 1FS 176.4 192

MCLK_IN 256FS 8,192 11,289.6 12,288 256FS 16,384 22,579.2 24,576 128FS 22,579.2 24,576

EXT. PLL 2048FS 65,536 90,316.8 98,304 1024FS 65,536 90,316.8 98,304 512FS 90,316.8 98,304

SLES041B—November 2002 TAS5026

9

Architecture Overview

2.1.5 PLL Filter

A low jitter PLL produces the internal timing of the T AS5026 (when in master mode), the master clock, SCLK,
and LRCLK. Connections for the PLL external loop filter are provided through PLL_FLT_OUT and
PLL_FLT_RET as shown in Figure 2–2.

PLL_FLT_OUT

220 Ω

2.1.6 DCLK

DCLK is the internal high frequency clock that is produced by the PLL circuitry from MCLK. The T AS5026 uses
the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode, 4 times
MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I
clock cycles are used to specify Interchannel delay and to detect when the MCLK is frequency is drifting.
Table 2–4 DCLK shows the relationship between Sample Rate, MCLK and DCLK.

TAS5026

47 nF

PLL_FLT_RET

4.7 nF

Figure 2–2. External PLL Loop Filter

2

C addressable registers, DCLK

Table 2–4. DCLK

FS

(kHz)

32 8.1920 65.5360 15.3

44.1 11.2896 90.3168 11.1
48 12.2880 98.3040 10.2
88 22.5280 90.1120 11.1
96 24.5760 98.3040 10.2

192 49.1520 98.3040 10.2

MCLK
(MHz)

DCLK
(MHz)

DCK Period

(ns)

2.1.7 Serial Data Interface

The T AS5026 operates as a slave only/receive only serial data interface in all modes. The TAS5026 has three
PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs. The
serial audio data is in MSB first; 2’s complement format.

The serial data interfaces of the T AS5026 can be configured in right justified, I
This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data sample
rates. The serial data interface format is specified using the data interface control register. The supported word
lengths are shown in Table 2–5.

During normal operating conditions if the serial data interface settings change state, an error recovery
sequence is initiated.

10

2

S, left-justified, or DSP modes.

SLES041B—November 2002TAS5026