TEXAS INSTRUMENTS TAS5015 Technical data

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TAS5015

SLES017 – SEPTEMBER 2001

TRUE DIGITAL AUDIO AMPLIFIER

TAS5015 DIGITAL AUDIO PWM PROCESSOR

FEATURES

TAS5015 Plus Discrete Back-End TDAA

System — High-Quality Digital Audio Amplification

D 112-dB Dynamic Range (TAS5015 Device) D THD+N < 0.01% D Power Efficiency Is 90% into 8-Ω Load D 16-, 20-, or 24-Bit Input Data D 44.1-kHz, 48-kHz, 88.2-kHz, 96-kHz, 176.4-kHz,

192-kHz Sampling Rates

D Economical 48-Pin TQFP Package D External PLL D 3.3-V Power Supply D Mute D Clicks and Pops Reduction (Patent Pending)

APPLICATIONS

High-Performance Digital Amplification For:

– Integrated Amplifiers – AV Receiver – Car Audio

DESCRIPTION

The true digital audio amplifier (TDAA) is a new paradigm in digital audio. One TDAA system consists of the TAS5015 PCM-PWM modulator device plus a discrete back-end TDAA power output. This system accepts a serial PCM digital audio stream and converts it to a 3.3-V PWM audio stream (TAS5015). The discrete back-end TDAA then provides a large-signal PWM output. This digital PWM signal is then demodulated, providing power output for driving loudspeakers. This patented technology provides low-cost, high-quality, high-efficiency digital audio applicable to many audio systems developed for the digital age. The TAS5015 is an innovative, cost-effective, high-performance 24-bit stereo PCM-PWM modulator based on Equibit technology. The T AS5015 has a wide variety of serial input options including right-justified (16, 20, or 24 bits), IIS (16, 20, or 24 bits), left-justified (16 bits), or DSP (16 bits) data formats. It is fully compatible with AES standard sampling rates (Fs) of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. The TAS5015 also provides a de-emphasis function for 44.1-kHz and 48-kHz sampling rates.

Digital Audio

• Digital Audio

Processor

• DSP

• S/PDIF

• 1394

• Volume

• EQ

• DRC

TAS5015

• Serial Audio Input Port

• External PLL

• Equibit Modulator

• Up to 192-kHz Sampling

• Bass

• Treble

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Equibit is a trademark of Toccata Technology ApS, Denmark.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Left

Right

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Discrete

Back-End

Discrete

Back-End

• H-Bridges

Power Devices

• Improved Performance

From TAS5100

L-C

Filter

L-C

Filter

TAS5015

SLES017 – SEPTEMBER 2001

terminal assignments

48-Pin TQFP PACKAGE

(TOP VIEW)

AVDD1

AVSS1NCNC

AVSS1

DEM_EN

DEM_SEL

FTEST

STEST

DBSPD

MUTE

DVSS3_L

references

47 46 45 44 4348 42 40 39 3841

MCLK_IN

AVDD2

AVSS2

HFCLK

RESET

PDN

VALID_R

M_S

DVDD1

NC NC

1 2 3 4 5 6 7 8 9 10 11 12

14 15

DVSS1

NC – No internal connection

DVSS1

DVDD1

17 18 19 20

SDIN

SCLK

LRCLK

MCLK_OUT

22 23 24

MOD2

MOD1

MOD0

VALID_L

DVDD3_L

PWM_AP_L

PWM_AM_L

34 33

PWM_BM_L

PWM_BP_L DVDD2

DVSS2

PWM_AP_R

PWM_AM_R

PWM_BM_R

PWM_BP_R

DVDD3_R

DVSS3_R

D T rue Digital Audio Amplifier TAS5100 PWM Power Output Stage – T exas Instruments publication SLLS419 D Design Considerations for TAS5000/TAS5110 True Digital Audio Power Amplifiers – Texas Instruments

publication SLAA117

D Digital Audio Measurements – Texas Instruments publication SLAA114 D PowerPAD Thermally Enhanced Package – Texas Instruments publication SLMA002

PowerPAD is a trademark of Texas Instruments.

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functional block diagram

TAS5015

SLES017 – SEPTEMBER 2001

LRCLK

SCLK

SDIN

Serial Audio

Port

Control Section

Audio Port

Configuration

MOD0

MOD1

MOD2

HFCLK

Generator

Interpolation

MUTE

DEM_EN

DEM_SEL

MCLK_IN

Clock

Digital

Filter

RESET

PDN

VALID_R

VALID_L

FTEST

STEST

MCLK_OUT

Equibit

Modulator

M_S

DVDD1

DBSPD

DVSS1

DVDD2

DVSS2

DVDD3_L

Buffer

DVSS3_L

DVSS3_R

DVDD3_R

AVSS1

AVDD1

AVSS2

AVDD2

PWM_AP_L PWM_AM_L PWM_BP_L PWM_BM_L

PWM_AP_R PWM_AM_R PWM_BP_R PWM_BM_R

AVAILABLE OPTIONS

0°C to 70°C TAS5015PFB

–40°C to 85°C TAS5015IPFB

NOTE: These packages are available taped and reeled. Add R suffix

to ordering number (e.g., TAS5015PFBR).

PACKAGE

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TAS5015

SLES017 – SEPTEMBER 2001

Terminal Functions

TERMINAL

NAME NO.

AVDD1 48 I Analog supply AVDD2 2 I Analog supply AVSS1 44, 47 I Analog ground AVSS2 5 I Analog ground DBSPD 39 I Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high DEM_EN 43 I De-emphasis enable, active high DEM_SEL 42 I De-emphasis select (0 = 44.1 kHz, 1 = 48 kHz) DVDD1 12, 14 I Digital voltage supply for logic DVDD2 31 I Digital voltage supply for PWM reclocking DVDD3_L 36 I Digital voltage supply for PWM output (left) DVDD3_R 25 I Digital voltage supply for PWM output (right) DVSS1 13, 15 I Digital ground for logic DVSS2 30 I Digital ground for PWM reclocking DVSS3_L 37 I Digital ground for PWM output (left) DVSS3_R 24 I Digital ground for PWM output (right) FTEST 41 I Tied to DVSS1 for normal operation HFCLK 6 I External PLL clock input LRCLK 18 I/O Left/right clock (input when M_S = 0; output when M_S = 1) MCLK_IN 1 I MCLK input MCLK_OUT 16 O Buffered system clock output if M_S = 1; otherwise set to 0 MOD0 22 I Serial interface selection pin, bit 0 MOD1 21 I Serial interface selection pin, bit 1 MOD2 20 I Serial interface selection pin, bit 2 (MSB) M_S 10 I Master/slave, master=1, slave=0 MUTE 38 I Muted signal = 0, normal mode = 1 NC 3, 4, 11, 45,

46 PDN 8 I Power down, active low PWM_AM_L 34 O PWM left output A (differential –) PWM_AM_R 28 O PWM right output A (differential –) PWM_AP_L 35 O PWM left output A (differential +) PWM_AP_R 29 O PWM right output A (differential +) PWM_BM_L 33 O PWM left output B (differential –) PWM_BM_R 27 O PWM right output B (differential –) PWM_BP_L 32 O PWM left output B (differential +) PWM_BP_R 26 O PWM right output B (differential +) RESET 7 I Reset (active low) SCLK 17 I/O Shift clock (input when M_S = 0, output when M_S = 1) SDIN 19 I Stereo serial audio data input STEST 40 I T ied to DVSS1 for normal operation VALID_L 23 O PWM left outputs valid (active high) VALID_R 9 O PWM right outputs valid (active high)

I/O

DESCRIPTION

No connection

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External PLL, master, normal

External PLL, slave, normal s eed

SLES017 – SEPTEMBER 2001

functional description

serial audio port

The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin), and a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 44.1-kHz, 48-kHz,

88.2-kHz, 96-kHz, 176.4-kHz, or 192-kHz stereo). See the serial interface formats section.

system clocks—master mode and slave mode

The TAS5015 allows multiple system clocking schemes. Master mode indicates that the TAS5015 provides system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 128 Fs MCLK_OUT (quad speed), 64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode. Slave mode indicates that a system master other than the TAS5015 provides system clocks (LRCLK, SCLK, and MCLK_IN) to the TAS5015 (M_S = 0). The TAS5015 operates with LRCLK and SCLK synchronized to MCLK. The TAS5015 does not require any specific phase relationship between LRCLK and MCLK, but there must be synchronization. In the slave mode, MCLK_OUT is driven low. Table 1 shows all the possible master and slave modes.

sampling frequency

The normal sampling frequency is either 1 1.2896 MHz (Fs = 44.1 kHz) or 12.288 MHz (Fs = 48 kHz). T wice the normal sampling frequency can be selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz or Fs = 96 kHz. In the double-speed slave mode (DBSPD = 1, M_S = 0), the external clock input is either

22.5796 MHz (Fs = 88.2 kHz) or 24.576 MHz (Fs = 96 kHz). Table 1 explains the proper clock selection.

TAS5015

Table 1. External Clock and External PLL Functions

DESCRIPTION M_S DBSPD DEM_EN DEM_SEL

External PLL, master, normal speed (see Notes 1 and 2)

External PLL, master, double speed (see Notes 1 and 2)

External PLL, master, double speed (see Note 1 and 2)

External PLL, master, quad speed (see Notes 1 and 2)

External PLL, slave, normal speed (see Notes 3, 4, and 5)

NOTES: 1. SCLK and LRCLK are outputs

2. MCLK_IN tied LOW

3. External MCLK connected to MCLK_IN input

4. SCLK and LRCLK are inputs

5. MCLK_OUT is a buffered version of the external MCLK input

1 0

1 1 0 0 – 90.3168 5.6448 88.2 22.5792

1 1 0 0 – 98.304 6.144 96 24.576

1 0 0 1 – 90.3168 11.2896 176.4 22.5792

1 0 0 1 – 98.304 12.288 192 24.576

0 0

0 0 1 0 1 1 0 0

MCLK_IN

(MHz)

– 90.3168 2.8224 44.1 11.2896

– 98.304 3.072 48 12.288

11.2896 90.3168 2.8224 44.1 11.2896

12.288 98.304 3.072 48 12.288

HFCLK

(MHz)

SCLK (MHz)

LRCLK

(KHz)

MCLK_OUT

(MHz)

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TAS5015

SLES017 – SEPTEMBER 2001

functional description (continued)

Table 1. External Clock and External PLL Functions (Continued)

DESCRIPTION M_S DBSPD DEM_EN DEM_SEL

External PLL, slave, double speed (see Notes 3, 4, and 5)

External PLL, slave, quad speed (see Notes 3, 4, and 5)

NOTES: 3. External MCLK connected to MCLK_IN input

4. SCLK and LRCLK are inputs

5. MCLK_OUT is a buffered version of the external MCLK input

0 1 0 0 22.5792 90.3168 5.6448 88.2 22.5792

0 1 0 0 24.576 98.304 6.144 96 24.576

0 0 0 0 22.5792 90.3168 11.2896 176.4 22.5792

0 0 0 0 24.576 98.304 12.288 192 24.576

MCLK_IN

(MHz)

HFCLK

(MHz)

SCLK (MHz)

LRCLK

(kHz)

external PLL

For the highest system performance, an external PLL must be used with the T AS5015. For normal-speed mode, the external PLL input (HFCLK) must be 2048 Fs, for double-speed mode HFCLK must be 1024 Fs, and for quad-speed mode HFCLK must be 512 Fs.

digital interpolation filter

The 24-bit high-performance linear phase FIR interpolation filter up-samples the input digital data at a rate of two times (quad-speed mode = 176.4 kHz or 192 kHz), four times (double-speed mode = 88.2 kHz or 96 kHz), or eight times (normal mode = 44.1 kHz or 48 kHz) the incoming sample rate. This filter provides low pass-band ripple and optimized time domain transient response for accurate music reproduction.

digital PWM modulator

MCLK_OUT

(MHz)

The interpolation filter output is sent to the digital PWM modulator. This modulator consists of a highperformance fourth order digital-noise shaper and a PCM-to-PWM converter. Following the noise shaper, the PCM signal is fed into a low distortion PCM-to-PWM conversion block, buffered, and output from the chip. The modulation scheme is based on a 2-state control of the H-bridge output.

control, status, and operational modes

The T AS5015 control section consists of several control-input pins. Three serial mode pins (MOD0, MOD1, and MOD2) are provided to select various serial data formats. During normal operating conditions if any of the MOD0, MOD1, or MOD2 pins changes state, a reset sequence is initiated. Also provided are separate power-down (PDN

), reset (RESET), and mute (MUTE) pins.

power up

At power up, the V ALID_L and V ALID_R pins are asserted low and the PWM outputs go to the hard mute state in which the P outputs are held low and the M outputs are held high. Following initialization, the T AS5015 comes up in the operational state (differential PWM audio). There are two cases of power-up timing. The first case is shown in Figure 1 with RESET RESET

preceding PDN. The second case is shown in Figure 2 with PDN preceding

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functional description (continued)

RESET

PDN

VALID_L

VALID_R

Figure 1. Power-Up Timing (RESET Preceding PDN)

Greater Than 16 MCLK Periods

RESET

PDN

VALID_L

VALID_R

TAS5015

SLES017 – SEPTEMBER 2001

Initialization Time = 100 ms max

Initialization Time = 5 ms max

Figure 2. Power-Up Timing (PDN Preceding RESET)

reset

The reset signal for the TAS5015 must be applied whenever toggling the M_S, DBSPD signal. This reset is asynchronous. See Figure 3 for reset timing. To initiate the reset sequence the RESET

pin is asserted low. As long as the pin is held low the chip is in the reset state. During this reset time, the PWM outputs are hard-muted (P-outputs held low and M-outputs held high) and the PWM outputs valid pins (VALID_L. VALID_R) are held low. Assuming PDN

is high, the rising edge of the reset pulse begins chip initialization. After the initialization

time, the TAS5015 begins normal operation.

RESET

5 ms max

VALID_L

VALID_R

Normal Operation

PDN

Initialization

Normal

Operation

Figure 3. Reset Timing

power down

Note that power down is an asynchronous operation. To place the device in total power-down mode, both RESET

and PDN must be held low. As long as these pins are held low , the chip is in the power-down state and the PWM outputs are hard muted with the P outputs held low and the M outputs held high. To place the device back into normal mode, see the power up section.

NOTE:

In order for the dynamic logic to be properly powered down, the clocks should not be stopped before the PDN

pin goes low. Otherwise, the device may drain additional supply current.

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TAS5015

SLES017 – SEPTEMBER 2001

functional description (continued)

PDN

and RESET

VALID

Normal

Operation

Chip

Initialization

Power-Down

Normal Operation

Figure 4. Power-Down Timing

mute

The T AS5015 provides a mute function that is used when the MUTE

pin is asserted low. See Table 2 for mute description. This mute is a quiet mute; that is, the mute is accomplished by outputting a zero value waveform in which both sides of the differential PWM outputs have a 50% duty cycle (see Figure 5 for mute timing).

Table 2. Mute Description

MUTE P OUTPUTS M OUTPUTS DESCRIPTION

0 50% duty cycle 50% duty cycle Mute 1 DATA DATA Normal operation

10 µs max

MUTE

5 ms max

VALID_L

Initialization

VALID_R

PWM Outputs

50–50 Duty Cycle

(P, M Complementary)

Inactive State

Normal State

(P, M Complementary)

Figure 5. Mute Timing

double speed

Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz. In order to put the T AS5015 in double-speed mode with the device in normal operating conditions, the RESET switching the DBSPD pin high. After the RESET

pin is brought high again, a reset sequence takes place. If the

pin must be held low while

change is at power up, a power-up sequence is originated.

quad speed

Quad-speed mode is used to support sampling rates of 176.4 kHz and 192 kHz. In order to put the TAS5015 in quad-speed slave mode, M_S and DBPSB pins are brought low. Quad-speed mode is then automatically detected due to the fact that it is the only mode in which MCLK_IN is 128 Fs. DEM_SEL must be set to low when operating in the quad-speed slave mode. For quad-speed master mode M_S = 1, DBSPD = 0, DEM_SEL = 1, and DEM_EN = 0.

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SLES017 – SEPTEMBER 2001

functional description (continued)

de-emphasis filter

For audio sources that have been preemphasized, a precision 50 µs/15 µs de-emphasis filter is provided to support the sampling rates of 44.1 kHz and 48 kHz. Pins DEM_SEL and DEM_EN select the de-emphasis functions. See Figure 6 for a graph showing the de-emphasis filtering characteristics. See Table 3 for de-emphasis selection.

De-emphasis

–10

Response – dB

3.18 (50 µs) 10.6 (15 µs)

f – Frequency – kHz

Figure 6. De-Emphasis Filter Characteristics

de-emphasis selection

De-emphasis selection is accomplished by using the DEM_SEL and DEM_EN pins. See Table 3 for de-emphasis selection description.

TAS5015

Table 3. De-Emphasis Selection

DEM_SEL DEM_EN DESCRIPTION

0 0 De-emphasis disabled 0 1 De-emphasis enabled for Fs = 44.1 kHz 1 1 De-emphasis enabled for Fs = 48 kHz 1 0 Disallowed state. Do not use.

error status reporting (VALID_L and VALID_R)

The following is a list of the error conditions that will cause the V ALID_L and VALID_R pins to be asserted low.

– No clocks – Clock phase errors

When either of the above conditions is met, the VALID_L and VALID_R goes low and the PWM outputs go to the hard mute state. If the error condition is removed, the T AS5015 is reinitialized and the VALID_L and V ALID_R pins are asserted high.

serial interface formats

The TAS5015 is compatible with eight different serial interfaces. Available interface options are IIS, right justified, left justified, and DSP frame. T able 4 indicates how these options are selected using the MOD0, MOD1, and MOD2 pins.

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TAS5015

SLES017 – SEPTEMBER 2001

functional description (continued)

Table 4. Hardware Selection of Serial Audio Modes

MODE MOD2 PIN MOD1 PIN MOD0 PIN

0 0 0 0 16-bit, MSB first; right justified 1 0 0 1 20-bit, MSB first; right justified 2 0 1 0 24-bit, MSB first; right justified 3 0 1 1 16-bit IIS 4 1 0 0 20-bit IIS 5 1 0 1 24-bit IIS 6 1 1 0 16-bit MSB first, left justified 7 1 1 1 16-bit DSP frame

SERIAL INTERFACE

SDIN

The following figures illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the different interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded with binary 0s.

MSB first, right-justified (for 16, 20, 24 bits)

SCLK

LRCLK = f

SDIN

X MSB LSB MSB LSB

Left Channel Right Channel

Figure 7. MSB First Right Justified

Note the following characteristics of this protocol.

– Left channel is received when LRCLK is high. – Right channel is received when LRCLK is low. – SDIN is sampled at the rising edge of SCLK.

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functional description (continued)

IIS compatible serial format (for 16, 20, 24 bits)

SCLK

TAS5015

SLES017 – SEPTEMBER 2001

LRCLK = f

SDIN

X MSB LSB X MSB LSB

Left Channel Right Channel

Figure 8. IIS Compatible Serial Format

Note the following characteristics of this protocol.

– Left channel is received when LRCLK is low. – Right channel is received when LRCLK is high. – SDIN is sampled with the rising edge of the SCLK.

MSB left-justified serial interface format (for 16 bits)

SCLK

LRCLK = f

SDIN

MSB LSB MSB LSB

Left Channel Right Channel

Figure 9. MSB Left-Justified Serial Interface Format

Note the following characteristics of this protocol.

– Left channel is received when LRCLK is high. – Right channel is received when LRCLK is low. – SDIN is sampled at the rising edge of SCLK.

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TAS5015

SLES017 – SEPTEMBER 2001

functional description (continued)

DSP compatible serial interface format (for 16 bits)

SCLK

LRCLK = f

SDIN

15 14 13 0 15 14 13 0

Left Channel

(MSB = 15)

Right Channel

(MSB = 15)

Figure 10. DSP Compatible Serial Interface Format

Note the following characteristic of this protocol.

– Serial data is sampled with the falling edge of SCLK.

PWM Outputs

The T AS5015 is designed to be used with a discrete back-end. The T AS5015 PWM outputs provide differential

3.3-V square-wave signals. During normal operation these outputs represent the input PCM audio in the pulse-width modulation scheme. In the hard-mute state the P outputs (PWM_AP_L, PWM_BP_L, PWM_AP_R, and PWM_BP_R) are held low and the M outputs (PWM_AM_L, PWM_BM_L, PWM_AM_R, and PWM_BM_R) are held high. In the quiet-mute state the differential PWM outputs have a 50% duty cycle.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Analog supply voltage range, AVDD1, AVDD2 –0.3 V to 4.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital power supply voltage, DVDD1, DVDD2, DVDD3_L, DVDD3_R –0.3 V to 4.2 V. . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage, V Operating free-air temperature, T Storage temperature, T

(see Note 6) –0.3 V to DVDDX + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESD 2000 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: DVDD1, DVDD2, DVDD3_L, DVDD3_R.

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SLES017 – SEPTEMBER 2001

TAS5015

recommended operating conditions, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ±10%, A VDD1 = A VDD2 = 3.3 V ±10%, Fs = 44.1 kHz

MIN TYP MAX UNIT

Supply voltage

Supply current

Power dissipation

†

DVDD1, DVDD2, DVDD3_L, DVDD3_R

‡

If the clocks are turned off

AVDD1, AVDD2

Digital DVDDX Analog AVDDX

Digital

Analog

Digital

Analog

†

Operating 22 mA Power down Operating 1 mA Power down Operating 59.4 mW Power down Operating 3.3 mW Power down

‡

3 3.3 3.6 V

10 20 µA

10 100 µA

6.6 72 µW

33 360 µW

electrical characteristics, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = 3.3 V ±10%, AVDD1 = AVDD2 = 3.3 V ±10%

static digital specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level input voltage 2 DVDD1 V Low-level input voltage 0 0.8 V High-level output voltage IO = –1 mA 2.4 V Low-level output voltage IO = 4 mA 0.4 V Input leakage current –10 10 µA

digital interpolation filter and PWM modulator, Fs = 44.1 kHz

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Pass band 0 20 kHz Pass-band ripple ±0.012 dB Stop band 24.1 kHz Stop-band attenuation 24.1 kHz to 152.3 kHz 50 dB Group delay 700 µS PWM modulation index (gain) 0.93 dB

TAS5015/TAS5110 system performance measured at the speaker terminals

See the Design Consideration for TAS5000/TAS5100 True Digital Audio Power Amplifiers application note, Texas Instruments literature number SLAA117 for values.

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TAS5015

SLES017 – SEPTEMBER 2001

switching characteristics, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = AVDD1 = AVDD2 = 3.3 V ±10%

serial audio ports slave mode

PARAMETER MIN TYP MAX UNIT

(SCLK)

su(SDIN)

h(SDIN)

(LRCLK)

su(LRCLK)

serial audio ports master mode, CL = 50 pF

(MSD)

(MLRD)

SCLK frequency 12.288 MHz SDIN setup time before SCLK rising edge 20 ns SDIN hold time from SCLK rising edge 10 ns LRCLK frequency 44.1 48 192 kHz MCLK duty cycle 50% SCLK duty cycle 50% LRCLK duty cycle 50%

LRCLK edge setup before SCLK rising edge 20 ns

PARAMETER MIN TYP MAX UNIT

MCLK to SCLK 0 5 ns MLCK to LRCLK 0 5 ns

DSP serial interface mode

(SCLK)

w(FSHIGH)

su(SDIN)

su(LRCLK)

h(SDIN)

h(LRCLK)

SCLK frequency 12.288 MHz Pulse duration, sync 1/(64×fs) ns

SDIN and LRCLK setup time before SCLK falling edge 20 ns

SDIN and LRCLK hold time from SCLK falling edge 10 ns SCLK duty cycle 50%

PARAMETER MIN TYP MAX UNIT

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SLES017 – SEPTEMBER 2001

TAS5015

PARAMETER MEASUREMENT INFORMATION

SCLK

h(SDIN)

SDIN

su(SDIN)

Figure 11. Right-Justified, IIS, Left-Justified Serial Protocol Timing

SCLK

su(LRCLK)

LRCLK

NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns)

Figure 12. Right, Left, and IIS Serial Mode Timing Requirement

SCLK

LRCLK

(Output)

(MSD)

(MLRD)

MCLK

(Output)

SCLK

LRCLK

SDIN

Figure 13. Serial Audio Ports Master Mode Timing

su(LRCLK)

w(FSHIGH)

su(SDIN)

h(LRCLK)

Figure 14. DSP Serial Port Timing

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h(SDIN)

TAS5015

SLES017 – SEPTEMBER 2001

SCLK

LRCLK

w(FSHIGH)

PARAMETER MEASUREMENT INFORMATION

64 SCLK

SDIN

16-Bit Left Channel Data 16-Bit Left Channel Data 16-Bit Left Channel Data32-Bit Ignore

Figure 15. DSP Serial Port Expanded Timing

SCLK

su(SDIN)

SDIN

NOTE: Serial data is sampled with the falling edge of SCLK (setup time = 20 ns and hold time = 10 ns)

= 20 ns

h(SDIN)

= 10 ns

Figure 16. DSP Absolute Timing Requirement

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SLES017 – SEPTEMBER 2001

TAS5015

APPLICATION INFORMATION

TAS5015

3.3 V DIG

External

PLL

Audio

Source

Clock

Generator

DEM_SEL DEM_EN DBSPD SDIN

LRCLK SCLK MCLK_IN

MOD0 MOD1

MOD2

M_S

HFCLK

PWM_AP_L

PWM_AM_L

PWM_BP_L

PWM_BM_L

VALID_L

PWM_AP_R

PWM_AM_R

PWM_BP_R

PWM_BM_R

VALID_R

RESET

MUTE

PDN

Discrete

Back-End

RESET

Discrete

Back-End

RESET

System

Controller

FTEST STEST

NOTE A: See the Design Consideration for TAS5000/T AS5100 True Digital Audio Power Amplifiers application note, T exas Instruments literature

number SLAA1 17 for values.

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TAS5015

SLES017 – SEPTEMBER 2001

MECHANICAL DATA

PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK

1,05 0,95

0,50

0,27 0,17

5,50 TYP

7,20

6,80 9,20

8,80

0,08

0,05 MIN

Seating Plane

0,13 NOM

Gage Plane

0,25

0°–ā7°

0,75 0,45

1,20 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

0,08

4073176/B 10/96

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TEXAS INSTRUMENTS TAS5015 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual