D96-dB Dynamic Range (TAS5010 Device)
D93-dB Dynamic Range (TAS5010 & TAS5100
System Measured at Speaker Terminals)
DTHD+N < 0.08% (1 kHz, 1 to 30W RMS into 6 Ω)
DPower Efficiency Is 90% Into 8-Ω Load
D16-, 20-, or 24-Bit Input Data
D44.1-kHz, 48-kHz, 88.2-kHz, 96-kHz, 176.4-kHz,
192-kHz Sampling Rates
DEconomical 48-Pin TQFP Package
DLower-Jitter Internal PLL
D3.3-V Power Supply
DMute
DClicks and Pops Reduction (Patent Pending)
APPLICATIONS
DVD-Audio
D
DHome Theater
DCar Audio Amplifiers and Head Units
DInternet Music Appliance
DMini/Micro Component Systems
DESCRIPTION
The true digital audio amplifier (TDAA) is a new
paradigm in digital audio. One TDAA system consists of
the TAS5010 PCM-PWM modulator device + a
TAS5100 PWM power output device. This system
accepts a serial PCM digital audio stream and converts
it to a 3.3-V PWM audio stream (TAS5010). The
TAS5100 device then provides a large-signal PWM
output. This digital PWM signal is then demodulated
providing power output for driving loudspeakers. This
patented technology provides low-cost, high-quality,
high- efficiency digital audio applicable to many audio
systems developed for the digital age. The T AS5010 is
an innovative, cost-effective, high-performance 24-bit
stereo PCM-PWM modulator based on Equibit
technology. It has a wide variety of serial input options
including right-justified (16, 20, or 24 bits), IIS (16, 20,
or 24 bits), left-justified (16 bits), or DSP (16 bits) data
formats. It is fully compatible with AES standard
sampling rates of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. The T AS5010 also provides a
de-emphasis function for 44.1-kHz and 48-kHz
sampling rates.
Digital Audio
• TAS3001
• DSP
TAS5010
• S/PDIF
• 1394
• Serial Audio Input Port
• Volume
• EQ
• DRC
• Internal PLL
• Equibit Modulator
• Up to 192-kHz Sampling
• Bass
• Treble
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Equibit is a trademark of Toccata Technology ApS, Denmark.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Left
Right
www.ti.com
TAS5100
TAS5100
• H-Bridges
Power Devices
L-C
Filter
L-C
Filter
Copyright 2001, Texas Instruments Incorporated
1
TAS5010
SLAS328 – SEPTEMBER 2001
terminal assignments
48-Pin TQFP PACKAGE
(TOP VIEW)
AVDD1
XTL_IN
XTL_OUT
OSC_CAP
AVSS1
DEM_EN
DEM_SEL
FTEST
STEST
DBSPD
MUTE
DVSS3_L
references
MCLK_IN
AVDD2
PLL_FLT_OUT
PLL_FLT_RET
AVSS2
RESET
PDN
VALID_R
M_S
DVDD1
NC – No internal connection
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
47 46 45 44 43484240 39 3841
14 15
DVSS1
16
DVSS1
DVDD1
17 18 19 20
SCLK
LRCLK
MCLK_OUT
SDIN
MOD2
22 23 24
21
MOD1
37
MOD0
VALID_L
DVDD3_L
36
PWM_AP_L
35
PWM_AM_L
34
33
NC
32
NC
DVDD2
31
DVSS2
30
PWM_AP_R
29
PWM_AM_R
28
NC
27
NC
26
DVDD3_R
25
DVSS3_R
DTrue Digital Audio Amplifier TAS5100 Power Output Stage – Texas Instruments publication SLLS419A
DDesign Considerations for TAS5000/TAS5100 True Digital Audio Power Amplifiers – Texas Instruments
These packages are available taped and reeled. Add an R suffix to
device type (e.g., TAS5010PFBR).
FTEST
RESET
0°C to 70°CTAS5010PFB
STEST
AVAILABLE OPTIONS
T
A
M_S
DBSPD
Equibit
Modulator
DVDD1
DVSS1
DVDD2
OSC
DVSS2
DVSS3_L
DVDD3_L
PACKAGE
Buffer
AVDD1
DVSS3_R
DVDD3_R
†
AVSS1
AVSS2
AVDD2
PWM_AP_L
PWM_AM_L
PWM_AP_R
PWM_AM_R
www.ti.com
3
TAS5010
SLAS328 – SEPTEMBER 2001
Terminal Functions
TERMINAL
NAMENO.
AVDD148IAnalog supply for oscillator
AVDD22IAnalog supply for PLL
AVSS144IAnalog ground for oscillator
AVSS25IAnalog ground for PLL
DBSPD39IIndicates sample rate is double speed (88.2 kHz or 96 kHz), active high
DEM_EN43IDe-emphasis enable, active high
DEM_SEL42IDe-emphasis select (0 = 44.1 kHz, 1 = 48 kHz)
DVDD112, 14IDigital voltage supply for logic
DVDD231IDigital voltage supply for PWM reclocking
DVDD3_L36IDigital voltage supply for PWM output (left)
DVDD3_R25IDigital voltage supply for PWM output (right)
DVSS113, 15IDigital ground for logic
DVSS230IDigital ground for PWM reclocking
DVSS3_L37IDigital ground for PWM output (left)
DVSS3_R24IDigital ground for PWM output (right)
FTEST41ITied to DVSS1 for normal operation
LRCLK18I/OLeft/right clock (input when M_S = 0; output when M_S = 1)
MCLK_IN1IMCLK input
MCLK_OUT16OBuffered system clock output if M_S = 1; otherwise set to 0
MOD022ISerial interface selection pin, bit 0
MOD121ISerial interface selection pin, bit 1
MOD220ISerial interface selection pin, bit 2 (MSB)
M_S10IMaster/slave, master=1, slave=0
MUTE38IMuted signal = 0, normal mode = 1
NC6, 11, 26,
27, 32, 33
OSC_CAP45IOscillator cap return
PDN8IPower down, active low
PLL_FLT_OUT3OOutput terminal for external PLL filter
PLL_FLT_RET4IReturn for external PLL filter
PWM_AM_L34OPWM left output (differential –)
PWM_AM_R28OPWM right output (differential –)
PWM_AP_L35OPWM left output (differential +)
PWM_AP_R29OPWM right output (differential +)
RESET7IReset (active low)
SCLK17I/OShift clock (input when M_S = 0, output when M_S = 1)
SDIN19IStereo serial audio data input
STEST40ITied to DVSS1 for normal operation
VALID_L23OPWM left outputs valid (active high)
VALID_R9OPWM right outputs valid (active high)
XTL_IN47ICrystal or clock input (MCLK input)
XTL_OUT46OCrystal output (not for external usage).NC when XTL_IN is MCLK input
I/O
DESCRIPTION
No connection
4
www.ti.com
SLAS328 – SEPTEMBER 2001
functional description
serial audio port
The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin),
and a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 44.1 kHz, 48 kHz,
88.2 kHz, 96 kHz, 176.4kHz, or 192kHz) stereo. See serial interface formats section.
system clocks—master mode and slave mode
The TAS5010 allows multiple system clocking schemes. In this document, master mode indicates that the
T AS5010 provides system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 256Fs
MCLK_OUT , 64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode. Slave
mode indicates that a system master other than the TAS5010 provides system clocks (LRCLK, SCLK, and
MCLK_IN) to the T AS5010 (M_S = 0). The TAS5010 operates with LRCLK and SCLK synchronized to MCLK.
TAS5010 does not require any specific phase relationship between LRCLK and MCLK, but there must be
synchronization. In the slave mode MCLK_OUT is driven low. Table 1 shows all the possible master and slave
modes. When operating in quad mode (Fs = 176.4kHz or 192 kHz), the device works in slave mode only with
MCLK_IN = 128 Fs.
oscillator/sampling frequency
The sampling frequency is determined by the crystal (master mode) or master clock in (slave mode) which
should be either 11.2896 MHz (Fs = 44.1 kHz) or 12.288 MHz (Fs = 48 kHz). Twice the normal sampling
frequency can be selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz or Fs = 96 kHz. In the
double-speed slave mode (DBSPD = 1, M_S = 0), the external clock input is either 22.5796 MHz (Fs = 88.2 kHz)
or 24.576 MHz (Fs = 96 kHz). Table 1 explains the proper clock selection.
TAS5010
Table 1. Oscillator, External Clock, and PLL Functions
DESCRIPTIONM_SDBSPD
Master, normal speed1011.2896—2.822444.111.2896
Master, normal speed1012.288—3.0724812.288
Master, double speed11—22.5792
Master, double speed11—24.576
Slave, normal speed00—11.2896
Slave, normal speed00—12.288
Slave, double speed01—22.5792
Slave, double speed01—24.576
Slave, quad speed
Slave, quad speed
†
Either a crystal oscillator or an external clock of the specified frequency can be connected to XTL_IN.
‡
MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN is provided.
§
External MCLK connected to MCLK_IN input
¶
SCLK and LRCLK are outputs when M_S=1, inputs when M_S=0.
#
MCLK_OUT is driven low when M_S=0.
||
Quad speed mode is detected automatically.
||
||
00—22.5792§11.2896176.4Digital GND
00—24.576
XTL_IN
(MHz)
†
MCLK_IN
‡
(MHz)
SCLK
(MHz)
§
5.644888.222.5792
§
§
2.822444.1Digital GND
§
§
5.644888.2Digital GND
§
§
12.288192Digital GND
LRCLK
¶
6.1449624.576
3.07248Digital GND
6.14496Digital GND
(kHz)
¶
MCLK_OUT
(MHz)
phase-locked loop (PLL)/clock generation
A low jitter PLL is incorporated for internal use. Connections for the PLL external loop filter are provided as
PLL_FL T_RET and PLL_FL T_OUT . If the PLL loses lock, the PWM output status pins (V ALID_L and V ALID_R)
go low. Note that VALID_L and VALID_R can go low for other conditions as well. See error status reporting
section.
#
www.ti.com
5
TAS5010
SLAS328 – SEPTEMBER 2001
functional description (continued)
digital interpolation filter
The 24-bit high-performance linear phase FIR interpolation filter up-samples the input digital data at a rate of
2 times (quad speed mode = 176.4kHz or 192kHz), 4 times (double speed mode = 88.2 kHz or 96 kHz), or 8
times (normal mode = 44.1 kHz or 48 kHz) the incoming sample rate. This filter provides very low pass-band
ripple and optimized time domain transient response for accurate music reproduction.
digital PWM modulator
The interpolation filter output is sent to the modulator. This modulator consists of a high performance fourth order
digital noise shaper and a PCM-to-PWM converter. Following the noise shaper , the PCM signal is fed into a very
low distortion PCM-to-PWM conversion block, buffered, and output from the chip. The modulation scheme is
based on a 2-state control of the H-bridge output.
control, status, and operational modes
The T AS5010 control section consists of several control-input pins. Three serial mode pins (MOD0, MOD1, and
MOD2) are provided to select various serial data formats. During normal operating conditions if any of the
MOD0, MOD1, or MOD2 pins changes state, a reset sequence is initiated. Also provided are separate
power-down (PDN
), reset (RESET), and mute (MUTE) pins.
power up
At power up the V ALID_L and VALID_R pins are asserted low and the PWM outputs go to the hard mute state
in which the P outputs are held low and the M outputs are held high. Following initialization, the T AS5010 comes
up in the operational state (differential PWM audio). There are two cases of power-up timing. The first case is
shown in Figure 1 with RESET
RESET
.
RESET
PDN
VALID_L
VALID_R
preceding PDN. The second case is shown in Figure 2 with PDN preceding
Initialization Time = 100 ms max
Figure 1. Power-Up Timing (RESET Preceding PDN)
Greater Than 16 MCLK Periods
RESET
PDN
Initialization Time = 5 ms max
VALID_L
VALID_R
Figure 2. Power-Up Timing (PDN Preceding RESET)
6
www.ti.com
SLAS328 – SEPTEMBER 2001
functional description (continued)
reset
The reset signal for the TAS5010 must be applied whenever toggling the M_S, DBSPD signal. This reset is
asynchronous. See Figure 3 for reset timing. To initiate the reset sequence the RESET
long as the pin is held low the chip is in the reset state. During this reset time the PWM outputs are hard-muted
(P-outputs held low and M-outputs held high) and the PWM outputs valid pins (VALID_L. VALID_R) are held
low. Assuming PDN
is high, the rising edge of the reset pulse begins chip initialization. After the initialization
time, the TAS5010 begins normal operation.
RESET
pin is asserted low. As
TAS5010
5 ms max
VALID_L
VALID_R
Normal Operation
PDN
Initialization
Normal
Operation
Figure 3. Reset Timing
power down
When PDN is low (see Figure 4), both the PLL and the oscillator are shut down. Note that power down is an
asynchronous operation. To place the device in total power-down mode, both RESET
and PDN must be held
low. As long as these pins are held low , the chip is in the power-down state and the PWM outputs are hard muted
with the P outputs held low and the M outputs held high. to place the device back into normal mode, see the
power up section.
NOTE:
In order for the dynamic logic to be properly powered down, the clocks should not be stopped before
the PDN pin goes low. Otherwise, the device may drain additional supply current.
VALID
Normal
Operation
Chip
Initialization
Power-Down
Normal Operation
PDN
and RESET
Figure 4. Power-Down Timing
mute
The T AS5010 provides a mute function that is used when the MUTE
pin is asserted low. See Table 2 for mute
description. This mute is a quiet mute; that is, the mute is accomplished by outputting a zero value waveform
in which both sides of the differential PWM outputs have a 50% duty cycle (see Figure 5 for mute timing.
Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz. In order to put the T AS5010 in
double-speed mode with the device in normal operating conditions, the RESET
switching the DBSPD pin high. After the RESET
pin is brought high again, a reset sequence takes place. If the
change is at power up, a power-up sequence is originated.
Initialization
Normal State
(P, M Complementary)
pin must be held low while
quad speed
Quad-speed mode is used to support sampling rates of 176.4 kHz and 192 kHz. It is supported in slave mode
only. In order to put the TAS5010 in quad-speed mode, M_S and DBPSB pins are brought low. Quad-speed
mode is then automatically detected due to the fact that it is the only mode in which MCLK_IN is 128Fs.
de-emphasis filter
For audio sources that have been preemphasized, a precision 50 µs/15 µs de-emphasis filter is provided to
support the sampling rates of 44.1 kHz and 48 kHz. Pins DEM_SEL and DEM_EN select the de-emphasis
functions. See Figure 6 for a graph showing the de-emphasis filtering characteristics. See Table 3 for
de-emphasis selection.
0
De-emphasis
–10
Response – dB
3.18 (50 µs)10.6 (15 µs)
f – Frequency – kHz
Figure 6. De-Emphasis Filter Characteristics
8
www.ti.com
SLAS328 – SEPTEMBER 2001
functional description (continued)
de-emphasis selection
De-emphasis selection is accomplished by using the DEM_SEL and DEM_EN pins. See Table 3 for
de-emphasis selection description.
Table 3. De-Emphasis Selection
DEM_SELDEM_ENDESCRIPTION
00De-emphasis disabled
01De-emphasis enabled for Fs = 44.1 kHz
11De-emphasis enabled for Fs = 48 kHz
10Forbidden modey. Do not use.
error status reporting (VALID_L and VALID_R)
The following is a list of the error conditions that will cause the V ALID_L and V ALID_R pins to be asserted low:
DNo clocks
TAS5010
DClock phase errors
When either of the above conditions is met, the VALID_L and VALID_R goes low and the PWM outputs go to
the hard mute state. If the error condition is removed, the T AS5010 is reinitialized and the VALID_L and V ALID_R
pins are asserted high.
serial interface formats
The TAS5010 is compatible with eight different serial interfaces. Available interface options are IIS, right
justified, left justified, and DSP frame. T able 4 indicates how these options are selected using the MOD0, MOD1,
and MOD2 pins.
000016 bit, MSB first; right justified
100120 bit, MSB first; right justified
201024 bit, MSB first; right justified
301116 bit IIS
410020 bit IIS
510124 bit IIS
611016 bit MSB first, left justified
711116 bit DSP frame
The following figures illustrate the relationship between the SCLK, LRCLK and the serial data I/O for the different
interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded with
binary 0s.
www.ti.com
9
TAS5010
SLAS328 – SEPTEMBER 2001
functional description (continued)
MSB first, right-justified (for 16, 20, 24 bits)
SCLK
LRCLK = f
SDIN
s
XMSBLSBMSBLSB
Left ChannelRight Channel
Figure 7. MSB First Right Justified
Note the following characteristics of this protocol:
–Left channel is received when LRCLK is high.
–Right channel is received when LRCLK is low.
–SDIN is sampled at the rising edge of SCLK.
IIS compatible serial format (for 16, 20, 24 bits)
SCLK
LRCLK = f
SDIN
s
XMSBLSBXMSBLSB
X
Left ChannelRight Channel
Figure 8. IIS Compatible Serial Format
Note the following characteristics of this protocol:
–Left channel is received when LRCLK is low.
–Right channel is received when LRCLK is high.
–SDIN is sampled with the rising edge of the SCLK.
10
www.ti.com
functional description (continued)
MSB left-justified serial interface format (for 16 bits)
SCLK
TAS5010
SLAS328 – SEPTEMBER 2001
LRCLK = f
SDIN
s
MSBLSBMSBLSB
Left ChannelRight Channel
Figure 9. MSB Left-Justified Serial Interface Format
Note the following characteristics of this protocol:
–Left channel is received when LRCLK is high.
–Right channel is received when LRCLK is low.
–SDIN is sampled at the rising edge of SCLK.
DSP compatible serial interface format (for 16 bits)
SCLK
LRCLK = f
SDIN
s
15141301514130
Left Channel
(MSB = 15)
Right Channel
(MSB = 15)
Figure 10. DSP Compatible Serial Interface Format
Note the following characteristics of this protocol:
–Serial data is sampled with the falling edge of SCLK.
PWM Outputs
Designed to be used with the TAS5100 family of H-Bridges, the PWM outputs provide differential 3.3 V
square-wave signals. During normal operation these outputs represent the input PCM audio in the pulse-width
modulation scheme. In the hard-mute state the P outputs (PWM_AP_L and PWM_AP_R) are held low and the
M outputs (PWM_AM_L and PWM_AM_R) are held high. In the quiet-mute state the differential PWM outputs
have a 50% duty cycle.
www.ti.com
11
TAS5010
SLAS328 – SEPTEMBER 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Analog supply voltage range, AV
Digital power supply voltage, DV
Digital input voltage, V
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: DVDD1, DVDD2, DVDD3_L, DVDD3_R.
recommended operating conditions, T
= AV
Supply voltageDigitalDVDDX
Supply currentDigital
Power dissipationDigital
Supply voltageAnalogAVDDX
Supply currentAnalog
Power dissipationAnalog
‡
DVDD1, DVDD2, DVDD3_L, DVDD3_R
§
If the clocks are turned off
¶
AVDD1, AVDD2
= 3.3 V ±10%, Fs = 44.1 kHz
DD2
= 25°C, DV
A
‡
Operating22mA
Power down
Operating59.4mW
Power down
¶
Operating8mA
Power down
Operating26.4mW
Power down
DD1
§
§
§
§
= DV
DD2
= DV
DD3_L
= DV
= 3.3 V ±10%, AV
DD3_R
MINTYPMAXUNIT
33.33.6V
1020µA
6.672µW
33.33.6V
10100µA
33360µW
DD1
electrical characteristics, TA = 25°C, DV
AV
DD1
= AV
= 3.3 V ±10%
DD2
DD1
= DV
DD2
= DV
DD3_L
= DV
DD3_R
= 3.3 V ±10%,
static digital specifications
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
V
High-level input voltage2DVDD1V
IH
V
Low-level input voltage00.8V
IL
V
High-level output voltageIO = –1 mA2.4V
OH
V
Low-level output voltageIO = 4 mA0.4V
OL
Input leakage current–1010µA
digital interpolation filter and PWM modulator, Fs = 44.1 kHz
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Pass band020kHz
Pass band ripple±0.012dB
Stop band24.1kHz
Stop band attenuation24.1 kHz to 152.3 kHz50dB
Group delay700µS
PWM modulation index (gain)0.93
12
www.ti.com
TAS5010/TAS5100 system performance measured at the speaker terminals
See application note, literature number SLAA117.
switching characteristics,
T
= 25°C, DV
A
serial audio ports slave mode
f
(SCLK)
t
su(SDIN)
t
h(SDIN)
F
(LRCLK)
t
su(LRCLK)
SCLK frequency12.288MHz
SDIN setup time before SCLK rising edge20ns
SDIN hold time from SCLK rising edge10ns
LRCLK frequency44.148192kHz
MCLK duty cycle50%
SCLK duty cycle50%
LRCLK duty cycle50%
LRCLK edge setup before SCLK rising edge20ns
serial audio ports master mode, load conditions: 50 pF
t
(MSD)
t
(MLRD)
MCLK to SCLK05ns
MLCK to LRCLK05ns
DD1
= DV
DD2
= DV
DD3_L
PARAMETERMINTYPMAXUNIT
PARAMETERMINTYPMAXUNIT
= DV
DD3_R
= AV
DD1
= AV
= 10% 3.3 V ±10%
DD2
TAS5010
SLAS328 – SEPTEMBER 2001
DSP serial interface mode
PARAMETERMINTYPMAXUNIT
f(SCLK)SCLK frequency12.288MHz
t
W(FSHIGH)
t
su(SDIN)
t
su(LRCLK)
t
h(SDIN)
t
h(LRCLK)
Pulse duration, sync1/(64×fs)ns
,
SDIN and LRCLK setup time before SCLK falling edge20ns
,
SDIN and LRCLK hold time from SCLK falling edge10ns
SCLK duty cycle50%
www.ti.com
13
TAS5010
SLAS328 – SEPTEMBER 2001
PARAMETER MEASUREMENT INFORMATION
SCLK
t
h(SDIN)
SDIN
t
su(SDIN)
Figure 11. Right-Justified, IIS, Left-Justified Serial Protocol Timing
SCLK
t
su(LRCLK)
LRCLK
NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns)
Figure 12. Right, Left, and IIS Serial Mode Timing Requirement
SCLK
LRCLK
(Output)
t
(MSD)
t
(MLRD)
MCLK
(Output)
14
SCLK
LRCLK
SDIN
Figure 13. Serial Audio Ports Master Mode Timing
t
su(LRCLK)
t
w(FSHIGH)
t
su(SDIN)
t
h(LRCLK)
Figure 14. DSP Serial Port Timing
www.ti.com
t
h(SDIN)
ОООООО
ОООООО
SCLK
LRCLK
PARAMETER MEASUREMENT INFORMATION
t
w(FSHIGH)
TAS5010
SLAS328 – SEPTEMBER 2001
64 SCLKs
SDIN
16-Bit Left Channel Data 16-Bit Left Channel Data32-Bit Ignore
Figure 15. DSP Serial Port Expanded Timing
SCLK
t
su(SDIN)
= 20 ns
t
h(SDIN)
= 10 ns
SDIN
NOTE: Serial data is sampled with the falling edge of SCLK (setup time = 20 ns and hold time = 10 ns)
Figure 16. DSP Absolute Timing Requirement
16-Bit Left Channel Data
www.ti.com
15
TAS5010
SLAS328 – SEPTEMBER 2001
APPLICATION INFORMATION
TAS5010
†
C
1
3.3 V DIG
†
C
2
R
Audio
Source
Clock
Generator
PLL_FLT_RET
PWM_AP_L
PWM_AM_L
†
1
PLL_FLT_OUT
DEM_SEL
DEM_EN
DBSPD
SDIN
LRCLK
SCLK
MCLK_IN
MOD0
MOD1
MOD2
M_S
XTL_IN
VALID_L
PWM_AP_R
PWM_AM_R
VALID_R
RESET
MUTE
PDN
TAS5100
H-Bridge
RESET
TAS5100
H-Bridge
RESET
System
Controller
†
See application note, literature number SLAA117 for values
FTEST
STEST
16
www.ti.com
SLAS328 – SEPTEMBER 2001
TAS5010
MECHANICAL DATA
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
37
48
1,05
0,95
0,50
36
0,27
0,17
25
24
13
1
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
12
M
0,08
0,05 MIN
Seating Plane
0,13 NOM
Gage Plane
0,25
0°–ā7°
0,75
0,45
1,20 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
www.ti.com
0,08
4073176/B 10/96
17
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty . Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. T o minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party , or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.