TEXAS INSTRUMENTS TAS5001 Technical data

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TAS5001

SLES009A – SEPTEMBER 2001 – REVISED DECEMBER 2001

TRUE DIGITAL AUDIO AMPLIFIER

TAS5001 DIGITAL AUDIO PWM PROCESSOR

FEATURES

TAS5001 + TAS5100 TDAA System – High

D

Quality Digital Audio Amplification

D 96-dB Dynamic Range (TAS5001 Device)
D 93-dB Dynamic Range (TAS5001 and TAS5100

System Measured at Speaker Terminals)

D THD+N < 0.08% (1 kHz, 0 to 30 W RMS

Into 6 Ω) (T AS5001 & TAS5100 System
Measured at Speaker Terminals)

D Power Efficiency Is 90% Into 8-Ω Load
D 16-, 20-, or 24-Bit Input Data
D 32-kHz, 44.1-kHz, 48-kHz, 88.2-kHz, 96-kHz

Sampling Rates

D Economical 48-Pin TQFP Package
D Lower-Jitter Internal PLL
D 3.3-V Power Supply
D Mute
D Clicks and Pops Reduction (Patent Pending)

APPLICATIONS

D

DVD Audio

D Home Theater
D Car Audio Amplifiers and Head Units

D Internet Music Appliance
D Mini/Micro Component Systems

DESCRIPTION

The true digital audio amplifier (TDAA) is a new
paradigm in digital audio. One TDAA system consists of
the TAS5001 PCM-PWM modulator device + T AS5100
PWM power output device. This system accepts a serial
PCM digital audio stream and converts it to a 3.3-V
PWM audio stream (TAS5001). The TAS5100 device
then provides a large-signal PWM output. This digital
PWM signal is then demodulated providing power
output for driving loudspeakers. This patented
technology provides low-cost, high-quality, high­efficiency digital audio applicable to many audio
systems developed for the digital age. The T AS5001 is
an innovative, cost-effective, high-performance 24-bit
stereo PCM-PWM modulator based on Equibit
technology. It has a wide variety of serial input options
including right-justified (16, 20, or 24 bits), IIS (16, 20,
or 24 bits), left-justified (16 bits), or DSP (16 bits) data
formats. It is fully compatible with AES standard
sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,
and 96 kHz. The T AS5001 also provides a de-emphasis
function for 44.1-kHz and 48-kHz sampling rates.

Digital Audio

• TAS3001

• DSP

TAS5001

• S/PDIF

• 1394

• Serial Audio Input Port

• Volume

• EQ

• Internal PLL

• Equibit Modulator

• DRC

• Bass

• Treble

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Equibit is a trademark of Toccata Technology ApS, Denmark.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Left

Right

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TAS5100

TAS5100

• H-Bridges

Power Devices

L-C

Filter

L-C

Filter

Copyright  2001, Texas Instruments Incorporated

1

TAS5001

SLES009A – SEPTEMBER 2001 – REVISED DECEMBER 2001

terminal assignments

AVDD1

48-Pin TQFP PACKAGE

(TOP VIEW)

XTL_IN

XTL_OUT

OSC_CAP

AVSS1

DEM_EN

DEM_SEL

FTEST

STEST

DBSPD

MUTE

DVSS3_L

references

MCLK_IN

AVDD2

PLL_FLT_OUT

PLL_FLT_RET

AVSS2

RESET

PDN

VALID_R

M_S

DVDD1

NC – No internal connection

NC

NC

1
2
3
4
5
6
7
8
9
10
11
12

13

47 46 45 44 4348 42 40 39 3841

14 15

DVSS1

16

DVSS1

DVDD1

17 18 19 20

SCLK

LRCLK

MCLK_OUT

SDIN

MOD2

22 23 24

21

MOD1

37

MOD0

VALID_L

DVDD3_L

36

PWM_AP_L

35

PWM_AM_L

34
33

NC

32

NC
DVDD2

31

DVSS2

30

PWM_AP_R

29

PWM_AM_R

28

NC

27

NC

26

DVDD3_R

25

DVSS3_R

D True Digital Audio Amplifier TAS5100 PWM Power Output Stage – Texas Instruments literature

number SLLS419A

D Design Considerations for TAS5000/TAS5100 True Digital Audio Power Amplifiers – Texas Instruments

literature number SLAA117

D Digital Audio Measurements – Texas Instruments literature number SLAA114
D PowerPAD Thermally Enhanced Package – Texas Instruments literature number SLMA002

PowerPAD is a trademark of Texas Instruments.

2

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functional block diagram

PLL_FLT_RET

PLL_FLT_OUT

MCLK_IN

VALID_R

VALID_L

SLES009A – SEPTEMBER 2001 – REVISED DECEMBER 2001

MCLK_OUT

XTL_IN

XTL_OUT

OSC_CAP

TAS5001

LRCLK

SCLK

SDIN

Serial
Audio

Port

Control Section

Audio Port

Configuration

MOD0

MOD1

MOD2

†

These packages are available taped and reeled. Add an R suffix
to device type (e.g., TAS5001PFBR).

PLL/Clock
Generator

Digital

Interpolation

Filter

PDN

MUTE

DEM_EN

DEM_SEL

T

A

0°C to 70°C TAS5001PFB

–40°C to 85°C TAS5001IPFB

FTEST

RESET

STEST

AVAILABLE OPTIONS

M_S

DBSPD

Equibit

Modulator

DVDD1

DVSS1

DVSS2

DVDD2

PACKAGE

OSC

DVSS3_L

DVDD3_L

DVDD3_R

†

Buffer

AVSS1

AVDD1

DVSS3_R

AVSS2

AVDD2

PWM_AP_L
PWM_AM_L

PWM_AP_R
PWM_AM_R

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3

TAS5001

SLES009A – SEPTEMBER 2001 – REVISED DECEMBER 2001

Terminal Functions

TERMINAL

NAME NO.

AVDD1 48 I Analog supply for oscillator
AVDD2 2 I Analog supply for PLL
AVSS1 44 I Analog ground for oscillator
AVSS2 5 I Analog ground for PLL
DBSPD 39 I Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high
DEM_EN 43 I De-emphasis enable, active high
DEM_SEL 42 I De-emphasis select (0 = 44.1 kHz, 1 = 48 kHz)
DVDD1 12, 14 I Digital voltage supply for logic
DVDD2 31 I Digital voltage supply for PWM reclocking
DVDD3_L 36 I Digital voltage supply for PWM output (left)
DVDD3_R 25 I Digital voltage supply for PWM output (right)
DVSS1 13, 15 I Digital ground for logic
DVSS2 30 I Digital ground for PWM reclocking
DVSS3_L 37 I Digital ground for PWM output (left)
DVSS3_R 24 I Digital ground for PWM output (right)
FTEST 41 I Tied to DVSS1 for normal operation
LRCLK 18 I/O Left/right clock (input when M_S = 0; output when M_S = 1)
MCLK_IN 1 I MCLK input
MCLK_OUT 16 O Buffered system clock output if M_S = 1; otherwise set to 0
MOD0 22 I Serial interface selection pin, bit 0
MOD1 21 I Serial interface selection pin, bit 1
MOD2 20 I Serial interface selection pin, bit 2 (MSB)
M_S 10 I Master/slave, master=1, slave=0
MUTE 38 I Muted signal = 0, normal mode = 1
NC 6, 11, 26, 27,

32, 33
OSC_CAP 45 I Oscillator cap return
PDN 8 I Power down, active low
PLL_FLT_OUT 3 O Output terminal for external PLL filter
PLL_FLT_RET 4 I Return for external PLL filter
PWM_AM_L 34 O PWM left output (differential –)
PWM_AM_R 28 O PWM right output (differential –)
PWM_AP_L 35 O PWM left output (differential +)
PWM_AP_R 29 O PWM right output (differential +)
RESET 7 I Reset (active low)
SCLK 17 I/O Shift clock (input when M_S = 0, output when M_S = 1)
SDIN 19 I Stereo serial audio data input
STEST 40 I Tied to DVSS1 for normal operation
VALID_L 23 O PWM left outputs valid (active high)
VALID_R 9 O PWM right outputs valid (active high)
XTL_IN 47 I Crystal or clock input (MCLK input)
XTL_OUT 46 O Crystal output (not for external usage). NC when XTL_IN is MCLK input

I/O

No connection

DESCRIPTION

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SLES009A – SEPTEMBER 2001 – REVISED DECEMBER 2001

functional description

serial audio port

The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin),
and a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 32-kHz, 44.1-kHz,
48-kHz, 88.2-kHz, 96-kHz stereo). See the serial interface formats section for more information.

system clocks—master mode and slave mode

The TAS5001 allows multiple system clocking schemes. Master mode indicates that the TAS5001 provides
system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 256 Fs MCLK_OUT,
64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode. Slave mode
indicates that a system master other than the TAS5001 provides system clocks (LRCLK, SCLK, and MCLK_IN)
to the TAS5001 (M_S = 0). The TAS5001 operates with LRCLK and SCLK synchronized to MCLK. TAS5001
does not require any specific phase relationship between LRCLK and MCLK, but there must be synchronization.
In the slave mode MCLK_OUT is driven low. Table 1 shows all the possible master and slave modes.

oscillator/sampling frequency

The sampling frequency is determined by the crystal (master mode) or master clock in (slave mode) which
should be either 8.192 MHz (Fs = 32 kHz), 1 1.2896 MHz (Fs = 44.1 kHz), or 12.288 MHz (Fs = 48 kHz). T wice
the normal sampling frequency can be selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz
or Fs = 96 kHz. In the double-speed slave mode (DBSPD = 1, M_S = 0), the external clock input is either

22.5796 MHz (Fs = 88.2 kHz) or 24.576 MHz (Fs = 96 kHz). Note that 32-kHz sampling is supported in the
normal speed modes. Table 1 explains the proper clock selection.

TAS5001

Table 1. Oscillator, External Clock, and PLL Functions

DESCRIPTION M_S DBSPD

Master, normal speed 1 0 8.192 — 2.048 32 8.192
Master, normal speed 1 0 11.2896 — 2.8224 44.1 11.2896
Master, normal speed 1 0 12.288 — 3.072 48 12.288
Master, double speed 1 1 — 22.5792
Master, double speed 1 1 — 24.576
Slave, normal speed 0 0 — 8.192
Slave, normal speed 0 0 — 11.2896
Slave, normal speed 0 0 — 12.288
Slave, double speed 0 1 — 22.5792
Slave, double speed 0 1 — 24.576

†

Either a crystal oscillator or an external clock of the specified frequency can be connected to XTL_IN.

‡

MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN is provided.

§

External MCLK connected to MCLK_IN input

¶

SCLK and LRCLK are outputs when M_S=1, inputs when M_S=0.

#

MCLK_OUT is driven low when M_S=0.

XTL_IN
(MHz)

†

MCLK_IN

‡

(MHz)

SCLK

(MHz)

§

5.6448 88.2 22.5792

§

§

§

2.8224 44.1 Digital GND

§

§

5.6448 88.2 Digital GND

§

LRCLK

¶

6.144 96 24.576

2.048 32 Digital GND

3.072 48 Digital GND

6.144 96 Digital GND

(kHz)

¶

MCLK_OUT

(MHz)

#

phase-locked loop (PLL)/clock generation

A low-jitter PLL is incorporated for internal use. Connections for the PLL external loop filter are provided as
PLL_FL T_RET and PLL_FL T_OUT . If the PLL loses lock, the PWM output status pins (V ALID_L and V ALID_R)
go low. Note that VALID_L and VALID_R can go low for other conditions as well. See the error status reporting
section for more information.

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5

TAS5001

SLES009A – SEPTEMBER 2001 – REVISED DECEMBER 2001

functional description (continued)

digital interpolation filter

The 24-bit high-performance linear phase FIR interpolation filter up-samples the input digital data at a rate of
four times (double speed mode = 88.2 kHz or 96 kHz), or eight times (normal mode = 32 kHz, 44.1 kHz, or 48
kHz) the incoming sample rate. This filter provides very low pass-band ripple and optimized time domain
transient response for accurate music reproduction.

digital PWM modulator

The interpolation filter output is sent to the modulator. This modulator consists of a high performance fourth order
digital noise shaper and a PCM-to-PWM converter. Following the noise shaper , the PCM signal is fed into a very
low distortion PCM-to-PWM conversion block, buffered, and output from the chip. The modulation scheme is
based on a 2-state control of the H-bridge output.

control, status, and operational modes

The T AS5001 control section consists of several control-input pins. Three serial mode pins (MOD0, MOD1, and
MOD2) are provided to select various serial data formats. During normal operating conditions if any of the
MOD0, MOD1, or MOD2 pins changes state, a reset sequence is initiated. Also provided are separate
power-down (PDN

), reset (RESET), and mute (MUTE) pins.

power up

At power up the V ALID_L and VALID_R pins are asserted low and the PWM outputs go to the hard mute state
in which the P outputs are held low and the M outputs are held high. Following initialization, the T AS5001 comes
up in the operational state (differential PWM audio). There are two cases of power-up timing. The first case is
shown in Figure 1 with RESET
RESET

.

RESET

PDN

VALID_L

VALID_R

preceding PDN. The second case is shown in Figure 2 with PDN preceding

Initialization Time = 100 ms max

Figure 1. Power-Up Timing (RESET Preceding PDN)

Greater Than 16 MCLK Periods

RESET

PDN

Initialization Time = 5 ms max

VALID_L

VALID_R

Figure 2. Power-Up Timing (PDN Preceding RESET)

6

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