Texas Instruments TAS3204PAG, TAS3204 Datasheet
www.ti.com
1 Introduction
SDOUT1
SDOUT2
Differential
Analog
Out
SDIN1
SDIN2
Differential
Analog
In
MCLK_IN
LRCLK_IN
SCLK_IN
MCLK_OUTx
LRCLK_OUT
SCLK_OUT
I2C Port #1
I2C Port #2
Output
SAP
Stereo
DAC
Stereo
DAC
Volume
Update
Input
SAP
Stereo
ADC
Stereo
ADC
PLL
and
Clock
Control
TAS3204
I2C
Interface
Digital Audio
Processor Core
48-Bit Data Path
28-Bit Coefficients
76-Bit MAC
3K Code RAM
1K Upper Data RAM
768 Lower Data RAM
1.2K Coeff. RAM
Boot ROM
8051 MCU
8-Bit Microprocessor
256 IRAM
2K ERAM
16K Code RAM
10K Code ROM
2
2
2
3
2
2
2
2
4
2
2
4
2
2
1.1 Features
• High-Quality Audio Performance:
102-dB ADC/105-dB DAC (Typical) DNR
• Eight-Channel Programmable Audio DSP
(Four-Channel Digital and Four-Channel
Analog)
• Three Differential Stereo Analog Inputs
Multiplexed to Two Stereo Input ADCs
• Two Differential Stereo Output DACs
• Two Serial Audio Inputs (Four Channels) and
Two Serial Audio Outputs (Four Channels)
• 135-MHz Maximum Speed, >2800 Processing
Cycles Per Sample at 48 kHz
• 512 × Fs XTAL Input in Master Mode,
512 × Fs MCLK_IN in Slave Mode
• 48-kHz Sample Rate in Master Mode
• 44.1 or 48-kHz Sample Rate in Slave Mode
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
• 48-Bit Data Path and 28-Bit Coefficients
• 768 Words of 48-Bit Data Memory
• 1022 Words of 28-Bit Coefficient Memory
• 3K Words of 55-Bit Program RAM
• Hardware Single-Cycle Multiplier (28 × 48)
• 2812 Instructions Per Fs
• 5.88K Words of 24-Bit Delay Memory
(122.5 ms at 48 kHz)
• Data Formats: Left Justified, Right Justified,
and I2S
• Two I2C Ports for Slave or Master Download
• Single 3.3-V Power Supply
• Graphical Development Environment Provided
for Audio Processing; e.g., EQ, Algorithm
Development, Etc.
1.2 Applications
• MP3 Docking Systems
• Digital Televisions
• Mini-Component Audio
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
Copyright © 2007, Texas Instruments Incorporated
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
Contents
1 Introduction ............................................... 1 8.1 Absolute Maximum Ratings ......................... 37
1.1 Features .............................................. 1 8.2 Package Dissipation Ratings ........................ 37
1.2 Applications ........................................... 1 8.3 Recommended Operating Conditions ............... 37
2 Functional Description ................................. 3 8.4 Electrical Characteristics ............................ 38
2.1 Analog Input/MUX/Stereo ADCs ..................... 4 8.5 Audio Specifications ................................. 38
2.2 Stereo DACs .......................................... 4 8.6 Timing Characteristics ............................... 41
2.3 Analog Reference System ............................ 4 8.6.1 Master Clock ....................................... 41
2.4 Power Supply ......................................... 4 8.6.2 Serial Audio Port, Slave Mode ..................... 42
2.5 Clocks, Digital PLL, and Serial Data Interface ....... 4
2
2.6 I
C Control Interface .................................. 6
2.7 8051 Microcontroller ................................. 6
2.8 Audio Digital Signal Processor Core ................. 6
3 Physical Characteristics ............................... 7
3.1 Terminal Assignments ................................ 7
3.2 Ordering Information .................................. 7
3.3 Terminal Descriptions ................................ 8
3.4 Reset ( RESET) - Power-Up Sequence ............. 10
3.5 Voltage Regulator Enable ( VREG_EN) ............. 10
3.6 Power-On Reset ( RESET) .......................... 10
3.7 Power Down ( PDN) ................................. 10
2
3.8 I
C Bus Control (CS0) ............................... 11
3.9 Programmable I/O (GPIO) .......................... 11
3.10 Input and Output Serial Audio Ports ................ 12
4 Algorithm and Software Development Tools for
TAS3204 .................................................. 18
5 Clock Controls .......................................... 19
6 Microprocessor Controller .......................... 21
6.1 8051 Microprocessor Addressing Mode ............ 22
6.2 General I
2
6.3 I
2
6.4 I
2
C Operations ............................. 23
C Slave Mode Operation .......................... 24
C Master-Mode Device Initialization .............. 27
7 Digital Audio Processor (DAP) Arithmetic Unit . 33
7.1 DAP Instructions Set ................................ 34
7.2 DAP Data Word Structure ........................... 35
8 Electrical Specifications .............................. 37
8.6.3 Serial Audio Port Master Mode Signals
(TAS3204) ........................................... 43
8.6.4 Pin-Related Characteristics of the SDA and SCL
I/O Stages for F/S-Mode I
8.6.6 Reset Timing ........................................ 46
2
9 I
C Register Map ........................................ 47
9.1 Clock Control Register (0x00) ...................... 48
9.2 Microcontroller Clock Control Register .............. 48
9.3 Status Register (0x02) .............................. 49
9.4 I2C Memory Load Control and Data Registers (0x04
and 0x05) ............................................ 50
9.5 Memory Access Registers (0x06 and 0x07) ........ 51
9.6 Device Version (0x08) ............................... 52
9.7 Analog Power Down Control (0x10 and 0x11),
ESFR (0xE1 and 0xE2) ............................. 52
9.8 Analog Input Control (0x12), ESFR (0xE3) ......... 53
9.9 Dynamic Element Matching (0x13), ESFR (0XE4) .. 53
9.10 Current Control Select (0x14, 0x15, 0x17, 0x18),
ESFR (0xE5, 0xE6, 0xE7, 0xE9) .................... 54
9.11 DAC Control (0x1A, 0x1B, 0x1D), ESFR (0xEB,
0xEC, 0xEE) ......................................... 58
9.12 ADC and DAC Reset (0x1E), ESFR (0xFB) ........ 60
9.13 ADC Input Gain Control (0x1F), ESFR (0xFA) ...... 60
9.14 MCLK_OUT Divider (0x21 and 0x22) ............... 61
9.15 Digital Cross Bar (0x30 to 0x3F) .................... 61
9.16 Extended Special Function Registers (ESFR) Map . 63
2
C-Bus Devices .......... 44
10 Application Information ............................... 68
10.1 Schematics .......................................... 68
10.2 Recommended Oscillator Circuit .................... 69
2 Contents Submit Documentation Feedback
www.ti.com
2 Functional Description
DSP Core
8051MicroprocessorCore
Oscillator
DPLL
Clock
Divider
512FsXTAL
MCLK_IN
512Fs
Slave
Master
Clock
Generation
Serial AudioPort
LRCLK_OUT
SCLK_OUT
LRCLK_IN
SCLK_IN
SDOUT1/2
TwoStereo
ADC
Three
Differential
Stereo
AnalogInputs
TwoStereo
DAC
TwoDifferential
Stereo Analog
Outputs
SCL1/SDA1
SCL2/SDA2
GPIO1/2
Master/Slave
256Fs
Power
Supply
AVDD
DVDD
128Fs
Volume
Update
Input
Cross
Bar
Mixer
OutputCross
BarMixer
SDIN1/2
Clocks
Legend
DigitalData
AnalogData
InternalConnection
External Connection
Control
Registers
External
RAM2K
Code
RAM16K
8-Bit
MCU
Internal
RAM256
DataRAM
1KUpperMem
768LowerMem
Coefficient
RAM 1.2K
Code
RAM 3K
DSP
Control
Memory
Interface
Data
Path
I2C
Control
Interface
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
The TAS3204 is an audio system-on-a-chip (SOC) designed for mini/micro systems, multimedia-speaker,
and MP3 player docking systems. It includes analog interface functions: three multiplex (MUX) stereo
inputs with two stereo analog-to-digital converters (ADCs), two stereo digital-to-analog converters (DACs)
with analog outputs consisting of differential stereo line drivers. Four channels of serial digital audio
processing are also provided. The TAS3204 has a programmable audio digital signal processor (DSP) that
preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single cycle
28 × 48-bit multiplier. The programmability feature allows users to customize features in the DSP RAM.
The TAS3204 is composed of eight functional blocks:
1. Analog input/mux/stereo ADC
2. Two stereo DACs
3. Analog reference system
4. Power supply
5. Clocks, digital pll, and serial data interface
6. I2C control interface
7. 8051 microcontroller
8. Audio DSP – digital audio processing
Figure 2-1. Expanded Functional Block Diagram
Submit Documentation Feedback Functional Description 3
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
2.1 Analog Input/MUX/Stereo ADCs
These modules allow three differential analog stereo inputs to be sent to either of two ADCs to be
converted to digital data. The input multiplexers include a preamplifier. This amplifier is driving the ADCs,
and it is digitally controlled with changes synchronized with the sample clock of the ADC. Minimal
crosstalk between selected channels and unselected channels is maintained. When inputs are not needed
they are configured for minimal noise. Also included in this module are two fully differential over sampled
stereo ADCs. The ADCs are sigma-delta modulators with 256 times over-sampling ratio. Because of the
over-sampling nature of the audio ADCs and integrated digital decimation filters, requirements for analog
anti-aliasing filtering are relaxed. Filter performance for the ADCs are specified under physical
characteristics.
2.2 Stereo DACs
This module includes two stereo audio DACs, each of which consists of a digital interpolation filter, digital
sigma-delta modulator and an analog reconstruction filter. Each DAC can operate a maximum of 48 kHz.
Each DAC upsamples the incoming data by 128 and performs interpolation filtering and processing on this
data before conversion to a stereo analog output signal. The sigma-delta modulator always operates at a
rate of 128Fs, which ensures that quantization noise generated within the modulator stays low within the
frequency band below Fs/2.4 at all sample rates. The digital interpolation filters for interpolation from Fs to
8 × Fs are included in the audio DSP upper memory (reserved for analog processing), while interpolation
from 8 × Fs to 128Fs is done in a dedicated hardware sample and hold filter. The TAS3204 includes two
stereo line driver outputs. All line drivers are capable of driving up to a 10-k Ω load. Each stereo output can
be in power-down mode when not used. Popless operation is achieved by conforming to start and stop
sequences in the device controller code.
2.3 Analog Reference System
This module provides all internal references needed by the analog modules. It also provides bias currents
for all analog blocks. External decoupling capacitors are needed along with an external 1%-tolerance
resistor to set the internal bias currents. It includes a band-gap reference and several voltage buffers and
a tracking current reference. The TAS3204 also uses an internally generated mid supply that is used to
rereference all analog inputs and is present on all analog outputs. VMID is the analog mid supply and can
be used when buffered externally to rereference the analog inputs and outputs. The voltage reference
REXT requires a 22-k Ω 1% resistor to ground. The reference system can be powered down separately.
2.4 Power Supply
The power supply contains supply regulators that provide analog and digital regulated power for various
sections of the TAS3204. Only one external 3.3-V supply is required. All other voltages are generated on
chip from the external 3.3-V supply.
2.5 Clocks, Digital PLL, and Serial Data Interface
These modules provide the timing and serial data interface for the TAS3204. The clocking system for the
device is illustrated in Figure 2-2 . The TAS3204 can be either clock master or clock slave depending on
the configuration. However, master mode is the primary mode of operation.
Functional Description4 Submit Documentation Feedback
www.ti.com
DPLL
×5.5
÷4
135-MHz DCLK
Microprocessor Clock
MCLK_OUT
MCLK_OUT2
MCLK_OUT3
Programmable
Divider
÷2 ÷2 ÷2 ÷64
÷2
Programmable
Divider
Master/
Slave
LRCLK_OUT
SCLK_OUT
SDOUT
To DAP
Parallel
Data
SDIN
From DAP
Parallel
Data
LRCLK
Re-Creation
Serial
Audio Port
Receiver
Serial
Audio Port
Transmitter
256Fs 128Fs 64Fs
512Fs
Crystal
MCLKI
24.576 MHz
Oscillator
24.576 MHz
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
Figure 2-2. Clock Generation
DISCLAIMER: Analog performance is not ensured in slave mode, as the analog performance depends
upon the quality of the MCLK_IN. The TAS3204 is not robust with respect to MCLK_IN errors (glitches,
etc.); if the MCLK_IN frequency changes under operation, the device must be reset.
Master mode operation:
• External 512Fs crystal oscillator is used to generate all internal clocks plus all clocks for external
asynchronous sampling rate converter (ASRC) output (if external ASRC is present).
• LRCLK_OUT is fixed at 48 kHz (Fs).
• SCLK_OUT is fixed at 64Fs.
• MCLK_OUT is fixed at 256Fs. In master mode, the external ASRC converts incoming serial audio data
to 48-kHz sample rate synchronous to the internally generated serial audio data clocks.
• In master mode, all clocks generated for the TAS3204 are derived from the 24.576-MHz crystal. The
internal oscillator drives the crystal and generates the main clock to digital PLL (DPLL), master clock
outputs, 256Fs clock to the ADC, and 128Fs clock to the DAC. The DPLL generates internal clocks for
the DAP and the 8051 microprocessor.
Slave mode operation:
• MCLK_IN (512Fs), SCLK_IN (64Fs), and LRCLK_IN (Fs) are supplied externally. Clock generation is
similar to the master mode with the exception of the ADC and the DAC blocks. MCLK_IN signal is
divided down and sent directly to the ADC and the DAC blocks. Therefore, audio performance
depends on the MCLK_IN signal.
• DSP, MCU, and I2C clocks are still derived from external crystal oscillator.
• MCLK_OUT, SCLK_OUT, and LRCLK_OUT are passed through from clock inputs (MCLK_IN,
SCLK_IN, and LRCLK_IN).
• Internal analog clocks for ADC and DACs are derived from external MCLK_IN input, so analog
performance depends on MCLK_IN quality (i.e., jitter, phase noise, etc.). Degradation in analog
performance is to be expected.
Submit Documentation Feedback Functional Description 5
• Sample rate change/clock change
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
In slave mode, all incoming serial audio data must be synchronous to an incoming LRCLK_IN of 44.1 kHz
or 48 kHz.
2.6 I2C Control Interface
The TAS3204 has an I2C slave-only interface (SDA1 and SCL1) for receiving commands and providing
status to the system controller, and a separate master I2C interface (SDA2 and SCL2) to download
programs and data from external memory such as an EEPROM. See Section 6 for more information. I2C
interface is not 5-V tolerant.
2.7 8051 Microcontroller
The 8051 microcontroller receives and distributes I2C write data. It retrieves and outputs data as
requested from the I2C bus controller. It performs most processing tasks requiring multi-frame processing
cycles. The microprocessor has its own data RAM for storing intermediate values and queuing I2C
commands, a fixed boot program ROM, and a programmable RAM. The microprocessor's boot program
cannot be altered. The microcontroller has specialized hardware for a master and slave interface
operation, volume updates, and a programmable interval-timer interrupt.
– Sample rate change on the fly should be handled by customer system controller. The TAS3204
device does not include any internal clock error or click/pop detection/management.
– Customer-specific DAP filter coefficients must be uploaded by customer system controller on
changing sample rate.
2.8 Audio Digital Signal Processor Core
The audio digital signal processor core arithmetic unit is a fixed-point computational engine consisting of
an arithmetic unit and data and coefficient memory blocks. The audio processing structure, which can
include mixers, multiplexers, volume, bass and treble, equalizers, dynamic range compression, or
third-party algorithms, is running in the DAP. The 8051 microcontroller has access to DAP resources such
as coefficient RAM and is able to support the DAP with certain tasks; for example, a volume ramp. The
primary blocks of the audio DSP core are:
• 48-bit data path with 76-bit accumulator
• DSP controller
• Memory interface
• Coefficient RAM (1K × 28)
• Data RAM – 24-bit upper memory (1K × 24), 48-bit lower memory (768 × 48)
• Program RAM (3K × 55)
The DAP is discussed in detail in the following sections.
6 Functional Description Submit Documentation Feedback
www.ti.com
PAG PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
I2C1_SCL
I2C1_SDA
GPIO2
GPIO1
MUTE
CS0
PDN
DVSS1
DVDD1
VR_PLL
AVSSI
AIN1LP
AIN1LM
AIN1RP
AIN1RM
AIN2LP
AIN2LM
AIN2RP
AIN2RM
AIN3LP
AIN3LM
AIN3RP
AIN3RM
A
VDD1
VMID
VREF
REXT
AVDD2
AOUT2LM
A
OUT2LP
AOUT2RM
AOUT2RP
MCLK_OUT1
MCLK_OUT2
MCLK_OUT3
DVDD2
DVSS2
MCLK_IN
XTAL_OUT
XTAL_IN
AVDD3
VR_ANA
AVSS_ESD
AVSSO
AOUT1RP
AOUT1RM
AOUT1LP
AOUT1LM
I2C2_SCL
I2C2_SDA
RESET
SDIN1/GPIO3
SDIN2/GPIO4
SCLK_IN
LRCLK_IN
DVDD3
DVSS3
VR_DIG
SDO1
SDO2
SCLK_OUT
LRCLK_OUT
RESER
VED
VREG_EN
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
3 Physical Characteristics
3.1 Terminal Assignments
3.2 Ordering Information
T
A
0 ° C to 70 ° C TAS3204PAG
PLASTIC 64-PIN PQFP (PN)
Submit Documentation Feedback Physical Characteristics 7
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
3.3 Terminal Descriptions
TERMINAL
NAME NO.
AIN1LM 13 Analog Input Pull to VMID
AIN1LP 12 Analog Input Analog input, channel 1, left, + input
AIN1RM 15 Analog Input Pull to VMID
AIN1RP 14 Analog Input Analog input, channel 1, right, + input
AIN2LM 17 Analog Input Pull to VMID
AIN2LP 16 Analog Input Analog input, channel 2, left, + input
AIN2RM 19 Analog Input Pull to VMID
AIN2RP 18 Analog Input Analog input, channel 2, right, + input
AIN3LM 21 Analog Input Pull to VMID
AIN3LP 20 Analog Input Analog input, channel 3, left, + input
AIN3RM 23 Analog Input Pull to VMID
AIN3RP 22 Analog Input Analog input, channel 3, right,+ input
AOUT1LM 33 Analog Output Analog output, channel 1, left, – output
AOUT1LP 34 Analog Output Analog output, channel 1, left, + output
AOUT1RM 35 Analog Output Analog output, channel 1, right, – output
AOUT1RP 36 Analog Output Analog output, channel 1, right, + output
AOUT2LM 29 Analog Output Analog output, channel 2, left, – output
AOUT2LP 30 Analog Output Analog output, channel 2, left, + output
AOUT2RM 31 Analog Output Analog output, channel 2, right, – output
AOUT2RP 32 Analog Output Analog output, channel 2, right,+ output
AVDD1 24 Power
AVSS1 11 Power Analog supply ground
AVDD2 28 Power
AVSS2 37 Power Analog supply ground
AVDD3 40 Power
AVSS3 38 Power Analog supply ground
CS0 6 Digital Input I2C secondary address
DVDD1 9 Power
DVSS1 8 Power Digital supply ground
DVDD2 45 Power
DVSS2 44 Power Digital supply ground
DVDD3 57 Power
DVSS3 56 Power Digital supply ground
GPIO1 4 Digital IO
GPIO2 3 Digital IO General-purpose I/O pin
I2C1_SCL 1 Digital Input
INPUT/ PULLUP/
OUTPUT
(1)
PULLDOWN
(2)
(3)
Analog input, channel 1, left, – input
(3)
Analog input, channel 1, right, – input
(3)
Analog input, channel 2, left, – input
(3)
Analog input, channel 2, right, – input
(3)
Analog input, channel 3, left, – input
(3)
Analog input, channel 3, right, – input
3.3-V analog power supply. This pin must be decoupled according to
good design practices.
3.3-V analog power supply. This pin must be decoupled according to
good design practices.
3.3-V analog power supply. This pin must be decoupled according to
good design practices.
3.3-V digital power supply. This pin must be decoupled according to
good design practices.
3.3-V digital power supply. This pin must be decoupled according to
good design practices.
3.3-V digital power supply. This pin must be decoupled according to
good design practices.
General-purpose I/O pin. When booting from internal ROM, the
TAS3204 streams audio when GPIO1 is low; otherwise it mutes.
Slave I2C serial control data interface input/output. Normally connected
to system micro.
DESCRIPTION
(1) I = input; O = output
(2) All pullups are 20- µ A weak pullups, and all pulldowns are 20- µ A weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 20 µ A while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 µ A while maintaining a logic-1 drive level.
(3) Pull to VMID when analog input is in single-ended mode.
Physical Characteristics8 Submit Documentation Feedback
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
TERMINAL
NAME NO.
I2C1_SDA 2 Digital I/O Slave I2C serial clock input. Normally connected to system micro.
I2C2_SCL 64 Digital Input
I2C2_SDA 63 Digital I/O Master I2C serial clock input. Normally connected to EEPROM.
LRCLK_IN 58 Digital Input Pulldown Serial data input left/right clock for I2S interface
LRCLK_OUT 51 Digital Output Serial data output left/right clock for I2S interface
MCLK_IN 43 Digital Input Pulldown
MCLK_OUT1 48 Digital Output 12.288 MHz clock output. This output is valid even when reset is LOW.
MCLK_OUT2 47 Digital Output in the range 0 to 255. Default value is 1.024 MHz. This output is valid
MCLK_OUT3 46 Digital Output in the range 0 to 255. Default value is 512 kHz. This output is valid
MUTE 5 Digital Input Pulldown
PDN 7 Digital Input
RESERVED 50 N/A Pulldown Connect to ground.
RESET 62 Digital Input Pullup
REXT 27 Analog Output
SCLK_IN 59 Digital Input Serial data input bit clock for I2S interface
SCLK_OUT 52 Digital Output Serial data output bit clock for I2S interface
SDIN1/GPIO3 61 Digital I/O Pullup Serial data input #1 for I2S interface or programmable for GPIO #3
SDIN2/GPIO4 60 Digital I/O Pullup Serial data input #2 for I2S interface or programmable for GPIO #4
SDOUT1 54 Digital Output Serial data output #1 for I2S interface
SDOUT2 53 Digital Output Serial data output #2 for I2S interface
VMID 25 Analog Output
VR_ANA 39 Power
VR_DIG 55 Power
VR_PLL 10 Power
VREF 26 Analog Output between this terminal and AVSS_PLL. This terminal must not be used
VREG_EN 49 Digital Input
XTAL_IN 41 Digital Input Crystal input. A 24.576-MHz (512Fs) crystal should be used.
XTAL_OUT 42 Digital Output Crystal output.
(4) If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provide an extended high frequency supply decoupling.
INPUT/ PULLUP/
OUTPUT
(1)
PULLDOWN
(2)
Master I2C serial control data interface input/output. Normally
connected to EEPROM.
MCLK input is used in slave mode. MCLK_IN must be locked to
LRCLK_IN, and the frequency is 512Fs (24.576 MHz for 48-kHz Fs).
The frequency for this clock is 6.144 MHz/(n+1) where n is programable
even when reset is LOW.
The frequency for this clock is 512 kHz/(n+1) where n is programmable
even when reset is LOW.
This pin needs to be programmed as mute pin in the application code.
In has no function in default after reset.
Power down, active LOW. After successful boot, its function is defined
by the boot code.
System reset input, active low. A system reset is generated by applying
a logic LOW to this terminal.
Requires a 22-k Ω (1%) external resistor to ground to set analog
currents. Trace capacitance must be kept low.
Analog mid supply reference. This pin must be decoupled with a 0.1- µ F
low-ESR capacitor and an external 10- µ F filter cap.
Voltage reference for analog supply. A pin-out of the internally
regulated 1.8 V power. A 0.1- µ F low ESR capacitor and a 4.7- µ F filter
capacitor must be connected between this terminal and AVSS_PLL.
This terminal must not be used to power external devices.
Voltage reference for digital supply. A pin-out of the internally regulated
1.8 V power. A 0.1- µ F low ESR capacitor and a 4.7- µ F filter capacitor
must be connected between this terminal and DVSS. This terminal
must not be used to power external devices.
Voltage reference for DPLL supply. A pin-out of internally regulated
1.8-V power supply. A 0.1- µ F low-ESR capacitor and a 4.7- µ F filter
capacitor must be connected between this terminal and DVSS. This
terminal must not be used to power external devices.
Band gap output. A 0.1- µ F low ESR capacitor should be connected
to power external devices.
Voltage regulator enable. When enabled LOW, this input causes the
power-supply regulators to be enabled.
DESCRIPTION
(4)
(4)
(4)
(4)
(4)
Submit Documentation Feedback Physical Characteristics 9
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
3.4 Reset ( RESET) - Power-Up Sequence
The RESET pin is an asynchronous control signal that restores all TAS3204 components to the default
configuration. When a reset occurs, the audio DSP core is put into an idle state and the 8051 starts
initialization. A valid XTAL_IN must be present when clearing the RESET pin to initiate a device reset. A
reset can be initiated by applying a logic 0 on RESET.
As long as RESET is held LOW, the device is in the reset state. During reset, all I2C and serial data bus
operations are ignored. The I2C interface SCL and SDA lines go into a high-impedance state and remain
in that state until device initialization has completed.
The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and
setting the default register values. Once these are complete, the TAS3204 enables its master I2C interface
and disables its slave I2C interface.
Using the master interface, the TAS3204 automatically tests to see if an external I2C EEPROM is at
address "1010x". The value x can be chip selects, other information, or don't care, depending on the
EEPROM selected.
If a memory is present and it contains the correct header information and one or more blocks of
program/memory data, the TAS3204 begins to load the program, coefficient and/or data memories from
the external EEPROM. If an external EEPROM is present, the download is considered complete when an
end of program header is read by the TAS3204. At this point, the TAS3204 disables the master I2C
interface, enable the slave I2C interface, and start normal operation. After a successful download, the
micro program counter is reset, and the downloaded micro and DAP application firmware controls
execution.
If no external EEPROM is present or if an error occurs during the EEPROM read, TAS3204 disables the
master I2C interface and enables the slave I2C interface initialization to load the slave default
configuration. In this default configuration, the TAS3204 streams audio from input to output if the GPIO1
pin is asserted LOW; if the GPIO1 pin is asserted HIGH, the ADC and the DAC are muted.
Note: The master and slave interfaces do not operate simultaneously.
3.5 Voltage Regulator Enable ( VREG_EN)
Setting the VREG_EN high shuts down all voltage regulators in the device. Internal register settings are
lost in this power down mode. A full power-up/reset/program-load sequence must be completed before the
device is operational.
3.6 Power-On Reset ( RESET)
On power up, it is recommended that the TAS3204 RESET be held LOW until DVDD has reached 3.3 V.
This can be done by programming the system controller or by using an external RC delay circuit. The
1-k Ω and 1- µ F values provide a delay of approximately 200 µ s. The values of R and C can be adjusted to
provide other delay values as necessary.
3.7 Power Down ( PDN)
The TAS3204 supports a number of power-down modes.
PDN can be used to put the device into power saving standby mode. PDN is user-firmware definable. Its
default configuration is to stop all clocks, power down all analog circuitry, and ramp down volume for all
digital inputs. This mode is used to minimize power consumption while preserving register settings. If there
is no EEPROM or if the EEPROM has an invalid image–i.e., an unsuccessful boot from the EEPROM–and
PDN is pulled low, the TAS3204 is in powerdown mode. After a successful boot, PDN is defined by the
boot code.
Physical Characteristics10 Submit Documentation Feedback
www.ti.com
Individual power down DAC and ADC – Each stereo DAC and ADC can be powered down individually. To
avoid audible artifacts at the outputs, the sequences defined in the TI document TAS3108/TAS3108IA
Firmware Programmer's Guide (SLEU067 ) must be followed. The control signals for these operations are
defined as ESFR. The feature is made available to the board controller via the I2C interface.
Power down of analog reference – The analog reference can be powered down if all DAC and ADC are
powered down. This operation is handled by the device controller through the ESFRs, and is made
available to the board controller via the I2C interface.
3.8 I2C Bus Control (CS0)
The TAS3204 has a control to specify the slave and master I2C address. This control permits up to two
TAS3204 devices to be placed in a system without external logic. GPIO pins are level sensitive. They are
not edge triggered.
See Section 6.3 for a complete description of this pin.
3.9 Programmable I/O (GPIO)
The TAS3204 has four GPIO pins and two general purpose input pins that are 8051 firmware
programmable.
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
GPIO1 and GPIO2 pins are single function I/O pins. Upon power up, GPIO1 is an input. If there is an
unsuccessful boot and GPIO1 is pulled high externally, the DAC output is disabled. If there is an
unsuccessful boot and the GPIO1 is pulled low externally, the DAC output is enabled. If there is a
successful boot, GPIO1 is pulled low by the internal microprocessor, and its function is defined by the boot
code in the EEPROM.
GPIO3 and GPIO4 pins are dual function I/O pins. These pins can be used as SDIN1 and SDIN2
respectively.
Mute and power down functions have to be programmed in the EEPROM boot code. These are
general-purpose input pins and can be programmed for functions other than mute and power down.
For more information, see the Texas Instruments document TAS3108/TAS3108IA Firmware Programmer's
Guide (SLEU067 ).
3.9.1 No EEPROM is Present or a Memory Error Occurs
Following reset or power-up initialization with the EEPROM not present or if a memory error occurs, the
TAS3204 is in one of two modes, depending on the setting of GPIO1.
• GPIO1 is logic HIGH
With GPIO1 held HIGH during initialization, the TAS3204 comes up in the default configuration with the
serial data outputs not active. Once the TAS3204 has completed the default initialization procedure,
after the status register is updated and the I2C slave interface is enabled, then GPIO1 is an output and
is driven LOW. Following the HIGH-to-LOW transition of the GPIO pin, the system controller can
access the TAS3204 through the I2C interface and read the status register to determine the load
status.
If a memory-read error occurs, the TAS3204 reports the error in the status register (I2C subaddress
0x02).
• GPIO1 is logic LOW
With GPIO1 held LOW during initialization, the TAS3204 comes up in an I/O test configuration. In this
case, once the TAS3204 completes its default test initialization procedure, the status register is
updated, the I2C slave interface is enabled, and the TAS3204 streams audio unaltered from input to
output as SDIN1 to SDOUT1, SDIN2 to SDOUT2, etc.
Submit Documentation Feedback Physical Characteristics 11
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
In this configuration, GPIO1 is an output signal that is driven LOW. If the external logic is no longer
driving GPIO1 low after the load has completed (~100 ms following a reset if no EEPROM is present),
the state of GPIO1 can be observed.
Then the system controller can access the TAS3204 through the I2C interface and read the status
register to determine the load status.
If the GPIO1 state is not observed, the only indication that the device has completed its initialization
procedure is the fact that the TAS3204 streams audio and the I2C slave interface has been enabled.
3.9.2 GPIO Pin Function After Device Is Programmed
Once the TAS3204 has been programmed, either through a successful boot load or via slave I2C
download, the operation of GPIO can be programmed to be an input and/or output.
3.10 Input and Output Serial Audio Ports
Serial data is input on SDIN1/SDIN2 on the TAS3204, allowing up to four channels of digital audio input.
The TAS3204 supports serial data in 16-, 20-, or 24-bit data in left, right, and I2S serial data formats. The
parameters for the clock and serial data interface input formats are I2C configurable.
Serial data is output on SDOUT1 and SDOUT2, allowing up to four channels of digital audio output.
SDOUT port supports the same formats as the SDIN port. Output data rate is the same data rate as the
input. The SDOUT output uses the SCLK_OUT and LRCLK_OUT signals to provide synchronization.
The TAS3204 supported data formats are listed in Table 3-1 .
Table 3-1. Supported Data Formats
Input SAP (SDIN1, SDIN2) Output SAP (SDOUT1, SDOUT2)
2-channel I2S 2-channel I2S
2-channel left-justified 2-channel left-justified
2-channel right-justified 2-channel right-justified
Table 3-2. Serial Data Input and Output Formats
Mode Control Control Serial Format Word Lengths Rates SCLK
2-channel 0001 0001 Right-justified 16, 20, 24 32–48 3.072
Input Output Data MAX
IM[3:0] OM[3:0] (kHz) (MHz)
0000 0000 Left-justified 16, 20, 24
0010 0010 I2S 16, 20, 24
Physical Characteristics12 Submit Documentation Feedback
www.ti.com
0x00
DWFMT (Data Word Format)
AckIOMAck
OW[2:0]
15
IW[2:0]
0
XX
14 13 11 10 8
7
DWFMT
815
AckxxxxxxxxAckSubaddrAckSlave AddrS
2431
OM[3:0]IM[3:0]
7 4 3 0
xxxxxxxxAck
1623
Output Port
Format
Input Port
Format
Input Port
Word Size
Output Port
Word Size
R0003-01
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
Figure 3-1. Serial Data Controls
Table 3-3. Serial Data Input and Output Data Word Sizes
IW1, OW1 IW0, OW0 FORMAT
0 0 Reserved
0 1 16-bit data
1 0 20-bit data
1 1 24-bit data
Following a reset, ensure that the clock register (0x00) is written before performing volume, treble, or bass
updates.
Commands to reconfigure the SAP can be accompanied by mute and unmute commands for quiet
operation. However, care must be taken to ensure that the mute command has completed before the SAP
is commanded to reconfigure. Similarly, the TAS3204 should not be commanded to unmute until after the
SAP has completed a reconfiguration. The reason for this is that an SAP configuration change while a
volume or bass or treble update is taking place can cause the update not to be completed properly.
When the TAS3204 is transmitting serial data, it uses the negative edge of SCLK to output a new data bit.
The TAS3204 samples incoming serial data on the rising edge of SCLK.
Submit Documentation Feedback Physical Characteristics 13
www.ti.com
23 22
SCLK
32 Clks
LRCLK (Note Reversed Phase) Left Channel
24-Bit Mode
9 8 5 4 1 0
19 18
20-Bit Mode
5 4 1 0
16-Bit Mode
1 015 14
MSB LSB
23 22
SCLK
32 Clks
Right Channel
9 8 5 4 1 0
19 18 5 4 1 0
1 015 14
MSB LSB
2-Channel I2S (Philips Format) Stereo Input/Output
T0034-04
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
3.10.1 2-Channel I2S Timing
In 2-channel I2S timing, LRCLK is LOW when left-channel data is transmitted and HIGH when
right-channel data is transmitted. SCLK is a bit clock running at 64 × fSwhich clocks in each bit of the
data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data
on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS3204 masks unused trailing data-bit positions.
14 Physical Characteristics Submit Documentation Feedback
Figure 3-2. I2S 64f
Format
S
www.ti.com
3.10.2 2-Channel Left-Justified Timing
23 22
SCLK
32 Clks
LRCLK
Left Channel
24-Bit Mode
9 8 5 4 1 0
MSB LSB
23 22
32 Clks
LRCLK
Right Channel
9 8 5 4 1 0
MSB LSB
18
20-Bit Mode
5 4 1 019
14
16-Bit Mode
1 015
18 5 4 1 019
14 1 015
2-Channel Left-Justified Stereo Input
T0034-02
In 2-channel left-justified timing, LRCLK is HIGH when left-channel data is transmitted and LOW when
right-channel data is transmitted. SCLK is a bit clock running at 64 × fS, which clocks in each bit of the
data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written
MSB first and is valid on the rising edge of the bit clock. The TAS3204 masks unused trailing data-bit
positions.
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
Figure 3-3. Left-Justified 64f
Submit Documentation Feedback Physical Characteristics 15
Format
S
www.ti.com
23 22
SCLK
32 Clks
LRCLK
Left Channel
24-Bit Mode
19 18 15 14 1 0
19 18
20-Bit Mode
15 14 1 0
16-Bit Mode
1 015 14
MSB LSB
2-Channel Right-Justified (Sony Format) Stereo Input
23 22
32 Clks
Right Channel
19 18 15 14 1 0
19 18 15 14 1 0
1 015 14
MSB LSB
T0034-03
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
3.10.3 2-Channel Right-Justified Timing
In 2-channel right-justified (RJ) timing, LRCLK is HIGH when left-channel data is transmitted and LOW
when right-channel data is transmitted. SCLK is a bit clock running at 64 × fSwhich clocks in each bit of
the data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK
toggles. In the RJ mode, the last bit clock before LRCLK transitions always clocks the LSB of data. The
data is written MSB first and is valid on the rising edge of the bit clock. The TAS3204 masks unused
leading data-bit positions.
Figure 3-4. Right-Justified 64f
3.10.4 SAP Input to SAP Output—Processing Flow
All SAP data format options other than I2S result in a two-sample delay from input to output. If I2S
formatting is used for both the input SAP and the output SAP, the polarity of LRCLK must be inverted.
However, if I2S format conversions are performed between input and output, the delay becomes either 1.5
samples or 2.5 samples, depending on the processing clock frequency selected for the audio DSP core
relative to the sample rate of the incoming data.
The I2S format uses the falling edge of LRCLK to begin a sample period, whereas all other formats use
the rising edge of LRCLK to begin a sample period. This means that the input SAP and audio DSP core
operate on sample windows that are 180 ° out of phase with respect to the sample window used by the
output SAP. This phase difference results in the output SAP outputting a new data sample at the midpoint
of the sample period used by the audio DSP core to process the data. If the processing cycle completes
all processing tasks before the midpoint of the processing sample period, the output SAP outputs this
processed data. However, if the processing time extends past the midpoint of the processing sample
period, the output SAP outputs the data processed during the previous processing sample period. In the
former case, the delay from input to output is 1.5 samples. In the latter case, the delay from input to output
is 2.5 samples.
Physical Characteristics16 Submit Documentation Feedback
Format
S
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
The delay from input to output can thus be either 1.5 or 2.5 sample times when data format conversions
are performed that involve the I2S format. However, which delay time is obtained for a particular
application is determinable and fixed for that application, providing care is taken in the selection of
MCLK_IN/XTAL_IN with respect to the incoming sample clock, LRCLK.
Submit Documentation Feedback Physical Characteristics 17
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
4 Algorithm and Software Development Tools for TAS3204
The TAS3204 algorithm and software development tool set is a combination of classical development
tools and graphical development tools. The tool set is used to build, debug, and execute programs in both
the audio DSP and 8051 sections of the TAS3204.
Classical development tooling includes text editors, compilers, assemblers, simulators, and source-level
debuggers. The 8051 can be programmed exclusively in ANSI C.
The 8051 tool set is an off-the-shelf tool set, with modifications as specified in this document. The 8051
tool set is a complete environment with an IDE, editor, compiler, debugger, and simulator.
The audio DSP core is programmed exclusively in assembly. The audio DSP tool set is a complete
environment with an IDE, context-sensitive editor, assembler, and simulator/debugger.
Graphical development tooling provides a means of programming the audio DSP core and 8051 through a
graphical drag-and-drop interface using modular audio software components from a component library.
The graphical tooling produces audio DSP assembly and 8051 ANSI C code as well as coefficients and
data. The classical tools can also be used to produce the executable code.
In addition to building applications, the tool set supports the debug and execution of audio DSP and 8051
code on both simulators and EVM hardware.
18 Algorithm and Software Development Tools for TAS3204 Submit Documentation Feedback
www.ti.com
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
5 Clock Controls
Clock management for the TAS3204 consists of two control structures:
• Master clock management
– Oversees the selection of the clock frequencies for the 8051 microprocessor, the I2C controller, and
the audio DSP core
– The master clock (MCLK_IN or XTAL_IN) is the source for these clocks.
– In most applications, the master clock drives an on-chip digital phase-locked loop (DPLL), and the
DPLL output drives the microprocessor and audio DSP clocks.
– Also available is the DPLL bypass mode, in which the high-speed master clock directly drives the
microprocessor and audio DSP clocks.
• Serial audio port (SAP) clock management
– Oversees SAP master/slave mode
– Controls output of SCLKOUT, and LRCLK in the SAP master mode
Input pin MCLK_IN or XTAL_IN provides the master clock for the TAS3204. Within the TAS3204, these
two inputs are combined by an OR gate and, thus, only one of these two sources can be active at any one
time. The source that is not active must be logic 0.
The TAS3204 only supports dynamic sample-rate changes between any of the supported sample
frequencies when a fixed-frequency master clock is provided. During dynamic sample-rate changes, the
TAS3204 remains in normal operation and the register contents are preserved. To avoid producing audio
artifacts during the sample-rate changes, a volume or mute control can be included in the application
firmware that mutes the output signal during the sample-rate change. The fixed-frequency clock can be
provided by a crystal attached to XTAL_IN and XTAL_OUT or an external 3.3-V fixed-frequency TTL
source attached to MCLK_IN.
When the TAS3204 is used in a system in which the master clock frequency (f
TAS3204 must be reset during the frequency change. In these cases, the procedure shown in Figure 5-1
should be used.
) can change, the
MCLK
Submit Documentation Feedback Clock Controls 19
www.ti.com
Are
Clocks
Stable?
No
Yes
RESET Pin = Low
Enable Mute and
Wait for Completion
Change f
MCLK
RESET Pin = High
After
TAS3204
Initializes,
Re-initialize
I C Registers
2
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
FSSample Ch Per LRCLK Ch Per LRCLK PLL F
Rate (kHz) SDIN Ratio SDOUT (FS) Multiplier (MHz)
20 Clock Controls Submit Documentation Feedback
Figure 5-1. Master Clock Frequency (f
) Change Procedure
MCLK
When the serial audio port (SAP) is in the master mode, the SAP uses the XTAL_IN master clock to drive
the serial port clocks SCLK_OUT and LRCLK. When the SAP is in the slave mode, MCLK_IN, SCLK_IN,
and LRCLK_IN are input clocks. SCLK_OUT and LRCLK_OUT are derived from SCLK_IN and
LRCLK_IN, respectively.
See Clock Register (0x00), Section 9.1 , for information on programming the clock register.
Table 5-1. TAS3204 MCLK and LRCLK Common Values (MCLK = 24.576 MHz or MCLK = 22.579 MHz)
MCLK/
44.1 2 512 22.579 64 2.822 64 2 64 5.5 124.2 2816
48 2 256 24.576 64 3.072 64 2 64 5.5 135.2 2816
Master Mode, 2 Channels In, 2 Channels Out
48 2 256 24.576 N/A N/A 64 2 64 5.5 135.2 2816
( × fS)
Slave Mode, 2 Channels In, 2 Channels Out
MCLK SCLKIN SCLK_IN SCLK_OUT
Freq Rate Freq Rate f
(MHz) ( × fS) (MHz) ( × fS)
DSPCLK
/f
DSPCLK
S
www.ti.com
6 Microprocessor Controller
The 8051 microprocessor receives and distributes I2C write data, retrieves and outputs to the I2C bus
controllers the required I2C read data, and participates in most processing tasks requiring multiframe
processing cycles. The microprocessor has its own data RAM for storing intermediate values and queuing
I2C commands, a fixed boot-program ROM, and a program RAM. The microprocessor boot program
cannot be altered. The microprocessor controller has specialized hardware for master and slave interface
operation, volume updates, and a programmable interval timer interrupt. For more information see the
TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067 ).
The TAS3204 has a slave-only I2C interface that is compatible with the Inter IC (I2C) bus protocol and
supports both 100-kbps and 400-kbps data-transfer rates for multiple 4-byte write and read operations
(maximum is 20 bytes). The slave I2C control interface is used to program the registers of the device and
to read device status.
The TAS3204 also has a master-only I2C interface that is compatible with the I2C bus protocol and
supports 375-kbps data transfer rates for multiple 4-byte write and read operations (maximum is 20 bytes).
The master I2C interface is used to load program and data from an external I2C EEPROM.
On power up of the TAS3204, the slave interface is disabled and the master interface is enabled.
Following a reset, the TAS3204 disables the slave interface and enables the master interface. Using the
master interface, the TAS3204 automatically tests to see if an I2C EEPROM is at address 1010x. The
value x can be chip select, other information, or don’t cares, depending on the EEPROM selected. If a
memory is present and it contains the correct header information and one or more blocks of
program/memory data, the TAS3204 loads the program, coefficient, and/or data memories from the
EEPROM. If a memory is present, the download is complete when a header is read that has a zero-length
data segment. At this point, the TAS3204 disables the master I2C interface, enables the slave I2C
interface, and starts normal operation.
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
If no memory is present or if an error occurred during the EEPROM read, TAS3204 disables the master
I2C interface, enables the slave I2C interface, and loads the unprogrammed default configuration. In this
default configuration, the TAS3204 streams audio from input to output if the GPIO pin is LOW. The master
and slave interfaces do not operate simultaneously.
In the slave mode, the I2C bus is used to:
• Load the program and coefficient data
– Microprocessor program memory
– Microprocessor extended memory
– Audio DSP core program memory
– Audio DSP core coefficient memory
– Audio DSP core data memory
• Update coefficient and other control values
• Read status flags
Once the microprocessor program memory has been loaded, it cannot be updated until the TAS3204 has
been reset.
The master and slave modes do not operate simultaneously.
When acting as an I2C master, the data transfer rate is fixed at 375 kHz, assuming MCLK_IN or
XTAL_IN = 24.576 MHz.
When acting as an I2C slave, the data transfer rate is determined by the master device on the bus.
The I2C communication protocol for the I2C slave mode is shown in Figure 6-1 .
Submit Documentation Feedback Microprocessor Controller 21
www.ti.com
SDA
SCL
0S
Start
(By Master)
Slave Address
(By Master)
0 1 1 0 1
C
S
0
Read or Write
(By Master)
R
/
W
A
C
K
M
S
B
Acknowledge
(By TAS3204)
L
S
B
Data Byte
(By Transmitter)
A
C
K
Acknowledge
(By Receiver)
M
S
B
L
S
B
Data Byte
(By Transmitter)
A
C
K
Acknowledge
(By Receiver)
S
Stop
(By Master)
MSB MSB-1 MSB-2 LSB
Start Condition
SDA ↓While SCL = 1
Stop Condition
SDA ↑While SCL = 1
(1)
TAS3204
AUDIO DSP
WITH ANALOG INTERFACE
SLES197 – APRIL 2007
Figure 6-1. I2C Slave-Mode Communication Protocol
6.1 8051 Microprocessor Addressing Mode
The 256 bytes of internal data memory address space is accessible using indirect addressing instructions
(including stack operations). However, only the lower 128 bytes are accessible using direct addressing.
The upper 128 bytes of direct address Data Memory space are used to access Extended Special Function
Registers (ESFRs).
6.1.1 Register Banks
There are four directly addressable register banks, only one of which may be selected at one time. The
register banks occupy Internal Data Memory addresses from 00 hex to 1F hex.
6.1.2 Bit Addressing
The 16 bytes of Internal Data Memory that occupy addresses from 20 hex to 2F hex are bit addressable.
SFRs that have addresses of the form 1XXXX000 binary are also bit addressable.
6.1.3 External Data Memory
External data memory occupies a 2K × 8 address space. This space contains the External Special
Function Data Registers (ESFRs). The ESFR permit access and control of the hardware features and
internal interfaces of the TAS3204.
Microprocessor Controller22 Submit Documentation Feedback
Loading...