TEXAS INSTRUMENTS TAS3103 Technical data

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Data M anua

February 2004 Digital Audio Solutions

SLES038C

IMPORTANT NOTICE

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Contents

Section Title Page

1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Terminal Assignments 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Hardware Block Diagram 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Functional Block Diagram 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Ordering Information 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Terminal Functions 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 Operational Modes 1−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7.1 Terminal-Controlled Modes 1−9. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

1.7.2 I

2 Hardware Architecture 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Input and Output Serial Audio Ports (SAPs) 2−3. . . . . . . . . . . . . . . . . . . . . .

2.1.1 SAP Configuration Options 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 Processing Flow—SAP Input to SAP Output 2−10. . . . . . . . . . .

2.2 DPLL and Clock Management 2−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Controller 2−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 8051 Microprocessor 2−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 I

2.4 Digital Audio Processor (DAP) Arithmetic Unit 2−21. . . . . . . . . . . . . . . . . . .

2.5 Reset 2−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Power Down 2−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Watchdog Timer 2−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 General-Purpose I/O (GPIO) Ports 2−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.1 GPIO Functionality—I

2.8.2 GPIO Functionality—I

3 Firmware Architecture 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 I2C Coefficient Number Formats 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 28-Bit 5.23 Number Format 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.2 48-Bit 25.23 Number Format 3−2. . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Input Crossbar Mixers 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 3D Effects Block 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 CH1/CH2 Effects Block 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 CH3 Effects Block 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Biquad Filters 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Bass and Treble Processing 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 Treble and Bass Processing and Concurrent I

3.6 Soft Volume/Loudness Processing 3−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Bus-Controlled Modes 1−10. . . . . . . . . . . . . . . . . . . . . . . . . . .

2

C Bus Controller 2−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

C Master Mode 2−25. . . . . . . . . . . . . . . .

2

C Slave Mode 2−26. . . . . . . . . . . . . . . . . .

2

C

Read Transactions 3−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

3.6.1 Soft Volume 3−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.2 Loudness Compensation 3−24. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.3 Time Alignment and Reverb Delay Processing 3−26. . . . . . . . . .

3.7 Dynamic Range Control (DRC) 3−29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.1 DRC Implementation 3−31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.2 Compression/Expansion Coefficient Computation

Engine Parameters 3−33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.3 DRC Compression/Expansion Implementation Examples 3−35

3.8 Spectrum Analyzer/VU Meter 3−45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9 Dither 3−47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.1 Dither Seeds 3−48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.2 Dither Mix Options 3−50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.3 Dither Gain Mixers 3−50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9.4 Dither Statistics 3−51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 Output Crossbar Mixers 3−54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Electrical Specifications 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Absolute Maximum Ratings Over Operating Temperature Ranges 4−1. .

4.2 Recommended Operating Conditions 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Electrical Characteristics Over Recommended Operating

Conditions 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 TAS3100 Timing Characteristics 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1 Master Clock Signals Over Recommended Operating

Conditions 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.2 Control Signals Over Recommended Operating Conditions

4.4.3 Serial Audio Port Slave Mode Signals Over Recommended

Operating Conditions ) 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.4 Serial Audio Port Master Mode Signals Over Recommended

Operating Conditions 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

4.4.5 I

C Slave Mode Interface Signals Over Recommended

Operating Conditions 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

A.1 I

C Subaddress Table A−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.2 TAS3103 Firmware Block Diagram A−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

List of Illustrations

Figure Title Page

2−1 TAS3103 Detailed Hardware Block Diagram 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Discrete Serial Data Formats 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 Four-Channel TDM Serial Data Formats 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 SAP Configuration Subaddress Fields 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 Recommended Procedure for Issuing SAP Configuration Updates 2−5. . . . . . .

2−6 Format Options: Input Serial Audio Port 2−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7 TDM Format Options: Output Serial Audio Port 2−8. . . . . . . . . . . . . . . . . . . . . . . .

2−8 Discrete Format Options: Output Serial Audio Port 2−9. . . . . . . . . . . . . . . . . . . . .

2−9 Word Size Settings 2−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 8 CH TDM Format Using SAP Modes 0101 and 1000 2−10. . . . . . . . . . . . . . . .

2−11 6 CH Data, 8 CH Transfer TDM Format Using SAP Modes

0101 and 1000 2−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−12 SAP Input-to-Output Latency 2−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−13 SAP Input-to-Output Latency for I

2−14 DPLL and Clock Management Block Diagram 2−15. . . . . . . . . . . . . . . . . . . . . . .

2−15 I 2−16 I

2

C Slave Mode Communication Protocol 2−17. . . . . . . . . . . . . . . . . . . . . . . . . . .

2

C Subaddress Access Protocol 2−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−17 Digital Audio Processor Arithmetic Unit Block Diagram 2−21. . . . . . . . . . . . . . . .

2−18 DAP Arithmetic Unit Data Word Structure 2−22. . . . . . . . . . . . . . . . . . . . . . . . . . .

2−19 DAP ALU Operation With Intermediate Overflow 2−22. . . . . . . . . . . . . . . . . . . . .

2−20 TAS3103 Reset Circuitry 2−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−21 GPIO Port Circuitry 2−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−22 Volume Adjustment Timing—Master I

3−1 5.23 Format 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 Conversion Weighting Factors—5.23 Format to Floating Point 3−1. . . . . . . . . . .

3−3 Alignment of 5.23 Coefficient in 32-Bit I

3−4 25.23 Format 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 Alignment of 5.23 Coefficient in 32-Bit I2C Word 3−3. . . . . . . . . . . . . . . . . . . . . . .

3−6 Alignment of 25.23 Coefficient in Two 32-Bit I

3−7 Serial Input Port to Processing Node Topology 3−5. . . . . . . . . . . . . . . . . . . . . . . . .

3−8. Input Mixer and Effects Block Topology—Internal Processing

Nodes A, B, C, D, E, and F 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−9 Input Mixer Topology—Internal Processing Nodes G and H 3−7. . . . . . . . . . . . . .

2

S Format Conversions 2−12. . . . . . . . . . . . .

2

C Mode 2−27. . . . . . . . . . . . . . . . . . . . . . .

2

C Word 3−2. . . . . . . . . . . . . . . . . . . . . . .

2

C Words 3−3. . . . . . . . . . . . . . . . .

v

3−10 TAS3103 3D Effects Processing Block 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11 Biquad Filter Structure and Coefficient Subaddress Format 3−10. . . . . . . . . . . .

3−12 Bass and Treble Filter Selections 3−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13 Bass and Treble Application Example—Subaddress Parameters 3−14. . . . . . .

3−14 I

2

C Bass/Treble Activity Monitor Procedure 3−16. . . . . . . . . . . . . . . . . . . . . . . . .

3−15 Soft Volume and Loudness Compensation Block Diagram 3−18. . . . . . . . . . . . .

3−16 Detailed Block Diagram—Soft Volume and Loudness Compensation 3−25. . .

3−17 Delay Line Memory Implementation 3−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−18 Maximum Delay Line Lengths 3−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−19 DRC Positioning in TAS3103 Processing Flow 3−29. . . . . . . . . . . . . . . . . . . . . . .

3−20 Dynamic Range Compression (DRC) Transfer Function Structure 3−30. . . . . .

3−21 DRC Block Diagram 3−32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−22 DRC Input Word Structure for 0-dB Channel Processing Gain 3−36. . . . . . . . .

3−23 DRC Transfer Curve—Example 1 3−38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−24 DRC Transfer Curve—Example 2 3−40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−25 DRC Transfer Curve—Example 3 3−42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−26 DRC Transfer Curve—Example 4 3−44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−27 Spectrum Analyzer/VU Meter Block Diagram 3−46. . . . . . . . . . . . . . . . . . . . . . . .

3−28 Logarithmic Number Conversions—Spectrum Analyzer/VU Meter 3−47. . . . . .

3−29 Dither Data Block Diagram 3−49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−30 Dither Data Magnitude (Gain = 1.0) 3−51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−31 Triangular Dither Statistics 3−52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−32 Triangular Dither Statistics 3−53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−33 Processing Node to Serial Output Port Topology 3−55. . . . . . . . . . . . . . . . . . . . .

3−34 Output Crossbar Mixer Topology 3−56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 Master Clock Signals Timing Waveforms 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 Control Signals Timing Waveforms 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3 Serial Audio Port Slave Mode Timing Waveforms 4−5. . . . . . . . . . . . . . . . . . . . . .

4−4 TAS3100 Serial Audio Port Master Mode Timing Waveforms 4−6. . . . . . . . . . . . .

2

4−5 I 4−6 I

C SCL and SDA Timing Waveforms 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

C Start and Stop Conditions Timing Waveforms 4−8. . . . . . . . . . . . . . . . . . . . . .

vi

List of Tables

Table Title Page

2−1 TAS3103 Throughput Latencies vs MCLK and LRCLK 2−13. . . . . . . . . . . . . . . . .

2−2 TAS3103 Clock Default Settings 2−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

2−3 I 2−4 Four Byte Write Exceptions—Reserved and Factory-Test I

2−5 Four Byte Read Exceptions—Reserved and Factory-Test I 2−6 GPIO Port Functionality—I

3−1 Biquad Filter Breakout 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 Bass Shelf Filter Indices for 1/2-dB Adjustments 3−14. . . . . . . . . . . . . . . . . . . . . .

3−3 Treble Shelf Filter Indices for 1/2-dB Adjustments 3−15. . . . . . . . . . . . . . . . . . . . .

3−4 Volume Adjustment Gain Coefficients 3−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 DRC Example 2 Parameters 3−39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−6 DRC Example 3 Parameters 3−41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−7 DRC Example 4 Parameters 3−45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−8 Mixer Gain Setting for LSB Dither Data Insertion 3−50. . . . . . . . . . . . . . . . . . . . . .

C EEPROM Data 2−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

C

Subaddresses 2−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

C

Subaddresses 2−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

C Master Mode 2−25. . . . . . . . . . . . . . . . . . . . . . . . . .

vii

viii

1 Introduction

The TAS3103 is a fully configurable digital audio processor that preserves high-quality audio by using a 48-bit data path, 28-bit filter coefficients, and a single cycle 28 x 48-bit multiplier and 76-bit accumulator. Because of the coefficient-configurable fixed-program architecture of the TAS3103, a complete set of user-specific audio processing functions can be realized, with short development times, in a small, low power , low-cost device. A personal computer (PC) GUI-based software development package and a comprehensive evaluation board provide additional facilities to further reduce development times. The TAS3103 uses 1.8-V core logic with 3.3-V I/O buffers, and requires only

3.3-V power. The TAS3103 is available in a 38-pin TSSOP package.

1.1 Features

• Audio Input/Output

− Four Serial Audio Input Channels

− Three Serial Audio Output Channels

− 8-kHz to 96-kHz Sample Rates Supported

− 15 Stereo/TDM Data Formats Supported

− Input/Output Data Format Selections Independent

− 16-, 18-, 20-, 24-, and 32-Bit Word Sizes Supported

2

• Serial Master/Slave I

• Three Independent Monaural Processing Channels

− Programmable Four Stereo Input Digital Mixer

− 3D Effect and Reverb Structure and Filters

− Programmable 12 Band Digital Parametric EQ

− Programmable Digital Bass and Treble Controls

− Programmable Digital Soft Volume Control (24 dB to −-∞ dB)

− Soft Mute/Unmute

− Programmable Dither

− Programmable Loudness Compensation

− VU Meter and Spectral Analysis I

− Programmable Channel Delay (Up to 42 ms at 48 kHz)

− 192-dB Dynamic Range (Supports Up to 32-Bit Audio Data)

− Dual Threshold Dynamic Range Compression/Expansion

C Control Channel

2

C Output

• Electrical and Physical

− Single 3.3-V Power Supply

− 38-Pin TSSOP Package

− Low Power Standby

1−1

1.2 Terminal Assignments

DBT PACKAGE

(TOP VIEW)

SCLKIN

PWRDN

REGULATOR_EN

XT ALI (1.8-V logic)

XTALO (1.8-V logic)

AVDD_BYPASS_CAP

A_VDDS (3.3 V)

AVSS

MCLKI

TEST

MICROCLK_DIV

I2C_SDA

I2C_SCL

SDIN1 SDIN2 SDIN3

SDIN4 GPIO0 GPIO1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

LRCLK

38

ORIN

37

SCLKOUT2

36

SCLKOUT1

35

MCLKO

34

SDOUT3

33

SDOUT2

32

VDDS (3.3 V)

31

SDOUT1

30

DVDD_BYPASS_CAP

29

DVSS

28

I2CM_S

27

RST

26

CS1

25

CS0

24

PLL1

23

PLL0

22

GPIO3

21

GPIO2

20

1−2

1.3 Hardware Block Diagram

SDIN1 SDIN2 SDIN3 SDIN4

SDOUT1 SDOUT2 SDOUT3

SCLKOUT2 SCLKOUT1

MCLKO

LRCLK

SCLKIN

TEST

PWRDN

PLL1 PLL0

XTALO

XTALI

RST

Serial

Audio

Port

Oscillator

and

PLL

External

Data

RAM

Code ROM

64 64 64 64 64 64 64

Internal

Data RAM

8051 MCU

(8-Bit)

Controller

Control

Registers

Data Path

76-Bit

ALU

Digital Audio Processor

28

2828

48

Memory

Interface

54

Delay

Memory

(4K x 16)

Volume Update

8

4

COEF

RAM

Data RAM

Code ROM

I2C

Serial

Interface

I2C_SDA I2C_SCL CS1 CS0

I2CM_S

GPIO[3:0]

1−3

ORIN

SDOUT1

Multi-

SDOUT2

PCM

mode

Cross-

Output

to

bar

Serial

Output

Multi-

plexer

SDOUT3

Port

AVSS A_VDDS

VDDS DVSS

AVDD_

BYPASS_

DVDD_

BYPASS_

M_S

I2C_

Test PWRDN

RST

GPIO(3:0) CS0 CS1PLL1

CAP

Voltage Regulation

Microprocessor

or

VU Meter

Spectrum Analyzer

Ch2

Center

Ch1

DRC

Ganged

Dither

Programmable

Delay

Loudness

Compensation

Soft

Volume

and

Bass

Treble

Dither

Programmable

Delay

Loudness

Compensation

Soft

Volume

and

Bass

Treble

3 Mono Processing Channels

Ch3

Dither

Programmable

Delay

DRC

Loudness

Compensation

Soft

Volume

and

Bass

Treble

S Clock Input/Generation

2

I

LRCLK SCLKIN SCLKOUT1 SCLKOUT2 MCLKO

SCL

I2C_

SDA

I2C_

and

PLL

Dividers

PLL0 MC/Div

XTALI

MCLKI

1.4 Functional Block Diagram

1−4

Oscillator

XTALO

SDIN1

12

Ch1

Multi-

Filters

Biquad

3D

Mode

Input

Cross-

Mode

Serial

SDIN2

bar

to

Effects

Mixer

PCM

12

Ch2

Block

Input

SDIN3

Filters

Biquad

Port

SDIN4

12

Ch3

Filters

Biquad

Ch3

1.5 Ordering Information

PULLUP/

DESCRIPTION

PULLUP/

1.6 Terminal Functions

PLASTIC

T

A

0°C to 70°C TAS3103DBT

−40°C to 85°C TAS3103IDBT

38-PIN TSSOP

(DBT)

TERMINAL

NAME NO. I/O TYPE

A_VDDS (3.3 V) 7 PWR The PWR pin is used to input 3.3-V power to the DPLL and clock oscillator.

AVDD_BYPASS_CAP 6 PWR AVDD_BYPASS_CAP is a pinout of the internally regulated 1.8-VDC power

AVSS 8 PWR AVSS is the ground reference for the internal DPLL and oscillator circuitry.

CS0 24 I D CS0 is the LSB of a 2-bit code used to generate part of an I2C device address

CS1 25 I D CS1 is the MSB of a 2-bit code used to generate part of an I2C device address

DVDD_BYPASS_CAP 29 PWR DVDD_BYPASS_CAP is a pin-out of the internally regulated 1.8-V power

DVSS 28 PWR DVSS is the digital ground pin. None GPIO0 18 I/O D GPIO0 is a general-purpose I/O, controlled by the internal microprocessor

GPIO1 19 I/O D GPIO1 is a general-purpose I/O, controlled by the internal microprocessor

GPIO2 20 I/O D GPIO2 is a general-purpose I/O, controlled by the internal microprocessor

GPIO3 21 I/O D GPIO3 is a general-purpose I/O, controlled by the internal microprocessor

I2CM_S 27 I D I2CM_S is a non-latched input that determines whether the TAS3103 acts as

(1)

This pin can be connected to the same power source used to drive the DVSS power pin. To achieve low DPLL jitter, this pin should be bypassed to AVSS with a 0.01-µF capacitor (low ESR preferable).

used by the DPLL and crystal oscillator . This pin should be connected to pin 8 with a 0.01-µF capacitor (low ESR preferable). This pin must not be used to power external devices.

This pin needs to reference the same ground as DVSS power pin. To achieve low DPLL jitter, ground noise at this pin must be minimized. The availability of the AVSS pin allows a designer to use optimizing techniques such as star ground connections, separate ground planes, or other quiet ground distribution techniques to achieve a quiet ground reference at this pin.

that makes it possible to address four TAS3103 ICs on the same bus without additional chip select logic. The pulldowns on the inputs select 00 as a default when neither pin is connected.

that makes it possible to address four TAS3103 ICs on the same bus without additional chip select logic.

used by all internal digital logic. This pin must not be used to power external devices. A low ESR capacitor of at least 470 nF should be placed as close to the device as possible between this pin and pin 28.

through I2C commands. When in the I2C master mode, GPIO0 serves as a volume up command for CH1/CH2.

through I2C commands. When in the I2C master mode, GPIO1 serves as a volume down command for CH1/CH2.

through I2C commands. When in the I2C master mode, GPIO2 serves as a volume up command for CH3.

through I2C commands. When in the I2C master mode, GPIO3 serves as a volume down command for CH3.

an I2C master or slave. Logic high, or no connection, sets the TAS3103 as an I2C master device. A logic low sets the TAS3103 as an I2C slave device. As a master I2C device, the TAS3103 I2C port must have access to an external EEPROM for input.

DOWN

None

Pulldown

None

Pullup

(2)

1−5

TERMINAL

(1)

TYPE

NAME

I2C_SCL 13 I/O D I2C_SCL is the I2C clock pin. When the TAS3103 I2C port is a master,

I/ONO.

I2C_SCL is (1/2N) x (1/(M+1)) x 1/10 times the microprocessor clock, where N and M are set to 2 and 8 respectively. When the TAS3103 I2C port is a slave, input clock rates up to 400 kHz can be supported. This pin must be provided an external pullup (5 kΩ is recommended for most applications).

DESCRIPTION

PULLUP/

(2)

DOWN

External

pullup

required

I2C_SDA 12 I/O D I2C_SDA is the I2C bidirectional data pin. The TAS3103 I2C port can support

data rates up to 400K bits/sec. This pin must be provided an external pullup (5 kΩ is recommended for most applications).

LRCLK 38 I/O D LRCLK is either an input or an output, depending on whether the T AS3103 is in

a master or slave serial audio port mode, which is determined by bit 22 of subaddress 0xF9.

MCLKI 9 I D MCLKI is a master clock input that provides an alternative to using a fixed

crystal frequency. In DPLL modes, the input frequency of this clock can range from 2.8 MHz to 24.576 MHz. In PLL bypass mode, frequencies up to 136 MHz can be used. Whenever MCLKI is not used and XTALI/XTALO provide the master clock input, MCLKI must be grounded.

MCLKO 34 O D MCLKO is the master output clock pin. It is produced by dividing MCLKI/XTALI

by 1, 2, or 4 (depending on the setting of a subaddress control field). MCLKO is provided to interconnect, without the need for additional glue logic, the TAS3103 interfaces chips that require different multiples of the audio sample rate (FS) as a master clock.

MICROCLK_DIV 11 I D MICROCLK_DIV sets the division ratio between the digital audio processing

clock and the internal microprocessor clock. The audio-processing clock is the DPLL output clock if PLL_bypass is not enabled. The audio-processing clock is MCLKI/XTALI master clock if PLL_bypass is enabled. Logic high on this pin sets the microprocessor clock equal to the audio-processing clock. A logic low sets the microprocessor clock to 1/4 the digital audio-processing clock. MICROCLK_DIV must be set low if the audio processing clock is > 36 MHz. MICROCLK_DIV must be set high if the audio processing clock is ≤ 36 MHz.

ORIN 37 I D ORIN allows the processing of a multichannel signal set through two

TAS3103s without any additional components. One use of ORIN would be to fully emulate a 6-channel audio processor at speeds up to a 96-kHz sample rate with only two TAS3103s and no glue logic.

The two-chip configuration is accomplished by wiring the SDOUT1 port of one of the two TAS3103 chips to the ORIN port of the second T AS3103. Internal to the chip, the ORIN input is OR’ed with internal SDOUT1 data to generate the resulting output data on channel SDOUT1. For TDM output formats, the SDOUT1 outputs of the two chips differ in phasing in both the left and right channels to arrive at the proper composite output. For discrete outputs, one chip contributes the left channel of the composite SDOUT1, and the other chip contributes the right channel of the composite SDOUT1.

If not used, ORIN must be connected to ground.

External

pullup

required

Pulldown

None

Pulldown

PLL0 22 I D PLL0 is the LSB of a 2-bit code used to select four different modes of DPLL

multiplexer/input divider operation. PLL[1:0] values of 00, 01, and 10 select the DPLL input clock to be MCLKI/XTALI divided by 1, 2, and 4 respectively. A value of 11 results in MCLKI/XT ALI being substituted for the DPLL output. The pullup/pulldown combination provides a default of 01 when neither pin is connected.

PLL1 23 I D PLL1 is the MSB of a 2-bit code used to select four different modes of DPLL

multiplexer/input divider operation. PLL[1:0] values of 00, 01, and 10 select the DPLL input clock to be MCLKI/XTALI divided by 1, 2, and 4 respectively. A value of 11 results in MCLKI/XT ALI being substituted for the DPLL output. The pullup/pulldown combination provides a default of 01 when neither pin is connected.

1−6

Pullup

Pulldown

TERMINAL

(1)

TYPE

NAME

PWRDN 2 I D PWRDN powers down all logic and stops all clocks whenever logic high is

REGULATOR_EN 3 I D REGULATOR_EN is only used in factory tests. This pin should always be tied

RST 26 I D RST is the master reset input. Applying a logic low to this pin generates a

SCLKIN 1 I D SCLKIN is the serial audio port (SAP) input data clock. This clock is only used

SCLKOUT1 35 O D SCLKOUT1 is one of two serial output bit clocks. It is divided from

SCLKOUT2 36 O D SCLKOUT2 is one of two serial output bit clocks. It is divided from

SDIN1 14 I D SDIN1, SDIN2, SDIN3, and SDIN4 are the four TAS3103 serial data input

SDIN2 15 I D SDIN2 is one of the four TAS3103 serial data input ports. SDIN2 supports four

SDIN3 16 I D SDIN3 is one of the four TAS3103 serial data input ports. SDIN4 supports four

SDIN4 17 I D SDIN4 is one of the four TAS3103 serial data input ports. SDIN4 supports four

SDOUT1 30 O D SDOUT1, SDOUT2, and SDOUT3 are the three TAS3103 serial data output

SDOUT2 32 O D SDOUT2 is one of the three serial data output ports. SDOUT2 supports four

SDOUT3 33 O D SDOUT3 is one of the three serial data output ports. SDOUT3 supports four

TEST 10 I D TEST is only used in factory tests. This pin must be left unconnected or

I/ONO.

applied. However, the coefficient memory remains stable through a power down cycle, as long as a reset is not sent after a power down cycle.

to ground.

master reset. The master reset results in all coefficients being set to their power-up default state, all data memories being cleared, and all logic signals being returned to their default values.

when the SAP is a slave. In master mode, SCLKOUT1 internally provides the serial input clock (SCLKOUT1 from a given TAS3103 must not be connected to SCLKIN on the same TAS3103 chip).

MCLKI/XTALI in master mode, and SCLKIN in slave mode. Subaddress control fields determine the divide ratio in both cases. When the serial audio port is in a master mode, SCLKOUT1 is used to receive incoming serial data and should be wired to the data source(s) providing data to the SDIN inputs.

MCLKI/XTALI in master mode, and SCLKIN in slave mode. Subaddress control fields determine the divide ratio in both cases. SCLKOUT2 is always used to clock out serial data from the three serial SDOUT output data channels. SCLKOUT2 is provided separately from SCLKOUT1 to allow discrete in to TDM out and TDM in to discrete out data format conversions without the use of external glue logic.

ports. All four input ports support four discrete (stereo) data formats. SDIN1 is the only data input port that also supports eleven time division multiplexed data formats. All four ports are capable of receiving data with bit rates up to

24.576 MHz.

discrete (stereo) data formats, and is capable of receiving data with bit rates up to 24.576 MHz.

ports. All three output ports support four discrete (stereo) data formats. SDOUT1 is the only data output port that also supports eleven time division multiplexed data formats. All three ports are capable of outputting data at bit rates up to 24.576 MHz.

discrete (stereo) data formats, and is capable of outputting data at bit rates up to 24.576 MHz.

grounded.

DESCRIPTION

PULLUP/

PULLUP/ DOWN

DOWN

Pulldown

None

Pullup

Pulldown

None

Output

Pulldown

None

Pulldown

(2)

1−7

TERMINAL

(1)

TYPE

NAME

VDDS (3.3 V) 31 - PWR VDDS is the 3.3-V pin that powers (1) the 1.8-V internal power regulator used

XTALI (1.8-V logic) 4 I A XTALO and XTALI provide a master clock for the TAS3103 via use of an

XTALO (1.8-V logic) 5 O A XTALO and XTALI provide a master clock for the TAS3103 via use of an

NOTES: 1. TYPE: A = analog; D = 3.3-V digital; PWR = power/ground/decoupling

2. All pullups are 20-µA weak pullups and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to assure proper input logic levels if the pins are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive inputs with pullups must be able to sink 20 µA while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must be able to source 20 µA, while maintaining a logic 1 drive level.

3. Crystal type and recommended circuit:

I/ONO.

to supply logic power to the chip and (2) the I/O ring. It is recommended that this pin be bypassed to DVSS (pin 28) with a low ESR capacitor in the range of

0.01 µF.

external fundamental mode crystal. XTALI is the 1.8-V input port for the oscillator circuit. See Note 3 for recommended crystal type and accompanying circuitry. This pin should be grounded when the MCLKI pin is used as the source for the master clock.

external fundamental mode crystal. XTALO is the 1.8-V output drive to the crystal. XTALO can support crystal frequencies between 2.8 MHz and 20 MHz. See Note 3 for recommended crystal type and accompanying circuitry. This pin should be left unconnected in applications using an external clock input to MCLKI.

DESCRIPTION

TAS3103

PULLUP/

(2)

DOWN

None

OSC

C

1

C

2

r

d

Circuit

XO

XI

AVSS

• Crystal type = parallel-mode, fundamental-mode crystal = drive level control resistor—vendor specified

• r

d

• C

= Crystal load capacitance (capacitance of circuitry between the two terminals of the crystal)

L

• C

= (C1× C2) / (C1 + C2) + CS (where CS = board stray capacitance ~2 pF)

L

− Example: Vendor recommended C

= 18 pF, CS = 3 pF ⇒ C1 = C2 = 2 x (18 − 3) = 30 pF

L

1.7 Operational Modes

The TAS3103 operation is governed by I/O terminal voltage level settings and register / coefficient settings within the TAS3103. The terminal settings are wholly sufficient to address all external environments - allowing the remaining configuration settings to be determined by either I

2

the I

C master mode is selected).

2

C commands or by the content of an I2C serial EEPROM (when

1−8

1.7.1 Terminal-Controlled Modes

ÎÎ

1.7.1.1 Clock Control

PLL1 PLL0 DAP CLOCK

0 0 11 x MCLK 0 1 (11 x MCLK)/2 1 0 (11 x MCLK)/4 1 1 MCLK (PLL bypass)

MICROCLK_DIV MICROPROCESSOR CLOCK

XTALIMCLKI

PLL0

0 DAP clock/4 1 DAP clock

PLL1

MICROCLK_DIV

1.7.1.2 I2C Bus Setup

MCLK

Reference

Divider

PLL

÷ 11

Audio Processor

1400 x Fs 3 DAP Clock 3 136 MHz

SLAVE ADDRESS CS1 CS0

0x68/69 0 0

0x6A/6B 0 1

0x6C/D 1 0

0x6E/6F 1 1

I2CM_S I2C BUS MODE

0 Slave 1 Master

TAS3103 I2C Slave Address

Digital

(DAP) Clock

Microprocessor

Scaler

Microprocessor

Clock < 36 MHz

SDA

SCL

Start

a6 = 0 a5 = 1 a4 = 1 a3 = 0 a2 = 1 a1=CS1 a0=CS0 R/W ACK

123456789

1.7.1.3 Power-Down/Sleep Selection

PWRDN POWER STATUS

0 Active 1 Power down/sleep

1−9

download. If comparison fails, a second attempt is made. If the second

Node

28

Gain Coefficient G0

48

(Format = 5.23)

48

28

0x81_42_24_18

C master mode only

2

C mode, the two check words are compared after EEPROM

2

Gain Coefficient

(Format = 5.23)

32 or 48

C mode, the default value for both check words is:

2

0

b

48

Magnitude

76

Σ

76

28

48

a

Truncation

b

Node

comparison fails, the parameters default to the slave default values.

S Check words apply to I

S In master I

S In slave I

1

Ack

l

s

b

Ack

l

s

b

a

Ack

l

s

b

48

−1

z

48

28

1

76

28

1

48

−1

z

2

a

Ack

l

s

b

−1

z

48

28

2

a

76

28

2

b

48

−1

0

b

Ack

l

s

b

NOTE: All gain coefficients 5.23 numbers.

z

2

1

b

Ack

l

s

b

Σ

28

(Format = 5.23)

48 48

48

28

(Format = 5.23)

Gain Coefficient G1

Reverberation

l

Delay

Reverberation Block

G0

G1

Ack

l

s

b

C Check Word

2

C Bus-Controlled Modes

2

SUBADDRESS(es) PARAMETER(s)

m

0xFC – Ending I

0x00 – Starting I

s

b

S Slave Addr Ack Sub-Addr Ack xxxxxxx Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

0x01 − 0x33

Input Mixer 28-Bit Gain Coefficients

Output Mixer 28-Bit Gain Coefficients

0x84 – 0xA1

m

s

S Slave Addr Ack Sub-Addr Ack xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

1.7.2 I

1−10

b

0x34−0x4B

m

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx s

s

b

m

Effects Block BiQuad Filter Coefficients

S Slave Addr Ack Sub-Addr Ack xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

m

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx s

b

m

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx s

b

m

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

s

b

Reverberation Block Gains

Channel 1 0x4C

Reverberation Block Subaddress

Channel 2 0x4D

Channel 3 0x4E

m

s

b

S Slave Addr Ack Sub-Addr Ack xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

m

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

s

b

0

b

0

48

76

Magnitude

48

28

48

76

Truncation

48

b

1

Truncation

b

1

a

1

28 28

z

−1

z

−1

28

−1

Inline Gain Coeeficient

28

Bass

Σ

Treble

Bass

Σ

Treble

(Format = 5.23)

Bypass Gain Coeeficient

Magnitude

Σ

28

z

48

a

76

48

z

−1

z

28

48

28

2

a

76

28

2

b

48

−1

z

(Format = 5.23)

Shelf Filter

28

(Format = 5.23)

Bypass Gain Coeeficient

Bass and Treble Block

NOTE: All gain coefficients 5.23 numbers

1

2

a

Ack s

0

b

Ack

l

s

b

a

Ack

l

s

b

1

b

Ack s

2

Inline Gain

Ack b

l

s

b

Bypass Gain

Ack

l

s

b

Ack

l

s

b

Subaddress

SUBADDRESS(es) PARAMETER(s)

BLOCK

Channel 1 0x4F−0x5A

Channel 2 0x5B−0x66

MAIN FILTER

Channel 3 0x67−0x72

Cascaded (Twelve/Channel) Main Filter BiQuads

m

s

b

S Slave Addr Ack Sub-Addr Ack xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

m

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx s

b

m

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx s

b

m

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx s

b

m

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx s

b

Channel 1 = 0x73

Bass and Treble Gain Coefficients

s

m

Channel 2 = 0x74

Channel 3 = 0x75

S Slave Addr Ack Sub-Addr Ack xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

s

b

m

1−11

Word1

Ack

l

Ack Word2

l

s

b

m

l

Dynamic Range Control (DRC) Mixer Coefficients

s

b

m

Ack Sub-Addr Ack xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

Slave Addr

S

Ack s

b

xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

s

b

Mix j to o − Inline =

Word 1

Mix l to p − Inline =

Word 1

Word 2 = Mix j to o − Bypass

CH1− 0x7C

Word 1 = Mix n to q − Inline

Word 2 = Mix l to p − Bypass

CH2− 0x7D

o

DRC_bypass_1

j

Loudness

Volume

CH 1 Soft

u

Word 2 = Mix n to q − Bypass

0x7E

CH1−

CH1

Σ

Mix_j_to_o_via_DRC_mult

Mix_j_to_i

Σ

Dynamic

Range Control

i

Σ

CH2

Σ

p

Mix_l_to_p_via_DRC_mult

Mix_l_to_k

l

ΣΣ

Σ

k

Loudness

v

DRC_bypass_2

Dynamic

Range Control

Volume

CH 2 Soft

CH3

q

Mix_n_to_q_via_DRC_mult

Mix_n_to_m

n

Σ Σ

m

Σ

Loudness

w

Σ

DRC_bypass_3

Volume

CH 3 Soft

1−12

m

s

b

S Slave Addr Ack Sub-Addr Ack xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

= Mix j to i

0x76 = Mix u to i

0x79

CH1

= Mix l to k

= Mix v to k 0x77

0x7A

CH2

Mix_u_to_i

CH 1

Block

Bass and Treble

= Mix n to m

= Mix w to m 0x78

0x7B

CH3

Mix_v_to_k

CH 2

Bass and Treble

Block

Mix_w_to_m

CH 3

Bass and Treble

Block

Channel 2 0x80 = Mix Dither 2 to p − 28-Bit Coefficient

Range Control

1

Channel 2 0x80 = Mix Dither 2 to p − 28-Bit Coefficient

Range Control

3

Channel 1

Mix−Delay3_to_o

Processed Audio

Channel 2

Processed Audio

Channel 3

Processed Audio

Dither 1

Dither−Processed Audio Out _ CH

o

Σ

Channel 1

Loudness / Soft Volume

Processed Output

Ack

l

s

b

Dither 2

Mix_Dither2_to_p

Mix_Dither1_to_o

Dynamic

Dither−Processed Audio Out _ CH 2

p

Σ

Channel 2

Loudness / Soft Volume

Processed Output

Dither 3

Mix_Dither3_to_q

Dynamic

Range Control

Dither−Processed Audio Out _ CH

q

Σ

Channel 3

Loudness / Soft Volume

Processed Output

Delay 1

32-Bit Truncate

Node o

Σ

Delay 2

32-Bit Truncate

Mix−Delay3_to_o

Node p

Σ

Ack

l

s

b

Delay 3

32-Bit Truncate

Mix−Delay3_to_p

Node q

Σ

SUBADDRESS(es) PARAMETER(s)

s

b

m

Dither Mix Gain Coefficients

S Slave Addr Ack Sub-Addr Ack xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

Channel 1 0x7F = Mix Dither 1 to o − 28-Bit Coefficient

Channel 3 0x81 = Mix Dither 3 to q − 28-Bit Coefficient

s

b

m

Channel 3 to Channel 1 and Channel 2 Mix Gain Coefficients

S Slave Addr Ack Sub-Addr Ack xxx0000 Ack xxxxxxxx Ack xxxxxxxx Ack xxxxxx

Channel 1 0x82 = Mix Channel 3 Output to o − 28-Bit Coefficient

Channel 2 0x83 = Mix Channel 3 Output to p − 28-Bit Coefficient

1−13

LO MSBs

LO LSBs

Ack

lsb

xxxxxxx

lsb

G

xxxxxxx

0 MSBs

lsb

0 LSBs

Ack

xxxxxxx

Subaddress

CH1 CH2 CH3

Loudness

LG 0xA2 0xA7 0xAC

LO 0xA3 0xA8 0xAD

G 0xA4 0xA9 0xAE

O 0xA5 0xAA 0xAF

Parameter

BiQuad 0xA6 0xAB 0xB0

Soft Volume and Loudness Subaddress

LOUDNESS

CH 1 = 0xA2

CH 2 = 0xA7

VCS

AckAck Ack Ack Ack

LG

lsb

LG Is A 5.23 Format Number

CH 3 = 0xAC

xxx0000 Ack Ack Ack Ack

msb

S Slave Addr Ack Sub-Addr Ack xxxxxxxx xxxxxxxx xxxxxx

LG

( )

BiQuad Coefficients

CH 1 = 0xA3

1

a

lsb

Ack Ack Ack Ack xxx0000

msb

CH 1 = 0xA6

CH 2 = 0xAB

CH 3 = 0xB0

S Slave Addr Ack Sub-Addr Ack xxxxxxxx xxxxxxxx xxxxxx

xxxxxxx

msb

CH 2 = 0xA8

CH 3 = 0xAD

Ack Sub-Addr Ack 00000000 Ack 00000000 Ack Ack xxxxxxxx Ack

Slave Addr S

LO

2

a2b0b1b

lsb

xxxxxxxx xxxxxxxx xxxxxx

xxx0000 Ack Ack Ack Ack

msb

xxxxxxxx

LO Is A 25.23 Format Number

Ack Ack Ack

xxxxxxxx

2

lsb

xxxxxxxx xxxxxxxx xxxxxx

xxx0000 Ack Ack Ack Ack

msb

CH 1 = 0xA4

CH 2 = 0xA9

CH 3 = 0xAE

Σ

28

0

b

xxxxxxxx

G Is A 5.23 Format Number

xxx0000

msb

Slave Addr Ack Sub-Addr Ack Ack Ack Ack Ack

S

G

−1

z

28

1

a

28

1

b

−1

z

CH 1 = 0xA5

CH 2 = 0xAA

−1

z

28

2

a

28

2

b

−1

z

xxxxxxx

xxxxxxxxAck Ack Ack

msb

CH 3 = 0xAF

xxxxxxxx

Ack Sub-Addr Ack 00000000 Ack 00000000 Ack Ack xxxxxxxx Ack

Slave Addr S

O

Σ

All biquad gain coefficients 5.23 numbers.

O Is A 25.23 Format Number

AUDIO OUTAUDIO IN

Loudness Compensation

4848

48

Σ

Commanded 5.23

Volume Command

28

48

1−14

Subaddress

CH1 CH2 CH3

0xF2 0xF3 0xF4

Soft Volume

Volume Command

S Mute/Unmute = 0xF0

S Volume Slew Command = 0xF1

Parameter

Volume Command

0xF1

vcs

xxxxxxx

Ack

S Slave Addr Sub-Addr xxxxxxxx xxxxxxxx xxxxxxxx

= 2048/FS

= 4096/FS

transition

SOFT VOLUME

VCS = 0 ⇒ t

VCS = 1 ⇒ t

C Master Mode

2

I

GPIO1 − Volume Down − CH1 / CH2

GPIO2 − Volume Up − CH3

GPIO3 − Volume Down − CH1 / CH2

GPIO0 − Volume Up − CH1 / CH2

Volume Commands − GPIO Terminals

Commanded

Volume

Original

Volume

C Slave Mode

2

I

transition

t

Mute / Unmute Command

0xF0

321

CCC

HHH

Ack Ack Ack Ack Ack

Slave Addr Ack Sub-Addr xxxxxxxx xxxxxxxx xxxxxxxx xxxxx S

Volume

Command

CH 1 = 0xF2

CH 2 = 0xF3

CH 3 = 0xF4

Mute Command = 1 => 0x0000000 Volume Control

C Bus

2

Volume

I

Commands

lsb

msb

xxxxxxx

xxxxxxxx

xxx0000

Slave Addr Ack Sub-Addr Ack Ack Ack Ack Ack S

(LSB)

MAX

Cut

23

= x16 Boost

= 1/2

= Zero Output For 0x0000000 Volume Control

(5.23 Precision)

Volume Command

Note: Negative Volume Commands Result In Audio Polarity Inversion

O1-MSBits

O1-LSBits

O2-MSBits

O2-LSBits

lsb

xxxxxxx

xxxxxxxx

msb

xxxxxxxx

xxxxxxx

xxxxxxxx

xxxxxxx

msb

CH3 = 0xB9

CH1/CH2 = 0xB4

Ack xxxxxxxx Ack Ack Ack

Ack 00000000 Ack Ack Ack

Ack xxxxxxxx Ack Ack Ack

xxxxxxxx

00000000

Ack Ack 00000000 Ack Ack Ack

Slave Addr Ack Sub-Addr 00000000

S

T1-LSBits

T2-MSBits

xxxxxxx

xxxxxxxx

msb

xxxxxxxx

xxxxxxx

T2-LSBitsxxxxxxxx

lsb

xxxxxxx

T1-MSBits

lsb

Subaddress — Dynamic Range Control (DRC) Block

xxxxxxxx

xxxxxxx

msb

CH3 = 0xB7

lsb

CH3 = 0xB8

CH1/CH2 = 0xB3

msb

K0

xxxxxxx

xxxxxxxx

xxx0000

Ack Ack Ack Ack Ack

Slave Addr Ack Sub-Addr

S

K1

lsb

xxxxxxx

xxxxxxxx

Ack xxxxxxxx Ack Ack AckK2Ack Ack Ack Ack xxx0000

msb

lsb

xxxxxxx

xxxxxxxx

xxx0000

msb

ae

xxxxxxxx

xxxxxxx

CH1/CH2 = 0xB2

Ack xxxxxxxx Ack Ack Ack

Ack 00000000 Ack Ack Ack

Ack xxxxxxxx Ack Ack Ack

CH3 = 0xB6

CH1/CH2 = 0xB1

xxxxxxxx

00000000

Ack Ack 00000000 Ack Ack Ack

lsb

xxxxxxx

xxxxxxxx

CH3 = 0xBA

CH1/CH2 = 0xB5

xxxxxxxx

xxx0000

msb

S

5.23 Format

1−ae

lsb

xxxxxxx

xxxxxxxx

Ack xxxxxxxx Ack Ack Ack

xxxxxxxx

aa

msb

Ack Ack Ack Ack Ack

Slave Addr Ack Sub-Addr

1−aa

lsb

xxxxxxx

xxxxxxxx

Ack xxxxxxxx Ack Ack AckadAck Ack Ack Ack xxx0000

lsb

msb

xxxxxxx

xxxxxxxx

xxx0000

1−ad

lsb

xxxxxxx

xxxxxxxx

Ack Ack Ack Ack xxx0000

msb

5.23 Format

25.23

Format

Compression / Expansion

Coefficient Computation

25.23

Format

Cut

Attack / Decay Control

K2

{

K1

RMS

Voltage

Estimator

32

DRC-Derived

28

O2

{

K0

Gain Coefficient

Volume

O1

Comparator

5.23 Format

a

t

x ln(1−aa)]

x ln(1−ad)]

S

≈ −1/[F

a

d

t

d

t

T2

T1

NOTE: Compression / Expansion / Compression Displayed

= Audio Sample Frequency

S

x ln(1−ae)] Where F

S

≈ −1/[F

RMS

Voltage

Estimator

Applies to DRC Servicing CH1/CH2 Only

Window

ae and (1−ae) Set Time Window Over Which RMS Value is Computed

t

32

Slave Addr Ack Sub-Addr 00000000

S

Slave Addr Ack Sub-Addr 00000000 S

5.23 Format Audio Input

CH1 or CH3

CH2

Audio Input

1−15

BiQuad 1

Estimator

BiQuad 1

Estimator

RMS Voltage

Log

BiQuad 4

r

RMS Voltage

Log

s

co

RMS Voltage

od

C Bus

2

I

Log

RMS Voltage

Spectrum Analyzer / VU Meter

Log

Estimator

RMS Voltage

BiQuad 2

Log

Estimator

RMS Voltage

BiQuad 3

der

Log

Estimator

RMS Voltage

BiQuad 4

Log

Estimator

BiQuad 5

Log

Estimator

RMS Voltage

BiQuad 6

RMS Voltage

Sub-Address Dec

Log

Estimator

RMS Voltage

BiQuad 7

BiQuad 8

BiQuad 9

Log

Estimator

RMS Voltage

BiQuad 10

Estimator

= Audio Sample Frequency

S

x ln(1−asa)] Where F

S

≈ −1/[F

Window

asa and (1−asa) Set Time Window Over Which RMS Value Is

Computed

t

s

1

2

0

1

a

b

2

b

1−asaAck Ack Ack Ackxxxxxxxx xxxxxxx

l

s

xxxxxxxx

Ack Ack Ack Ackxxxxxxxx xxxxxxx xxx0000

s

m

b

s

xxxxxxxx

Ack Ack Ack Ackxxxxxxxx xxxxxxx xxx0000

s

m

b

xxxxxxx

xxxxxxxx

xxx0000 s

b

m

b

s

xxxxxxxx

Ack Ack Ack Ackxxxxxxxx xxxxxxx xxx0000

s

m

b

l

s

xxxxxxxx

Ack Ack Ack Ackxxxxxxxx xxxxxxx xxx0000

s

m

b

Spectrum Analyzer/VU Meter Spectrum Analyzer/VU Meter

Ack Ack Ack Ack Ackxxxxxxxx

S Slave Addr Ack Sub-Addr a

BiQuad 1 to 10 Subaddresses = 0xBC to 0xC5

RMS Window Time Constant Subaddress = 0xBB

l

s

xxxxxxxx

xxx0000 s

m

S Slave Addr Ack Sub-Addr asaAck Ack Ack Ack Ackxxxxxxxx xxxxxxx

b

l

s

b

BiQuad 2

BiQuad 3

Ackxxxxx.xxx

xxxxxxxx

xxx0000 s

b

m

S Slave Addr Ack Sub-Addr BiQuad 1Ack Ackxxxxx.xxx

Spectrum Analyzer Output Subaddress = 0xFD

BiQuad 4

Ackxxxxx.xxx

BiQuad 5

Ackxxxxx.xxx

BiQuad 6

Ackxxxxx.xxx

BiQuad 7

Ackxxxxx.xxx

BiQuad 8

Ackxxxxx.xxx

BiQuad 9

Ackxxxxx.xxx

VU Meter Output 1

BiQuad 10

Ackxxxxx.xxx

(BiQuad 5)

Ack Ackxxxxx.xxx

S Slave Addr Ack Sub-Addr

VU Meter Output = 0xFE

(BiQuad 6)

Ackxxxxx.xxx

1−16

l

s

b

xxxxxxxx

0xC6

xxx0000 s

Dither Block

b

m

Distribution 2 Mix

l

s

b

xxxxxxxx

Ack Ack Ack Ackxxxxxxxx xxxxxxx xxx0000

s

b

m

LFSR1 Mix and LFSR2 Mix Are 5.23 Format Coefficients

LFSR1

L

O

Output

− W 0 +W

0.5

Linear Feedback Shift Register Block

0.25

p

1

t

S

St2St3St4St5S

Sampler

l

s

b

LFSR2

I

C

G

Seed

LFSR1

Condensed

Seed

LFSR2

Condensed

m

l

m

xxxxxx s

b

s

b

s

b

Seed Build Logic

0000000000000000

0xC7

t6

S Slave Addr Ack Sub-Addr Distribution 1 MixAck Ack Ack Ack Ackxxxxxxxx xxxxxxx

Σ

Dither 1

Σ

Dither 2

Σ

Dither 3

S Slave Addr Ack Sub-Addr Dither SeedAck Ack Ack Ack Ackxxxxxx

NOTE: W = 16.0 => 0x000008000000 in 25.23 Format

1−17

Ack

70

0000000x Ack

00000000

15 8

Ack

00000000

23 16

Ack

0xEB

31 24

Timer

1 (Default State)

Disables Watchdog

Microprocessor

Clock

Counter

Watchdog

16

Decode 2

Microprocessor

Control

Ack

210

3

GPIO_in_out

3

0000

74

Ack

GPIO and Watchdog Timer Subaddresses

0xC8−0xC9 Factory Test Subaddresses

0xD0−0xD1 CH1/CH2 to CH3 After Effects Mixers

0xCA−0xCF SDIN4 Input Mixers

SUBADDRESS(es) PARAMETER(s)

0xEF

0xD2−0xEA Reserved

Determines How Many Consecutive Logic 0 Samples

(Where Each Sample Is Spaced by GPIOFSCOUNT LRCLKs)

Are Required to Read a Logic 0 on a GPIO Input Port

Ack

GPIO_samp_int Ack

Microprocessor

Firmware

GPIOFSCOUNT Ack

210

GPIODIR

3

0000 Ack

31 24 23 20 19 16 15 8 7 0

Microprocessor

S Slave Addr Sub-AddrAck 00000000Ack

LD

Down

Counter

Reset

Decode 0

Microprocessor

Bus

EN

READ

C Slave Mode

2

I

DATA PATH SWITCH

Q

D

C Master Mode

2

and

I

Write

Q

Logic

Sample

D

C Master

2

I

Mode Read

Q

D

Q

D

00000000

15 8

Ack

00000000 Ack

31 24 23 16 0

S Slave Addr Sub-AddrAck 00000000Ack

0xEE

1−18

S Slave Addr Sub-AddrAck 00000000Ack

LRCLK

PWRDN

GPIO0

GPIO1

GPIO2

GPIO3

TBLC[7:0]

Slew Rate

Treble and Bass

vsc

0000000000000000

31 24 23 16 15 8 7 0

Ack Ack Ack Ack Ackxxxxxxxx0000000

Bass

Filter Set N

0xF1—Also See Subaddress 0xA2 and Subaddress 0xF5

S Slave Addr Ack Sub-Addr

Treble

Filter Set N

= TBLC[7:0] x 1/LRCLK

Transition

t

0xEC−0xED Reserved/Factory Test Subaddresses

SUBADDRESS(es) PARAMETER(s)

0xF0—See Subaddress 0xA2 Master Mute/Un-Mute

0xEE−0xEF—See Subaddress 0xEB GPIO Port I/O Values and GPIO Parameters

0xF1

= TBLC[7:0] x 1/LRCLK

Transition

t

0xF2−0xF4—See Subaddress 0xA2 CH1−CH3 Volume CMDS

1−19

Subaddress—Bass and Treble Shelf Filter Parameters

Treble/Bass Slew Rate Selection

(LRCLK)

Bass Filter Set Selection

S Slave Addr Ack Sub-Addr Ack Ack Ack00000xxx00000000

0xF5

Bass Shelf Selection (Filter Index)

S Slave Addr Ack Sub-Addr Ack Ack Ackxxxxxxxx00000000

0xF6

BASS FILTER 5

S Slave Addr Ack Sub-Addr Ack Ack Ack0000000000000000

0xF1

CH3

Treble Filter Set Selection

S Slave Addr Ack Sub-Addr Ack Ack Ack00000xxx00000000

0xF7

Treble Shelf Selection (Filter Index)

S Slave Addr Ack Sub-Addr Ack Ack Ackxxxxxxxx00000000

0xF8

BASS FILTER 3

BASS FILTER 1

CH2

MAX BOOST

SHELF

MID-BAND

CH1

Ack00000xxx

CH1CH2CH3

Ackxxxxxxxx Ackxxxxxxxx

TREBLE FILTER 5

Ack00000xxx

CH3

TREBLE FILTER 3

V

Ack0000000 Ackxxxxxxxx

C S

Treble/Bass Slew Rate = TBLC

(Slew Rate = TBLC/FS,

Where FS = Audio Sample Rate)

CH2

Ack00000xxx

CH2

TREBLE FILTER 1

CH1

Ackxxxxxxxx Ackxxxxxxxx

07

CH1

Ack00000xxx

BASS FILTER 4

Treble & Bass Filter Set Commands

0 => No Change 1 − 5 => Filter Sets 1 − 5 6 − 7 => Illegal (Behavior Indeterminate)

BASS FILTER 2

MAX CUT

SHELF

FREQUENCY

TREBLE FILTER 4

Treble & Bass Filter Shelf Commands

0 => Illegal (Behavior Indeterminate) 1 − 150 => Filter Shelves 1 − 150 1 => +18-dB Boost

150 => −18-dB Cut 151 − 255 => Illegal (Behavior Indeterminate)

TREBLE FILTER 2

3-dB CORNERS (kHz)

FS

FILTER SET 5 FILTER SET 4 FILTER SET 3 FILTER SET 2 FILTER SET 1

BASS TREBLE BASS TREBLE BASS TREBLE BASS TREBLE BASS TREBLE

96 kHz 0.25 6 0.5 12 0.75 18 1 24 1.5 36

88.4 kHz 0.23 5.525 0.46 11.05 0.691 16.575 0.921 22.1 1.381 33.15 64 kHz 0.167 4 0.333 8 0.5 12 0.667 16 1 24 48 kHz 0.125 3 0.25 6 0.375 9 0.5 12 0.75 18

44.1 kHz 0.115 2.756 0.23 5.513 0.345 8.269 0.459 11.025 0.689 16.538 32 kHz 0.083 2 0.167 4 0.25 6 0.333 8 0.5 12 24 kHz 0.063 1.5 0.125 3 0.188 4.5 0.25 6 0.375 9

22.05 kHz 0.057 1.378 0.115 2.756 0.172 4.134 0.23 5.513 0.345 8.269 16 kHz 0.042 1 0.083 2 0.125 3 0.167 4 0.25 6 12 kHz 0.031 0.75 0.063 1.5 0.094 2.25 0.125 3 0.188 4.5

11.025 kHz 0.029 0.689 0.057 1.378 0.086 2.067 0.115 2.756 0.172 4.134

1−20

18 Bit

20 Bit

24 Bit

32 Bit

1

32 Bit

16 Bit

Word Size

0101010

IW0/OW0

†

0011001

IW1/OW1

Word Size Code

0000111

AB assigns TDM time slots for those TDM

outputs involving two TAS3103s. For these

output formats, one of the TAS3103 chips

must be defined as AB = 0. The other

C M AND N ASSIGNMENTS

2

IW2/OW2

TAS3103 chip must be defined as AB = 1.

Input and output word sizes are

†

independent.

MCLKI

OSC

XTALO

CRYSTAL

XTALI

0

MUX

MCLKO

PLL0

PLL[1:0]

PLL1

14 13 11 10 8

DWFMT (Data Word Format)

15

÷2

÷4

1

2

3

÷2

÷4

0

1

2

MUX

x11

PLL

0

1

2

3

MUX

OW[2:0]

IW[2:0]

AB

PLL

BYPASS

0xF9

0

7

815

161819212223242627282931

AckIOMAck

DWFMT Ackz[2:0]IMS x[2:0]ICSAck x[2:0]y[2:0]w[1:0]000AckSub-AddrAckSlave AddrS

OM[3:0]IM[3:0]

743 0

÷2

0

1

0

S)

2

S

2

Mode

Discrete, Left Justified

Discrete, Right Justified

Discrete, I

Discrete, 16 − Bit Packed

TDM_LJ_8

TDM_LJ_6

TDM_LJ_4

TDM_I2S_8

TDM_I2S_6

TDM_I2S_4

TDM_20Bit_6

6 Ch, Single Chip, Crystal (LJ)

6 Ch, Single Chip (LJ)

6 Ch, Single Chip, Crystal (I

6 Ch, Single Chip, 20 − Bit

‡

IM0/OM0

IM1/OM1IM2/OM2IM3/OM3

÷16

÷4

÷32

÷8

2

3

4

1

÷2

÷8

÷4

1

2

3

0

5

÷16

4

6

÷32

5

7

MUX

6

1

0

Serial Audio Port (AP) Mode Code

0 0 0 0

0 0 0 1

MUX

SCLKIN

7

MUX

0

MUX

1

MUX

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

Input and output mode selections are independent.

‡

1 1 1 0

1 1 1 1

S FORMAT, CLOCK MANAGEMENT, AND I

2

I

MICROCLK_DIV

I2C_SDA

I2C_SCL

Clock

Processor

Digital Audio

1

Clock

C

2

Microprocessor

I

Sampling

÷4 0

Clock

SCLKOUT2 SCLKOUT1

÷128

÷192

÷256

÷512

0

÷64

1

2

3

4

÷384

5

6

7

MUX

LRCLK

÷32

Ack

02

n[2:0]

m[3:0]

C

2

I

Master

SCL

0xxxxxxx

Ack

00000000 Ack

00000000

MUX

36

N

÷2

1/(M+1)

÷10

C

2

I

Module

0xFB

00000000 Ack

Sub-AddrAckSlave AddrS Ack

See Section 2.1.1 for a detailed discussion of this restriction.

NOTE: F9 must not be updated without first muting all three monaural channels in the TAS3103.

1−21

Delay/Reverb Assignments

0xFA

Delay Reverb

Delay Channel 1 = 2 x {D1[11:0] + 1}

Delay Channel 2 = 2 x {D2[11:0] + 1}

Delay Channel 3 = 2 x {D3[11:0] + 1}

Reserved

m

S Slave Addr Ack Sub-Addr D1 and R1Ack Ack Ack Ack Ackxxxxxxx

xxx0000

s b

m

xxx0000

Ack Ack Ack Ack

s b

m

xxx0000

s b

xxxxxxx

l s b

m

xxx0000

s b

m

xxx0000

s b

m

s b

xxxxxxx

xxx0000

Note: 2 x (D1 + D2 + D3) + 3 x (R1 +R2 +R3) ≤ 4076

l s b

l s

D2 and R2

b l

D3 and R3Ack Ack Ack Ackxxxxxxx

s b

Reverb Channel 1 = 2 x {R1[11:0] + 1}

Reverb Channel 2 = 2 x {R2[11:0] + 1}

Reverb Channel 3 = 2 x {R3[11:0] + 1}

Reserved

NOTE: Changes in reverb and delay assignments can result in unplesasant and extended audio artifacts.

It is recommended that the TAS3103 always be muted before making reverb and delay changes. See section 3.6.3 for a detailed discussion of this restriction.

1−22

TEXAS INSTRUMENTS TAS3103 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual