TEXAS INSTRUMENTS TAS3004 Technical data
查询TAS3004供应商
Data
Manual
2001 Digital Audio Products
SLAS325
IMPORTANT NOTICE
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Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Terminal Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Audio Data Formats 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Serial Interface Formats 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 ADC Digital Output Modes 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 MSB First, Right-Justified Serial Interface
Format—Normal Mode 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 I
2.2.3 MSB Left-Justified Serial Interface Format—Normal Mode 2–4
2.3 ADC Digital Output Mode—Monaural 2–4. . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 MSB First, Right-Justified Serial Interface
2.3.2 I
2.3.3 MSB Left-Justified Serial Interface Format—Monaural
2.3.4 MSB First, Right-Justified Serial Interface
2.3.5 I
2.3.6 MSB Left-Justified Serial Interface Format—Monaural
2.4 Switching Characteristics 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Analog Input/Output 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Analog Input 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Analog Output 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Analog Output 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Analog Output With Gain 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Reference Voltage Filter 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Audio Control/Enhancement Functions 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Soft Volume Update 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Software Soft Mute 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Input Mixer Control 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Mono Mixer Control 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Treble Control 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
S Serial Interface Format—Normal Mode 2–3. . . . . . . . . . . . .
Format—Monaural ADC Mode, B Left Input Selected 2–5. . . .
2
S Serial Interface Format—Monaural ADC Mode,
B Left Input Selected 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Mode, B Left Input Selected 2–7. . . . . . . . . . . . . . . . . . . . .
Format—Monaural ADC Mode, B Right Input Selected 2–8. .
2
S Serial Interface Format—Monaural ADC Mode, B Right
Input Selected 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC Mode, B Right Input Selected 2–10. . . . . . . . . . . . . . . . . . . .
iii
4.6 Bass Control 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 De-Emphasis (DM) 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Analog Control Register Operation 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Dynamic Loudness Contour 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.1 Loudness Biquads 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.2 Loudness Gain 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.3 Loudness Contour Operation 4–5. . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Dynamic Range Compression/Expansion 4–6. . . . . . . . . . . . . . . . . . . . . . .
4.11 AllPass Function 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 Main Control Register 2 (43h) 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Filter Processor 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Biquad Block 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Filter Coefficients 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.2 Biquad Structure 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
6I
C Serial Control Interface 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Introduction 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 I
2
C Protocol 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Operation 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1 Write Cycle Example 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2 TAS3004 I
6.3.3 I
2
C Wait States 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Readback Example 6–3. . . . . . . . . . . . . . . . . . . . .
6.4 SMBus Operation 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1 Block Write Protocol 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2 Write Byte Protocol 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.3 Wait States 6–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.4 TAS3004 SMBus Readback 6–5. . . . . . . . . . . . . . . . . . . . . . . . . .
7 Microcontroller Operation 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 General Description 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Power-Up/Power-Down Reset 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.1 Power-Up Sequence 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.2 Reset 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.3 Reset Circuit 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.4 Fast Load Mode 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2.5 Codec Reset 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Power-Down Mode 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.1 Power-Down Timing Sequence 7–3. . . . . . . . . . . . . . . . . . . . . . .
7.4 Test Mode 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 Internal Interface 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 GPI Terminal Programming 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.1 Switch Interface 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6.2 GPI Architecture 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 External EPROM Memory Maps 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Electrical Characteristics 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Absolute Maximum Ratings Over Operating Temperature Ranges 8–1.
iv
8.2 Recommended Operating Conditions 8–1. . . . . . . . . . . . . . . . . . . . . . . . . .
8.3 Static Digital Specifications 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4 ADC Digital Filter 8–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5 Analog-to-Digital Converter 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6 Input Multiplexer 8–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.7 DAC Interpolation Filter 8–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.8 Digital-to-Analog Converter 8–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.9 DAC Output Performance Data 8–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
8.10 I
C Serial Port Timing Characteristics 8–6. . . . . . . . . . . . . . . . . . . . . . . . . .
9 System Diagrams 9–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Mechanical Information 10–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Software Interface A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1 Main Control Register Map A–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.1 Main Control Register 1 A–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.2 Main Control Register 2 A–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.3 Analog Control Register 2 A–4. . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 Volume Gain Command A–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3 Treble Control Register Command A–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.4 Bass Control Register Command A–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
A.5 I
C Mix Register Command A–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.6 Programming Instruction for the Loudness Contour A–9. . . . . . . . . . . . . .
A.7 Examples of DRCE A–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.7.1 DRCE On/Off A–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.7.2 Above Threshold Ratios A–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.7.3 Below Threshold Ratios A–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.7.4 Threshold A–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.7.5 Time Constants A–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.7.6 DRCE Example With Threshold at –12 dB A–13. . . . . . . . . . . . .
v
List of Illustrations
Figure Title Page
1–1 TAS3004 Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 TAS3004 Terminal Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 MSB First, Right-Justified Serial Interface Format—Normal Mode 2–2. . . . .
2–2I
2–3 MSB Left-Justified Serial Interface Format—Normal Mode 2–4. . . . . . . . . . .
2–4 MSB First, Right-Justified Serial Interface Format—Monaural ADC Mode,
2–5I
2–6 MSB Left-Justified Serial Interface Format—Monaural ADC Mode,
2–7 MSB First, Right-Justified Serial Interface Format—Monaural ADC
2–8I
2–9 MSB Left-Justified Serial Interface Format—Monaural ADC Mode,
2–10 For Right-/Left-Justified, I
3–1 Analog Input to the TAS3004 Device 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 VCOM Decoupling Network 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Analog Output With External Amplifier 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 TAS3004 Reference Voltage Filter 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 TAS3004 Mix Function 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 De-Emphasis Mode Frequency Response 4–3. . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Block Diagram 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 TAS3004 Digital Signal Processing Block Diagram 4–6. . . . . . . . . . . . . . . . . .
5–1 Biquad Cascade Configuration 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Typical I
7–1 TAS3004 Reset Circuit 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 Power-Down Timing Sequence 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–3 Internal Interface Block Diagram 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–1 ADC Digital Filter Characteristics 8–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–2 ADC Digital Filter Stopband Characteristics 8–2. . . . . . . . . . . . . . . . . . . . . . . .
8–3 ADC Digital Filter Passband Characteristics 8–3. . . . . . . . . . . . . . . . . . . . . . . .
8–4 ADC High Pass Filter Characteristics 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8–5 DAC Filter Overall Frequency Characteristics 8–4. . . . . . . . . . . . . . . . . . . . . . .
2
S Serial Interface Format—Normal Mode 2–3. . . . . . . . . . . . . . . . . . . . . . . . .
B Left Input Selected 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
S Serial Interface Format—Monaural ADC Mode,
B Left Input Selected 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B Left Input Selected 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode, B Right Input Selected 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
S Serial Interface Format—Monaural ADC Mode,
B Right Input Selected 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B Right Input Selected 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
S, and Left-/Left-Justified Serial Protocols 2–11. .
2
C Data Transfer Sequence 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
8–6 DAC Digital Filter Passband Ripple Characteristics 8–4. . . . . . . . . . . . . . . . . .
2
8–7I
C Bus Timing 8–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–1 Stereo Application 9–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9–2 TAS3004 Device, 2.1 Channels 9–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–1 TAS3004 DRCE Characteristics in the dB Domain A–10. . . . . . . . . . . . . . . . . .
A–2 DRCE Example With Threshold at –12 dB A–13. . . . . . . . . . . . . . . . . . . . . . . . .
vii
List of Tables
Table Title Page
1–1 TAS3004 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Serial Interface Options 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Analog Control Register Description 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Main Control Register 2 Description 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
6–1I
6–2I
6–3I
7–1 GPI Terminal Programming 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–2 512-Byte EEPROM Memory Map 2.0 Channels 7–6. . . . . . . . . . . . . . . . . . . .
7–3 512-Byte EEPROM Memory Map 2.1 Channels (with TAS3001) 7–7. . . . .
7–4 2048-Byte EEPROM Memory Map—2.0 Speakers With
7–5 2048-Byte EEPROM Memory Map—2.1 Speakers With
A–1I
A–2 Main Control Register 1 Description A–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–3 Main Control Register 2 Description A–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–4 Analog Control Register 2 Description A–4. . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–5 Volume Versus Gain Values A–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–6 Treble Control Register A–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–7 Bass Control Register A–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–8 Mixer1 and Mixer2 Gain Values A–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–9 Example of a DRCE I
A–10 Example of a DRCE I
A–11 Above Threshold Ratios for Compression A–10. . . . . . . . . . . . . . . . . . . . . . . . .
A–12 Above Threshold Ratios for Expansion A–11. . . . . . . . . . . . . . . . . . . . . . . . . . .
A–13 Below Threshold Ratios for Expansion A–11. . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–14 Below Threshold Ratios for Compression A–11. . . . . . . . . . . . . . . . . . . . . . . . .
A–15 Threshold Values A–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–16 Time Constants A–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C Protocol Definitions 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Address Byte Table 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Wait States 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple Equalizations 7–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple Equalizations 7–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Register Map A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
C Instruction With DRCE On A–9. . . . . . . . . . . . . . . .
2
C Instruction With DRCE Off A–9. . . . . . . . . . . . . . . .
viii
1 Introduction
1.1 Description
The TAS3004 device is a system-on-a-chip that replaces conventional analog equalization to perform digital
parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides
high-quality, soft digital volume, bass, and treble control. All control parameters are uploaded through the I
from an outside MCU through the I
The TAS3004 device also has an integrated 24-bit stereo codec with two I
2
C slave port or from an external EPROM through the I2C master port.
2
C-selectable, single-ended inputs per
channel.
The digital parametric equalization consists of seven cascaded, independent biquad filters per channel. Each biquad
filter has five 24-bit coefficients that can be configured into many different filter functions (such as bandpass, high
pass, and low pass).
The internal loudness contour algorithm can be controlled and programmed with an I
Dynamic range compression/expansion (DRCE) is programmable through the I
2
2
C command.
C port. The system designer can set
the threshold, energy estimation time constant, compression ratio, and attack and decay time constants.
The TAS3004 device supports 13 serial interface formats (I
16, 18, 20, or 24 bits. The sampling frequency (f
) may be set to 32 kHz, 44.1 kHz, or 48 kHz.
S
2
S, left justified, right justified) with data word lengths of
The TAS3004 device uses a system clock generated by the internal phase-locked loop (PLL). The reference clock
for the PLL is provided by an external master clock (MCLK) of 256f
or 512fS, or a 256fS crystal.
S
The TAS3004 device has six internally configurable general-purpose input (GPI) terminals that control volume, bass,
treble, and equalization. Each GPI terminal has a debounce algorithm that is programmed into the TAS3004 internal
microcontroller.
2
C port
1.2 Features
• Programmable seven-band parametric equalization
• Programmable digital volume control
• Programmable digital bass and treble control
• Programmable dynamic range compression/expansion (DRCE)
• Programmable loudness contour/dynamic bass control
• Configurable serial port for audio data
• Two input data channels that can be mixed with digital data from the analog-to-digital converter (ADC) of
the codec (analog input). These channels are controlled by I
• Three output data channels: Left and right data go through equalization; bass, treble, DRCE, and volume
to SDOUT1; SDOUT2 mixes left and right data. SDOUT2 operates as a center channel or subwoofer
channel. The output of the ADC is available for additional processing.
• Capability to configure ADC output to one of two monaural data streams or one stereo data stream
• Capability to di g i t a l l y m i x l e f t and right input channels for a monaural output to facilitate subwoofer operation
• Serial I
2
C master/slave port that allows:
– Downloading of control data to the device externally from the EPROM or an I
2
C commands.
2
C master
1–1
– Controlling other I2C devices
2
• Two I
C-selectable, single-ended analog input stereo channels
• Equalization bypass mode
• Single 3.3-V power supply
• Powerdown without reloading the coefficients
• Sampling rates: 32 kHz, 44.1 kHz, or 48 kHz
• Master clock frequency, 256f
or 512f
S
S
• Can have crystal input to replace MCLK. Crystal input frequency is 256fS.
• Six GPI terminals for volume, bass, treble up/down control, mute, and selection of equalization filters
1–2
1.3 Functional Block Diagram
AINRP
AINRM
RINA
RINB
AINLP
AINLM
LINA
LINB
ALLPASS
INPA
GPI5
GPI4
GPI3
GPI2
GPI1
GPI0
Controller
L+R
SS(REF)
REFM
REFP
V
V
AV
Voltage
Reference
AINRP
AINRM
24-Bit
Stereo
ADC
AINLP
AINLM
RFILT
V
Stereo DAC
DD
AV
Analog
Supplies
24-Bit
SS
AV
Analog
Control
Register
Output
Format
Control
Logic
DD
DV
Digital
Supplies
SS
DV
SDOUT0
VCOM
AOUTL
AOUTR
L+R
SDOUT2
CS1
SDA
SCL
PWR_DN
RESET
TEST
C
2
I
Control
Control
32-Bit Audio Signal
L
R
SDIN2
SDIN1
SDATA
Control
SCLK/O
LRCLK/O
32-Bit Audio Signal
IFM/S
CLKSEL
Figure 1–1. TAS3004 Block Diagram
Processor
Processor
OSC/CLK
Select
MCLK
XTALI/
XTALO
MCLKO
SDOUT1
PLL
CAP_PLL
1–3
1.4 Terminal Assignments
LINB
AINLP
REFMVREFP
AINLM
V
PACKAGE
(TOP VIEW)
AINRM
AINRP
RINA
RINB
VCOM
AOUTL
AOUTR
V
RFILT
AV
SS(REF)
AV
RESET
PWR_DN
TEST
CAP_PLL
CLKSEL
MCLKO
1.5 Terminal Functions
LINA
SS
INPA
CS1
47 46 45 44 4348 42
1
2
3
4
5
6
7
8
9
10
11
12
14 15
13
XTALO
17 18 19 20
16
SCL
SDA
DD
DV
SS
DV
LRCLK/O
40 39 3841
22 23 24
21
IFM/S
SCLK/O
37
SDIN1
SDIN2
XTALI/MCLK
Figure 1–2. TAS3004 Terminal Assignments
NC
36
AV
35
NC
34
33
GPI5
32
GPI4
GPI3
31
GPI2
30
GPI1
29
GPI0
28
ALLPASS
27
SDOUT1
26
SDOUT0
25
SDOUT2
DD
Table 1–1. TAS3004 Terminal Functions
TERMINAL
NAME NO.
AINLM 46 I ADC left channel analog input (anti-alias capacitor)
AINLP 47 I ADC left channel analog input (anti-alias capacitor)
AINRM 43 I ADC right channel analog input (anti-alias capacitor)
AINRP 42 I ADC right channel analog input (anti-alias capacitor)
ALLPASS 27 I Logic high bypasses equalization filters
AOUTL 39 O Left channel analog output
AOUTR 37 O Right channel analog output
AV
DD
AV
SS
AV
SS(REF)
CAP_PLL 10 I Loop filter for internal phase-locked loop (PLL)
CLKSEL 11 I Logic low selects 256fS; logic high selects 512fS MCLK
CS1 7 I I2C address bit A0; low = 68h, high = 6Ah
1–4
I/O
35 I Analog power supply (3.3 V)
4 I Analog voltage ground
3 I Analog ground voltage reference
DESCRIPTION
Table 1–1. TAS3004 Terminal Functions (Continued)
TERMINAL
NAME NO.
DV
DD
DV
SS
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
IFM/S 21 I Digital audio I/O control (low = input; high = output)
INPA 5 O Low when analog input A is selected (will sink 4 mA)
LINA 1 I Left channel analog input 1
LINB 48 I Left channel analog input 2
LRCLK/O 19 I/O Left/right clock input/output (output when IFM/S is high)
MCLKO 12 O MCLK output for slave devices
NC 34 No connection; Can be used as a printed circuit board routing channel
NC 36 No connection; Can be used as a printed circuit board routing channel
PWR_DN 8 I Logic high places the TAS3004 device in power-down mode
RESET 6 I Logic low resets the TAS3004 device to the initial state
RINA 40 I Right channel analog input 1
RINB 41 I Right channel analog input 2
SCL 15 I/O I2C clock connection
SCLK/O 20 I/O Shift (bit) clock input (output when IFM/S is high)
SDA 16 I/O I2C data connection
SDIN1 22 I Serial data input 1
SDIN2 23 I Serial data input 2
SDOUT1 26 O Serial data output (from internal audio processing)
SDOUT2 24 O Serial data output (a monaural mix of left and right, before processing)
SDOUT0 25 O Serial data output from ADC
TEST 9 I Reserved manufacturing test terminal; connect to DV
VCOM 38 O Digital-to-analog converter mid-rail supply (decouple with parallel combination of 10-µF and 0.1-µF
V
REFM
V
REFP
V
RFILT
XTALI/MCLK 13 I Crystal or external MCLK input
XTALO 14 I Crystal input (crystal is connected between terminals 13 and 14)
I/O
17 I Digital power supply (3.3 V)
18 I Digital ground
28
29
30
31
32
33
45 I ADC minus voltage reference
44 I ADC plus voltage reference
I Switch input terminals
capacitors)
2 O Voltage reference low pass filter
DESCRIPTION
SS
1–5
1–6
2 Audio Data Formats
2.1 Serial Interface Formats
The TAS3004 device works in master or slave mode.
In the master mode, terminal 21 (IFM/S
) is tied high. This activates the master clock (MCLK) circuitry. A crystal can
be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be
connected to X TALI/MCLK. In that case, MCLK outputs from terminal 12 (MCLKO) with terminals 19 (LRCLK/O) and
20 (SCLK/O) becoming outputs to drive slave devices.
In the slave mode, IFM/S
is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device
requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options
for selecting the clock rates. If the 512f
of 512f
must be supplied. If the 256fS MCLK is selected, CLKSEL is tied low and an MCLK of 256fS must be supplied.
S
MCLK rate is selected, terminal 1 1 (CLKSEL) is tied high and an MCLK rate
S
In both cases, an LRCLK of 64SCLK must be supplied.
• MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.
• If the LRCLK phase changes more than 10MCLK, the codec automatically resets.
2
The TAS3004 device is compatible with 13 different serial interfaces. Available interface options are I
and left justified. Table 2–1 indicates how the 13 options are selected using the I
(MCR, I
Additionally, the 16-bit mode operates at 32f
2
C address x01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64fS.
.
S
2
C bus and the main control register
S, right justified,
Table 2–1. Serial Interface Options
MODE MCR BIT (6) MCR BIT (5–4) MCR BIT (1–0)
0 0 00 00 16-bit, left justified, 32f
1 1 00 00 16-bit, left justified, 64f
2 1 01 00 16-bit, right justified, 64f
3 1 10 00 16-bit, I2S, 64f
4 1 00 01 18-bit, left justified, 64f
5 1 01 01 18-bit, right justified, 64f
6 1 10 01 18-bit, I2S, 64f
7 1 00 10 20-bit, left justified, 64f
8 1 01 10 20-bit, right justified, 64f
9 1 10 10 20-bit, I2S, 64f
10 1 00 11 24-bit, left justified, 64f
11 1 01 11 24-bit, right justified, 64f
12 1 10 11 24-bit, I2S, 64f
SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0
S
S
S
S
SERIAL INTERFACE
S
S
S
S
S
S
S
S
S
Figure 2–1 through Figure 2–9 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the
different interface protocols.
2–1
2.2 ADC Digital Output Modes
ADC digital output mode (SDOUT0) has two operational modes, normal and monaural. In the normal mode, the
output of the ADC conforms to the output modes described in Sections 2.2.1 through 2.2.3. To enter the normal output
mode, bit 7 (ADM) in the analog control register must be cleared to 0. In the monaural output mode, the digital output
of the ADC conforms to the output modes described in Sections 2.3.1 through 2.3.6. To enter the monaural mode,
bit 7 (ADM) in the analog control register must be set to 1.
2.2.1 MSB First, Right-Justified Serial Interface Format—Normal Mode
The normal output mode for the MSB first, right-justified serial interface format is for 16, 18, 20, and 24 bits with bit 7
(ADM) in the analog control register cleared to 0. Figure 2–1 shows the following characteristics of this protocol:
• Left channel is transmitted when LRCLK is high.
• The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.
• The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the
next rising edge of SCLK.
• If LRCLK phase changes by more than 10MCLK, the codec automatically resets.
SCLK
LRCLK = f
S
SDIN
SDOUT
Figure 2–1. MSB First, Right-Justified Serial Interface Format—Normal Mode
……
MSB LSB
MSB LSB
………… ……
…… ……
Left Channel Right Channel
MSB LSB
MSB LSB
……
……
2–2
2.2.2 I2S Serial Interface Format—Normal Mode
The normal output mode for the I2S serial interface format is for 16, 18, 20, and 24 bits with bit 7 (ADM) in the analog
control register cleared to 0.
Figure 2–2 shows the following characteristics of this protocol:
• Left channel is transmitted when LRCLK is low.
• SDIN is sampled with the rising edge of SCLK.
• SDOUT is transmitted on the falling edge of SCLK.
• If LRCLK phase changes by more than 10MCLK, the codec automatically resets.
SCLK
LRCLK = f
SDIN
SDOUT
S
X LSB
MSB
X LSB
MSB
Figure 2–2. I2S Serial Interface Format—Normal Mode
……
……
Left Channel Right Channel
…
…
X LSB
MSB
X LSB
MSB
……
……
…
…
2–3
2.2.3 MSB Left-Justified Serial Interface Format—Normal Mode
The normal output mode for the MSB left-justified serial interface format is for 16, 18, 20, and 24 bits with bit 7 (ADM)
in the analog control register cleared to 0.
Figure 2–3 shows the following characteristics of this protocol:
• Left channel is transmitted when LRCLK is high.
• The SDIN data is justified to the leading edge of the LRCLK.
• The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.
SCLK
LRCLK = f
SDIN
SDOUT
S
MSB LSB
MSB LSB
Figure 2–3. MSB Left-Justified Serial Interface Format—Normal Mode
……
……
Left Channel Right Channel
……
……
MSB LSB
MSB LSB
……
……
……
……
2.3 ADC Digital Output Mode—Monaural
For the monaural ADC digital output mode, bit 7 (ADM) is set to 1, and bit 6 (LRB) and bit 1 (INP) in the analog control
register (see Section 4.8, Analog Control Register Operation) control the operation of the monaural output mode. All
interface formats are for 16, 18, 20, and 24 bits.
2–4
2.3.1 MSB First, Right-Justified Serial Interface Format—Monaural ADC Mode, B Left Input
Selected
The monaural output mode for the MSB first, right-justified serial interface format is for 16, 18, 20, and 24 bits with
the following bits in the analog control register set as shown:
• Bit 7 (ADM) is set to 1.
• Bit 6 (LRB) is cleared to 0.
• Bit 1 (INP) is set to 1.
Figure 2–4 shows the following characteristics of this protocol:
• Left channel is transmitted when LRCLK is either high or low.
• The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.
• The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the
next rising edge of SCLK.
• If LRCLK phase changes by more than 10MCLK, the codec automatically resets.
SCLK
LRCLK = f
Figure 2–4. MSB First, Right-Justified Serial Interface Format—Monaural ADC Mode, B Left Input
SDIN
SDOUT0
S
……
MSB LSB
MSB LSB
………… ……
…… ……
Left Channel Left Channel
Selected
MSB LSB
MSB LSB
……
……
2–5
2.3.2 I2S Serial Interface Format—Monaural ADC Mode, B Left Input Selected
The monaural output mode for the I2S serial interface format is for 16, 18, 20, and 24 bits with the following bits in
the analog control register set as shown:
• Bit 7 (ADM) is set to 1.
• Bit 6 (LRB) is cleared to 0.
• Bit 1 (INP) is set to 1.
Figure 2–5 shows the following characteristics of this protocol:
• Left channel is transmitted when LRCLK is either high or low.
• SDIN is sampled with the rising edge of SCLK.
• SDOUT is transmitted on the falling edge of SCLK.
• If LRCLK phase changes by more than 10MCLK, the codec automatically resets.
SCLK
LRCLK = f
S
X LSB
SDIN
SDOUT0
Figure 2–5. I2S Serial Interface Format—Monaural ADC Mode, B Left Input Selected
MSB
MSB
X LSB
……
……
Left Channel Left Channel
…
…
X LSB
MSB
X LSB
MSB
……
……
…
…
2–6
2.3.3 MSB Left-Justified Serial Interface Format—Monaural ADC Mode, B Left Input Selected
The monaural output mode for the MSB left-justified serial interface format is for 16, 18, 20, and 24 bits with the
following bits in the analog control register set as shown:
• Bit 7 (ADM) is set to 1.
• Bit 6 (LRB) is cleared to 0.
• Bit 1 (INP) is set to 1.
Figure 2–6 shows the following characteristics of this protocol:
• Left channel is transmitted when LRCLK is either high or low.
• The SDIN data is justified to the leading edge of the LRCLK.
• The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.
SCLK
LRCLK = f
Figure 2–6. MSB Left-Justified Serial Interface Format—Monaural ADC Mode, B Left Input Selected
SDIN
SDOUT0
S
MSB LSB
MSB LSB
……
……
Left Channel Left Channel
……
……
MSB LSB
MSB LSB
……
……
……
……
2–7
2.3.4 MSB First, Right-Justified Serial Interface Format—Monaural ADC Mode, B Right Input
Selected
The monaural output mode for the MSB first, right-justified serial interface format is for 16, 18, 20, and 24 bits with
the following bits in the analog control register set as shown:
• Bit 7 (ADM) is set to 1.
• Bit 6 (LRB) is set to 1.
• Bit 1 (INP) is set to 1.
Figure 2–7 shows the following characteristics of this protocol:
• Right channel is transmitted when LRCLK is either high or low.
• The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.
• The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the
next rising edge of SCLK.
• If LRCLK phase changes by more than 10MCLK, the codec automatically resets.
SCLK
LRCLK = f
Figure 2–7. MSB First, Right-Justified Serial Interface Format—Monaural ADC Mode, B Right Input
SDIN
SDOUT0
S
……
MSB LSB
MSB LSB
………… ……
…… ……
Right Channel
Selected
MSB LSB
MSB LSB
Right Channel
……
……
2–8
2.3.5 I2S Serial Interface Format—Monaural ADC Mode, B Right Input Selected
The monaural output mode for the I2S serial interface format is for 16, 18, 20, and 24 bits with the following bits in
the analog control register set as shown:
• Bit 7 (ADM) is set to 1.
• Bit 6 (LRB) is set to 1.
• Bit 1 (INP) is set to 1.
Figure 2–8 shows the following characteristics of this protocol:
• Right channel is transmitted when LRCLK is either high or low.
• SDIN is sampled with the rising edge of SCLK.
• SDOUT is transmitted on the falling edge of SCLK.
• If LRCLK phase changes by more than 10MCLK, the codec automatically resets.
SCLK
LRCLK = f
Figure 2–8. I2S Serial Interface Format—Monaural ADC Mode, B Right Input Selected
SDIN
SDOUT0
S
X LSB
MSB
X LSB
MSB
……
……
X LSB
…
…
Right Channel Right Channel
MSB
X LSB
MSB
……
……
…
…
2–9
2.3.6 MSB Left-Justified Serial Interface Format—Monaural ADC Mode, B Right Input Selected
The monaural output mode for the MSB left-justified serial interface format is for 16, 18, 20, and 24 bits with the
following bits in the analog control register set as shown:
• Bit 7 (ADM) is set to 1.
• Bit 6 (LRB) is set to 1.
• Bit 1 (INP) is set to 1.
Figure 2–9 shows the following characteristics of this protocol:
• Right channel is transmitted when LRCLK is either high or low.
• The SDIN data is justified to the leading edge of the LRCLK.
• The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.
SCLK
LRCLK = f
Figure 2–9. MSB Left-Justified Serial Interface Format—Monaural ADC Mode, B Right Input Selected
SDIN
SDOUT0
S
MSB LSB
MSB LSB
……
……
Right Channel Right Channel
……
……
MSB LSB
MSB LSB
……
……
……
……
2–10
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