Texas Instruments TAS3002 User Manual

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2001 Digital Audio: Digital Speakers

SLAS307B

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Copyright  2001, Texas Instruments Incorporated

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stated by TI for

1 Introduction

1.1 Description

The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital
parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides
high-quality, soft digital volume, bass, and treble control. All control parameters are uploaded from an outside MCU
through the I

The TAS3002 device also has an integrated 24-bit stereo codec with two I
channel.

The digital parametric equalization consists of seven cascaded, independent biquad filters per channel. Each biquad
filter has five 24-bit coefficients that can be configured into many different filter functions (such as band-pass,
high-pass, and low-pass).

The internal loudness contour algorithm can be controlled and programmed with an I
Dynamic range compression/expansion (DRCE) is programmable through the I

the threshold, energy estimation time constant, compression ratio, and attack and decay time constants.
The TAS3002 device supports 13 serial interface formats (I

16, 18, 20, or 24 bits. The sampling frequency (f
formats are listed and described in Section 2.1.

The TAS3002 device uses a system clock generated by the internal phase-locked loop (PLL). The reference clock
for the PLL is provided by an external master clock (MCLK) of 256f

The TAS3002 device has six internally configurable general-purpose input (GPI) terminals that control volume, bass,
treble, and equalization. Each GPI terminal has a debounce algorithm that is programmed into the TAS3002 internal
microcontroller.

2

C slave port or from an external EEPROM through the I2C master port.

2

C-selectable, single-ended inputs per

2

C port. The system designer can set

2

S, left justified, right justified) with data word lengths of

) may be set to 32 kHz, 44.1 kHz, or 48 kHz. The 13 serial interface

S

or 512fS, or a 256fS crystal.

S

2

C command.

1.2 Features

• Programmable seven-band parametric equalization

• Programmable digital volume control

• Programmable digital bass and treble control

• Programmable dynamic range compression/expansion (DRCE)

• Programmable loudness contour/dynamic bass control

• Configurable serial port for audio data

• Two input data channels that can be mixed with digital data from the analog-to-digital converter (ADC) of

the codec (analog input). These channels are controlled by I

• Three output data channels: Left and right data go through equalization; bass, treble, DRCE, and volume
to SDOUT1; SDOUT2 mixes left and right data. SDOUT2 operates as a center channel or subwoofer
channel. The output of the ADC is available for additional processing.

• Capability to di g i t a l l y m i x l e f t a n d r i g h t i n p u t c h a n n els for a monaural output to facilitate subwoofer operation

• Serial I

2

C master/slave port that allows:

− Downloading of control data to the device externally from the EEPROM or an I

− Controlling other I

2

C devices

2

C commands.

2

C master

1−1

• Two I2C-selectable, single-ended analog input stereo channels

• Equalization bypass mode

• Single 3.3-V power supply

• Power down without reloading the coefficients

• Sampling rates of 32 kHz, 44.1 kHz, or 48 kHz

• Master clock frequency of 256f

or 512f

S

S

• Can have crystal input to replace MCLK. Crystal input frequency is 256fS.

• Six GPI terminals for volume, bass, treble up/down control, mute, and selection of equalization filters

1.3 Functional Block Diagram

Figure 1−1 is a block diagram showing the major functions of the TAS3002.

1−2

AINRP

AINRM

RINA
RINB

SS(REF)

REFM

REFP

AV

V

V

Voltage

Reference

AINRP

AINRM

RFILT

V

Analog

Supplies

SS

AVDDAV

Supplies

SS

DVDDDV

Digital

AINLP

AINLM

LINA
LINB

ALLPASS

INPA

GPI5
GPI4
GPI3
GPI2
GPI1
GPI0

CS1

SDA

SCL

Controller

C

2

I

Control

L+R

24-Bit

Stereo

ADC

AINLP

AINLM

32-Bit Audio Signal

SDOUT0

VCOM
AOUTL
AOUTR

24-Bit

Stereo DAC

L+R
SDOUT2

Processor

SDOUT1

PWR_DN

RESET

TEST

Control

L

R

SDIN2

SDIN1

SDATA

Control

SCLK/O

LRCLK/O

32-Bit Audio Signal

Processor

OSC/CLK

IFM/S

CLKSEL

Figure 1−1. TAS3002 Block Diagram

Select

MCLK

XTALI/

XTALO

MCLKO

PLL

CAP_PLL

1−3

1.4 Terminal Assignments

I/O

DESCRIPTION

Figure 1−2 shows the terminal locations on the package outline, along with the signal name assigned to each
terminal.

PACKAGE

(TOP VIEW)

REFMVREFP

AINRM

LINB

AINLPVAINLM

AINRP

RINB

RINA

VCOM

AOUTL

AOUTR

V

AV

SS(REF)

RESET

PWR_DN

TEST

CAP_PLL

CLKSEL

MCLKO

1.5 Terminal Functions

LINA

RFILT

AV

SS

INPA

CS1

47 46 45 44 4348 42

1
2
3
4
5
6
7
8
9
10
11
12

14 15

13

XTALO

17 18 19 20

16

SCL

SDA

DD

DV

SS

DV

LRCLK/O

40 39 3841

22 23 24

21

IFM/S

SCLK/O

37

SDIN1

SDIN2

XTALI/MCLK

Figure 1−2. TAS3002 Terminal Assignments

NC

36

AV

35

NC

34
33

GPI5

32

GPI4
GPI3

31

GPI2

30

GPI1

29

GPI0

28

ALLPASS

27

SDOUT1

26

SDOUT0

25

SDOUT2

DD

Table 1−1 lists the terminals in alphanumeric order by signal name, along with the terminal number, terminal type,
and a description of the terminal function.

Table 1−1. TAS3002 Terminal Functions

TERMINAL

NAME NO.

AINLM 46 I ADC left channel analog input (antialias capacitor)
AINLP 47 I ADC left channel analog input (antialias capacitor)
AINRM 43 I ADC right channel analog input (antialias capacitor)
AINRP 42 I ADC right channel analog input (antialias capacitor)
ALLPASS 27 I Logic high bypasses equalization filters
AOUTL 39 O Left channel analog output
AOUTR 37 O Right channel analog output

1−4

AV

DD

AV

SS

AV

SS(REF)

35 I Analog power supply (3.3 V)

4 I Analog voltage ground
3 I Analog ground voltage reference

Table 1−1. TAS3002 Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

CAP_PLL 10 I Loop filter for internal phase-locked loop (PLL)
CLKSEL 11 I Logic low selects 256fS; logic high selects 512fS MCLK
CS1 7 I I2C address bit A0; low = 68h, high = 6Ah

DV

DD

DV

SS

GPI0
GPI1
GPI2
GPI3
GPI4
GPI5

IFM/S 21 I Digital audio I/O control (low = input; high = output)
INPA 5 O Low when analog input A is selected (will sink 4 mA)
LINA 1 I Left channel analog input 1
LINB 48 I Left channel analog input 2
LRCLK/O 19 I/O Left/right clock input/output (output when IFM/S is high)
MCLKO 12 O MCLK output for slave devices
NC 34 No connection; Can be used as a printed circuit board routing channel
NC 36 No connection; Can be used as a printed circuit board routing channel
PWR_DN 8 I Logic high places the TAS3002 device in power-down mode
RESET 6 I Logic low resets the TAS3002 device to the initial state
RINA 40 I Right channel analog input 1
RINB 41 I Right channel analog input 2
SCL 15 I/O I2C clock connection
SCLK/O 20 I/O Shift (bit) clock input (output when IFM/S is high)
SDA 16 I/O I2C data connection
SDIN1 22 I Serial data input 1
SDIN2 23 I Serial data input 2
SDOUT0 25 O Serial data output from ADC
SDOUT1 26 O Serial data output (from internal audio processing)
SDOUT2 24 O Serial data output (a monaural mix of left and right, before processing)
TEST 9 I Reserved manufacturing test terminal; connect to DV
VCOM 38 O Digital-to-analog converter mid-rail supply (decouple with parallel combination of 10-µF and 0.1-µF

V

REFM

V

REFP

V

RFILT

XTALI/MCLK 13 I Crystal or external MCLK input
XTALO 14 I Crystal input (crystal is connected between terminals 13 and 14)

17 I Digital power supply (3.3 V)
18 I Digital ground
28

29
30
31
32
33

45 I ADC minus voltage reference
44 I ADC plus voltage reference

2 O Voltage reference low pass filter

I Switch input terminals

capacitors)

SS

1−5

1−6

2 Audio Data Formats

2.1 Serial Interface Formats

The TAS3002 device works in master or slave mode.
In the master mode, terminal 21 (IFM/S

) is tied high. This activates the master clock (MCLK) circuitry. A crystal can
be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be
connected to X TALI/MCLK. In that case, MCLK is outputs on terminal 12 (MCLKO), with terminals 19 (LRCLK/O) and
20 (SCLK/O) becoming outputs to drive slave devices.

In the slave mode, IFM/S

is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device
requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options
for selecting the clock rates. If the 512f
of 512f

must be supplied. If the 256fS MCLK is selected, CLKSEL is tied low and an MCLK of 256fS must be supplied.

S

MCLK rate is selected, terminal 1 1 (CLKSEL) is tied high and an MCLK rate

S

In both cases, an LRCLK of 64SCLK must be supplied.

• MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.

• If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

2

The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I
and left justified. Table 2−1 indicates how the 13 options are selected using the I
(MCR, I
Additionally, the 16-bit mode operates at 32f

2

C address 01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64 fS.

.

S

2

C bus and the main control register

S, right justified,

Table 2−1. Serial Interface Options

MODE MCR BIT (6) MCR BIT (5−4) MCR BIT (1−0)

0 0 00 00 16-bit, 32f
1 1 00 00 16-bit, left justified, 64f
2 1 01 00 16-bit, right justified, 64f
3 1 10 00 16-bit, I2S, 64f
4 1 00 01 18-bit, left justified, 64f
5 1 01 01 18-bit, right justified, 64f
6 1 10 01 18-bit, I2S, 64f
7 1 00 10 20-bit, left justified, 64f
8 1 01 10 20-bit, right justified, 64f

9 1 10 10 20-bit, I2S, 64f
10 1 00 11 24-bit, left justified, 64f
11 1 01 11 24-bit, right justified, 64f
12 1 10 11 24-bit, I2S, 64f

SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0

S

S

S

S

S

SERIAL INTERFACE

S

S

S

S

S

S

S

S

Figure 2−1 through Figure 2−3 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the
different interface protocols.

2−1

2.2 Digital Output Modes

The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3.

2.2.1 MSB-First, Right-Justified, Serial-Interface Format

The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−1
shows the following characteristics of this protocol:

• Left channel is transmitted when LRCLK is high.

• The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.

• The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the

next rising edge of SCLK.

• If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

SCLK

LRCLK = f

SDIN

SDOUT

S

MSB LSB

……

Figure 2−1. MSB-First, Right-Justified, Serial-Interface Format

MSB LSB

………… ……

…… ……

Left Channel Right Channel

MSB LSB

MSB LSB

……

……

2−2

2.2.2 I2S Serial-Interface Format

The normal output mode for the I2S serial-interface format is for 16, 18, 20, or 24 bits.
Figure 2−2 shows the following characteristics of this protocol:

• Left channel is transmitted when LRCLK is low.

• SDIN is sampled with the rising edge of SCLK.

• SDOUT is transmitted on the falling edge of SCLK.

• If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.

SCLK

LRCLK = f

SDIN

SDOUT

S

X LSB

MSB

X LSB

MSB

……

……

Left Channel Right Channel

Figure 2−2. I2S Serial-Interface Format

…

…

X LSB

MSB

X LSB

MSB

……

……

…

…

2−3

2.2.3 MSB-Left-Justified, Serial-Interface Format

The normal output mode for the MSB-left-justified, serial-interface format is for 16, 18, 20, or 24 bits.
Figure 2−3 shows the following characteristics of this protocol:

• Left channel is transmitted when LRCLK is high.

• The SDIN data is justified to the leading edge of the LRCLK.

• The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.

SCLK

LRCLK = f

SDIN

SDOUT

S

MSB LSB

MSB LSB

……

……

Left Channel Right Channel

Figure 2−3. MSB-Left-Justified, Serial-Interface Format

……

……

MSB LSB

MSB LSB

……

……

……

……

2−4

2.3 Switching Characteristics

PARAMETER MIN TYP MAX UNIT

t

c(SCLK)

t

d(SLR)

t

d(SDOUT)

t

su(SDIN)

t

h(SDIN)

f

(LRCLK)

NOTE 1: Maximum of 50-pF external load on SDOUT.

SCLK cycle time 325.5 ns
SCLK rising to LRCLK edge 20 ns
SDOUT valid from SCLK falling edge (see Note 1) (1/256fS) + 10 ns
SDIN setup before SCLK rising edge 20 ns
SDIN hold after SCLK rising edge 100 ns
LRCLK frequency 32 44.1 48 kHz
Duty cycle 50 %

t

c(SCLK)

SCLK

LRCLK

t

d(SLR)

t

f(SCLK)

t

r(SCLK)

SDOUT1
SDOUT2
SDOUT0

SDIN1
SDIN2

t

h(SDIN)

t

d(SLR)

t

su(SDIN)

t

d(SDOUT)

Figure 2−4. For Right-/Left-Justified and I2S Serial Protocols

2−5

2−6

3 Analog Input/Output

The TAS3002 device contains a stereo 24-bit ADC with two single-ended inputs per channel. Selection of the A or
B analog input is accomplished by setting a bit in the analog control register (ACR) by an I

2

C command. Additionally,

the TAS3002 device has a stereo 24-bit digital-to-analog converter (DAC).

3.1 Analog Input

Figure 3−1 shows the technique and components required for analog input to the TAS3002 device. The maximum
input signal must not exceed 0.7 V
20 Hz to 20 kHz at a sampling frequency of 48 kHz without alias frequency problems.

0.47 µF

1

1

0.47 µF

0.47 µF

1

1

0.47 µF

. Selection of the above component values gives a frequency response from

rms

2

1200 pF

2

1200 pF

AINRP
AINRM
RINA
RINB

AINLP
AINLM
LINA

LINB

Voltage

Reference

AINRP

AINRM

24-Bit

Stereo

ADC

AINLP

1 Analog Inputs − Use 0.47 µF for 20-Hz Cutoff

2

Anti-Alias Capacitors for fS = 48 kHz

3 Tie unused analog inputs to analog ground through 0.1-µF capacitors.

Figure 3−1. Analog Input to the TAS3002 Device

3.2 Analog Output

3.2.1 Direct Analog Output

The full scale analog output from the TAS3002 device is 0.707 V

1.5 Vdc. VCOM must be decoupled with the network shown in Figure 3−2.

. It is referenced to VCOM which is approximately

rms

AINLM

Input Select Command

From Internal Controller

3−1

AOUTR

(Adjust Capacitors for Desired

Analog Output

Low Frequency Response)

24-Bit

DAC

VCOM

10 µF

AOUTL

+

0.1 µF

AGND

Figure 3−2. VCOM Decoupling Network

3.2.2 Analog Output With Gain

Because the maximum analog output from the TAS3002 device is 0.707 V
using an external amplifier. The circuit shown in Figure 3−3 boosts the output level to 1 V

1.414) and provides improved signal-to-noise ratio (SNR). Since this circuit lowers the noise floor, THD + N is
improved also.

C4

AOUTR

−

C1

+

TLV2362

or Equilvalent

24-Bit

DAC

VCOM

10 µF

C3

+

0.1 µF

, the output level can be increased by

rms

(Adjust Capacitors for Desired

Low Frequency Response)

(when it has a gain of

rms

Analog Output

3−2

C1 = C2 = C

C4 = C

5

3

AOUTL

C2

AGND

+5 Op Amp/2

+5 Op Amp/2

C5C5

−

+

TLV2362

or Equilvalent

Figure 3−3. Analog Output With External Amplifier

3.2.3 Reference Voltage Filter

Figure 3−4 shows the TAS3002 reference voltage filter.

0.1 µF

15 µF

+

0.1 µF

4 23 45

SS

AV

SS(REF)

AV

RFILT

V

REFM

V

1 µF

0.1 µF

REFP

+

44V

TAS3002

Figure 3−4. TAS3002 Reference Voltage Filter

3−3