Texas Instruments TAS3002 User Manual

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Data
Manua
2001 Digital Audio: Digital Speakers
SLAS307B
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Copyright 2001, Texas Instruments Incorporated
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1 Introduction
1.1 Description
The TAS3002 device is a system-on-a-chip that replaces conventional analog equalization to perform digital parametric equalization, dynamic range compression, and loudness contour. Additionally, this device provides high-quality, soft digital volume, bass, and treble control. All control parameters are uploaded from an outside MCU through the I
The TAS3002 device also has an integrated 24-bit stereo codec with two I channel.
The digital parametric equalization consists of seven cascaded, independent biquad filters per channel. Each biquad filter has five 24-bit coefficients that can be configured into many different filter functions (such as band-pass, high-pass, and low-pass).
The internal loudness contour algorithm can be controlled and programmed with an I Dynamic range compression/expansion (DRCE) is programmable through the I
the threshold, energy estimation time constant, compression ratio, and attack and decay time constants. The TAS3002 device supports 13 serial interface formats (I
16, 18, 20, or 24 bits. The sampling frequency (f formats are listed and described in Section 2.1.
The TAS3002 device uses a system clock generated by the internal phase-locked loop (PLL). The reference clock for the PLL is provided by an external master clock (MCLK) of 256f
The TAS3002 device has six internally configurable general-purpose input (GPI) terminals that control volume, bass, treble, and equalization. Each GPI terminal has a debounce algorithm that is programmed into the TAS3002 internal microcontroller.
2
C slave port or from an external EEPROM through the I2C master port.
2
C-selectable, single-ended inputs per
2
C port. The system designer can set
2
S, left justified, right justified) with data word lengths of
) may be set to 32 kHz, 44.1 kHz, or 48 kHz. The 13 serial interface
S
or 512fS, or a 256fS crystal.
S
2
C command.
1.2 Features
Programmable seven-band parametric equalization
Programmable digital volume control
Programmable digital bass and treble control
Programmable dynamic range compression/expansion (DRCE)
Programmable loudness contour/dynamic bass control
Configurable serial port for audio data
Two input data channels that can be mixed with digital data from the analog-to-digital converter (ADC) of
the codec (analog input). These channels are controlled by I
Three output data channels: Left and right data go through equalization; bass, treble, DRCE, and volume to SDOUT1; SDOUT2 mixes left and right data. SDOUT2 operates as a center channel or subwoofer channel. The output of the ADC is available for additional processing.
Capability to di g i t a l l y m i x l e f t a n d r i g h t i n p u t c h a n n els for a monaural output to facilitate subwoofer operation
Serial I
2
C master/slave port that allows:
Downloading of control data to the device externally from the EEPROM or an I
Controlling other I
2
C devices
2
C commands.
2
C master
1−1
Two I2C-selectable, single-ended analog input stereo channels
Equalization bypass mode
Single 3.3-V power supply
Power down without reloading the coefficients
Sampling rates of 32 kHz, 44.1 kHz, or 48 kHz
Master clock frequency of 256f
or 512f
S
S
Can have crystal input to replace MCLK. Crystal input frequency is 256fS.
Six GPI terminals for volume, bass, treble up/down control, mute, and selection of equalization filters
1.3 Functional Block Diagram
Figure 1−1 is a block diagram showing the major functions of the TAS3002.
1−2
AINRP
AINRM
RINA RINB
SS(REF)
REFM
REFP
AV
V
V
Voltage
Reference
AINRP
AINRM
RFILT
V
Analog
Supplies
SS
AVDDAV
Supplies
SS
DVDDDV
Digital
AINLP
AINLM
LINA LINB
ALLPASS
INPA
GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
CS1
SDA
SCL
Controller
C
2
I
Control
L+R
24-Bit
Stereo
ADC
AINLP
AINLM
32-Bit Audio Signal
SDOUT0
VCOM AOUTL AOUTR
24-Bit
Stereo DAC
L+R SDOUT2
Processor
SDOUT1
PWR_DN
RESET
TEST
Control
L
R
SDIN2
SDIN1
SDATA
Control
SCLK/O
LRCLK/O
32-Bit Audio Signal
Processor
OSC/CLK
IFM/S
CLKSEL
Figure 1−1. TAS3002 Block Diagram
Select
MCLK
XTALI/
XTALO
MCLKO
PLL
CAP_PLL
1−3
1.4 Terminal Assignments
I/O
DESCRIPTION
Figure 1−2 shows the terminal locations on the package outline, along with the signal name assigned to each terminal.
PACKAGE
(TOP VIEW)
REFMVREFP
AINRM
LINB
AINLPVAINLM
AINRP
RINB
RINA
VCOM
AOUTL
AOUTR
V
AV
SS(REF)
RESET
PWR_DN
TEST
CAP_PLL
CLKSEL
MCLKO
1.5 Terminal Functions
LINA
RFILT
AV
SS
INPA
CS1
47 46 45 44 4348 42
1 2 3 4 5 6 7 8 9 10 11 12
14 15
13
XTALO
17 18 19 20
16
SCL
SDA
DD
DV
SS
DV
LRCLK/O
40 39 3841
22 23 24
21
IFM/S
SCLK/O
37
SDIN1
SDIN2
XTALI/MCLK
Figure 1−2. TAS3002 Terminal Assignments
NC
36
AV
35
NC
34 33
GPI5
32
GPI4 GPI3
31
GPI2
30
GPI1
29
GPI0
28
ALLPASS
27
SDOUT1
26
SDOUT0
25
SDOUT2
DD
Table 1−1 lists the terminals in alphanumeric order by signal name, along with the terminal number, terminal type, and a description of the terminal function.
Table 1−1. TAS3002 Terminal Functions
TERMINAL
NAME NO.
AINLM 46 I ADC left channel analog input (antialias capacitor) AINLP 47 I ADC left channel analog input (antialias capacitor) AINRM 43 I ADC right channel analog input (antialias capacitor) AINRP 42 I ADC right channel analog input (antialias capacitor) ALLPASS 27 I Logic high bypasses equalization filters AOUTL 39 O Left channel analog output AOUTR 37 O Right channel analog output
1−4
AV
DD
AV
SS
AV
SS(REF)
35 I Analog power supply (3.3 V)
4 I Analog voltage ground 3 I Analog ground voltage reference
Table 1−1. TAS3002 Terminal Functions (Continued)
I/O
DESCRIPTION
TERMINAL
NAME NO.
CAP_PLL 10 I Loop filter for internal phase-locked loop (PLL) CLKSEL 11 I Logic low selects 256fS; logic high selects 512fS MCLK CS1 7 I I2C address bit A0; low = 68h, high = 6Ah
DV
DD
DV
SS
GPI0 GPI1 GPI2 GPI3 GPI4 GPI5
IFM/S 21 I Digital audio I/O control (low = input; high = output) INPA 5 O Low when analog input A is selected (will sink 4 mA) LINA 1 I Left channel analog input 1 LINB 48 I Left channel analog input 2 LRCLK/O 19 I/O Left/right clock input/output (output when IFM/S is high) MCLKO 12 O MCLK output for slave devices NC 34 No connection; Can be used as a printed circuit board routing channel NC 36 No connection; Can be used as a printed circuit board routing channel PWR_DN 8 I Logic high places the TAS3002 device in power-down mode RESET 6 I Logic low resets the TAS3002 device to the initial state RINA 40 I Right channel analog input 1 RINB 41 I Right channel analog input 2 SCL 15 I/O I2C clock connection SCLK/O 20 I/O Shift (bit) clock input (output when IFM/S is high) SDA 16 I/O I2C data connection SDIN1 22 I Serial data input 1 SDIN2 23 I Serial data input 2 SDOUT0 25 O Serial data output from ADC SDOUT1 26 O Serial data output (from internal audio processing) SDOUT2 24 O Serial data output (a monaural mix of left and right, before processing) TEST 9 I Reserved manufacturing test terminal; connect to DV VCOM 38 O Digital-to-analog converter mid-rail supply (decouple with parallel combination of 10-µF and 0.1-µF
V
REFM
V
REFP
V
RFILT
XTALI/MCLK 13 I Crystal or external MCLK input XTALO 14 I Crystal input (crystal is connected between terminals 13 and 14)
17 I Digital power supply (3.3 V) 18 I Digital ground 28
29 30 31 32 33
45 I ADC minus voltage reference 44 I ADC plus voltage reference
2 O Voltage reference low pass filter
I Switch input terminals
capacitors)
SS
1−5
1−6
2 Audio Data Formats
2.1 Serial Interface Formats
The TAS3002 device works in master or slave mode. In the master mode, terminal 21 (IFM/S
) is tied high. This activates the master clock (MCLK) circuitry. A crystal can be connected across terminals 13 (XTALI/MCLK) and 14 (XTALO), or an external, TTL-compatible MCLK can be connected to X TALI/MCLK. In that case, MCLK is outputs on terminal 12 (MCLKO), with terminals 19 (LRCLK/O) and 20 (SCLK/O) becoming outputs to drive slave devices.
In the slave mode, IFM/S
is tied low. LRCLK/O and SCLK/O are inputs and the interface operates as a slave device requiring externally supplied MCLK, LRCLK (left/right clock), and SCLK (shift clock) inputs. There are two options for selecting the clock rates. If the 512f of 512f
must be supplied. If the 256fS MCLK is selected, CLKSEL is tied low and an MCLK of 256fS must be supplied.
S
MCLK rate is selected, terminal 1 1 (CLKSEL) is tied high and an MCLK rate
S
In both cases, an LRCLK of 64SCLK must be supplied.
MCLK and SCLK must be synchronous and their edges must be at least 3 ns apart.
If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.
2
The TAS3002 device is compatible with 13 different serial interfaces. Available interface options are I and left justified. Table 2−1 indicates how the 13 options are selected using the I (MCR, I Additionally, the 16-bit mode operates at 32f
2
C address 01h). All serial interface options at either 16, 18, 20, or 24 bits operate with SCLK at 64 fS.
.
S
2
C bus and the main control register
S, right justified,
Table 2−1. Serial Interface Options
MODE MCR BIT (6) MCR BIT (5−4) MCR BIT (1−0)
0 0 00 00 16-bit, 32f 1 1 00 00 16-bit, left justified, 64f 2 1 01 00 16-bit, right justified, 64f 3 1 10 00 16-bit, I2S, 64f 4 1 00 01 18-bit, left justified, 64f 5 1 01 01 18-bit, right justified, 64f 6 1 10 01 18-bit, I2S, 64f 7 1 00 10 20-bit, left justified, 64f 8 1 01 10 20-bit, right justified, 64f
9 1 10 10 20-bit, I2S, 64f 10 1 00 11 24-bit, left justified, 64f 11 1 01 11 24-bit, right justified, 64f 12 1 10 11 24-bit, I2S, 64f
SDIN1, SDIN2, SDOUT1, SDOUT2, AND SDOUT0
S
S
S
S
S
SERIAL INTERFACE
S
S
S
S
S
S
S
S
Figure 2−1 through Figure 2−3 illustrate the relationship between the SCLK, LRCLK, and the serial data I/O for the different interface protocols.
2−1
2.2 Digital Output Modes
The digital output modes (SDOUT1, SDOUT2, SDOUT0) are described in Sections 2.2.1 through 2.2.3.
2.2.1 MSB-First, Right-Justified, Serial-Interface Format
The normal output mode for the MSB-first, right-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−1 shows the following characteristics of this protocol:
Left channel is transmitted when LRCLK is high.
The SDIN(s) (recorded) data is justified to the trailing edge of the LRCLK.
The SDOUT(s) MSB (playback) data is transmitted at the same time as LRCLK edge and captured at the
next rising edge of SCLK.
If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.
SCLK
LRCLK = f
SDIN
SDOUT
S
MSB LSB
……
Figure 2−1. MSB-First, Right-Justified, Serial-Interface Format
MSB LSB
………… ……
…… ……
Left Channel Right Channel
MSB LSB
MSB LSB
……
……
2−2
2.2.2 I2S Serial-Interface Format
The normal output mode for the I2S serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−2 shows the following characteristics of this protocol:
Left channel is transmitted when LRCLK is low.
SDIN is sampled with the rising edge of SCLK.
SDOUT is transmitted on the falling edge of SCLK.
If the LRCLK phase changes by more than 10 cycles ofMCLK, the codec automatically resets.
SCLK
LRCLK = f
SDIN
SDOUT
S
X LSB
MSB
X LSB
MSB
……
……
Left Channel Right Channel
Figure 2−2. I2S Serial-Interface Format
X LSB
MSB
X LSB
MSB
……
……
2−3
2.2.3 MSB-Left-Justified, Serial-Interface Format
The normal output mode for the MSB-left-justified, serial-interface format is for 16, 18, 20, or 24 bits. Figure 2−3 shows the following characteristics of this protocol:
Left channel is transmitted when LRCLK is high.
The SDIN data is justified to the leading edge of the LRCLK.
The MSBs are transmitted at the same time as LRCLK edge and captured at the next rising edge of SCLK.
SCLK
LRCLK = f
SDIN
SDOUT
S
MSB LSB
MSB LSB
……
……
Left Channel Right Channel
Figure 2−3. MSB-Left-Justified, Serial-Interface Format
……
……
MSB LSB
MSB LSB
……
……
……
……
2−4
2.3 Switching Characteristics
PARAMETER MIN TYP MAX UNIT
t
c(SCLK)
t
d(SLR)
t
d(SDOUT)
t
su(SDIN)
t
h(SDIN)
f
(LRCLK)
NOTE 1: Maximum of 50-pF external load on SDOUT.
SCLK cycle time 325.5 ns SCLK rising to LRCLK edge 20 ns SDOUT valid from SCLK falling edge (see Note 1) (1/256fS) + 10 ns SDIN setup before SCLK rising edge 20 ns SDIN hold after SCLK rising edge 100 ns LRCLK frequency 32 44.1 48 kHz Duty cycle 50 %
t
c(SCLK)
SCLK
LRCLK
t
d(SLR)
t
f(SCLK)
t
r(SCLK)
SDOUT1 SDOUT2 SDOUT0
SDIN1 SDIN2
t
h(SDIN)
t
d(SLR)
t
su(SDIN)
t
d(SDOUT)
Figure 2−4. For Right-/Left-Justified and I2S Serial Protocols
2−5
2−6
3 Analog Input/Output
The TAS3002 device contains a stereo 24-bit ADC with two single-ended inputs per channel. Selection of the A or B analog input is accomplished by setting a bit in the analog control register (ACR) by an I
2
C command. Additionally,
the TAS3002 device has a stereo 24-bit digital-to-analog converter (DAC).
3.1 Analog Input
Figure 3−1 shows the technique and components required for analog input to the TAS3002 device. The maximum input signal must not exceed 0.7 V 20 Hz to 20 kHz at a sampling frequency of 48 kHz without alias frequency problems.
0.47 µF
1
1
0.47 µF
0.47 µF
1
1
0.47 µF
. Selection of the above component values gives a frequency response from
rms
2
1200 pF
2
1200 pF
AINRP AINRM RINA RINB
AINLP AINLM LINA
LINB
Voltage
Reference
AINRP
AINRM
24-Bit
Stereo
ADC
AINLP
1 Analog Inputs − Use 0.47 µF for 20-Hz Cutoff
2
Anti-Alias Capacitors for fS = 48 kHz
3 Tie unused analog inputs to analog ground through 0.1-µF capacitors.
Figure 3−1. Analog Input to the TAS3002 Device
3.2 Analog Output
3.2.1 Direct Analog Output
The full scale analog output from the TAS3002 device is 0.707 V
1.5 Vdc. VCOM must be decoupled with the network shown in Figure 3−2.
. It is referenced to VCOM which is approximately
rms
AINLM
Input Select Command
From Internal Controller
3−1
AOUTR
(Adjust Capacitors for Desired
Analog Output
Low Frequency Response)
24-Bit
DAC
VCOM
10 µF
AOUTL
+
0.1 µF
AGND
Figure 3−2. VCOM Decoupling Network
3.2.2 Analog Output With Gain
Because the maximum analog output from the TAS3002 device is 0.707 V using an external amplifier. The circuit shown in Figure 3−3 boosts the output level to 1 V
1.414) and provides improved signal-to-noise ratio (SNR). Since this circuit lowers the noise floor, THD + N is improved also.
C4
AOUTR
C1
+
TLV2362
or Equilvalent
24-Bit
DAC
VCOM
10 µF
C3
+
0.1 µF
, the output level can be increased by
rms
(Adjust Capacitors for Desired
Low Frequency Response)
(when it has a gain of
rms
Analog Output
3−2
C1 = C2 = C
C4 = C
5
3
AOUTL
C2
AGND
+5 Op Amp/2
+5 Op Amp/2
C5C5
+
TLV2362
or Equilvalent
Figure 3−3. Analog Output With External Amplifier
3.2.3 Reference Voltage Filter
Figure 3−4 shows the TAS3002 reference voltage filter.
0.1 µF
15 µF
+
0.1 µF
4 23 45
SS
AV
SS(REF)
AV
RFILT
V
REFM
V
1 µF
0.1 µF
REFP
+
44V
TAS3002
Figure 3−4. TAS3002 Reference Voltage Filter
3−3
3−4
4 Audio Control/Enhancement Functions
4.1 Soft Volume Update
The TAS3002 device implements a TI proprietary soft volume update. This feature allows a smooth and pleasant-sounding change from one volume level to another over the entire range of volume control (18 dB to mute).
2
The volume is adjustable by downloading a gain coefficient through the I integer and 16 bits for the fractional part. NO TAG lists the 4.16 coefficients converted into dB for the range of –70 dB to 18 dB with 0.5-dB step resolution.
Right and left channel volumes can be unganged and set to different values. This feature implements a balance control.
Volume is changed by writing the desired value into the volume control registers. This is done by asserting the volume-up or volume-down GPI terminal (see Section 7.6.1) for a limited range of volume control. Alternatively, volume control settings can be sent to the TAS3002 device over the I
4.2 Software Soft Mute
Soft mute is implemented by loading all zeros in the volume control register. This causes the volume to ramp down over a duration of 2048f
Soft mute can be enabled by either asserting the mute GPI terminal (see Section 7.6.1) or sending a mute command over the I
2
C bus. Subsequent assertions of the mute GPI terminal toggle soft mute off and on.
samples to a final output of 0 (− infinity dB).
S
C interface in 4.16 format—4 bits for the
2
C bus.
4.3 Input Mixer Control
The TAS3002 device is capable of mixing and multiplexing three channels (SDIN1, SDIN2, and the ADC output) of serial audio data. The mixing is controlled through three mixer control registers. This is accomplished by loading values into the corresponding bytes of the mixer left gain (07h) and mixer right gain (08h) control registers. See Figure 4−1 for a functional block diagram of the input mixer.
The values loaded into these registers are in 4.20 format—4 bits for the integer and 20 bits for the fractional part. NO TAG lists the 4.20 numbers converted into dB for the range of –70 dB to 18 dB, although any positive 4.20 number may be used.
To mute any of the channels, 0s are loaded into the respective mixer control register. Mixer controls are updated instantly and can cause audible artifacts for large changes in setting when updated
dynamically outside of the fast load mode; therefore, it is desirable to use fast load in conjunction with the soft-volume mode.
SDIN1, SDIN2, and the ADC output can be mixed with a user-selectable gain for each channel. The gain control registers are represented in 4.20 format.
4−1
SDIN1_L
Left Channel Mix Coefficients I2C Register Address 08h
SDIN1 ^ SDIN2 ^ ADC
= (3) 24-Bit Left Mix Coefficient
SDIN2_L
ADC_L
SDIN1_R
SDIN2_R
ADC_R
L_SUM
R_SUM
Right Channel Mix Coefficients I2C Register Address 07h
7 Biquad
Filters
7 Biquad
Filters
1/2
1/2
Tone
Tone
Figure 4−1. TAS3002 Mixer Function
Soft
Volume
DRCE
Soft
Volume
DRCE
L + R_SUM
SDIN1 ^ SDIN2 ^ ADC
= (3) 24-Bit Right Mix Coefficient
SDOUT1
SDOUT2
4.4 Mono Mixer Control
The TAS3002 device contains a second mixer that performs the function of mixing left and right channel digital audio data from the input mixer in order to derive a monaural channel. This mixer has a fixed gain of −6 dB so that full scale inputs on L_sum and R_sum do not produce clipping on the resulting L+R_sum.
The output of this mixer is present on terminal 24 (SDOUT2) and is generally used for a digitally-mixed subwoofer or center channel application.
4.5 Treble Control
The treble gain level may be adjusted within the range of 15 dB to – 15 dB with 0.5-dB step resolution. The level changes are accomplished by downloading treble codes (shown in NO TAG) into the treble gain register. Alternatively, a limited range of treble control is available by asserting the treble-up or treble-down GPI terminal (see Section 7.6.1).
The treble control has a corner frequency of 6 kHz at a 48-kHz sample rate. The gain values for treble control can be found in Section NO TAG.
4−2
4.6 Bass Control
The bass gain level can be adjusted within the range of 15 dB to −15 dB with 0.5-dB step resolution. The level changes are accomplished by downloading bass codes (shown in NO TAG) into the bass frequency control register. Alternatively, a limited range of bass control is available by asserting the bass-up or bass-down GPI terminal (see Section 7.6.1).
Bass control is a shelf filter with a corner frequency of 250 Hz at a 48-kHz sample rate. The gain values for bass control can be found in Section NO TAG.
4.7 De-Emphasis Mode (DM)
De-emphasis is implemented in the DAC and is software controlled. De-emphasis is valid at 44.1 kHz and 48 kHz.
2
To enable de-emphasis, values are written into the analog control register via the I analog control register operation.
Figure 4−2 illustrates the frequency response of the de-emphasis mode.
C command. See Section 4.8 for
Response (dB)
De-Emphasis
3.18
(50 µs)
Frequency (kHz)
10.6
(15 µs)
Figure 4−2. De-Emphasis Mode Frequency Response
4−3
4.8 Analog Control Register (40h)
The analog control register (ACR) allows control of de-emphasis, selection of the analog input channel to the ADC, and analog power down.
2
C master is required to write the appropriate command into the ACR. The ACR subaddress is 40h.
An I
Bit 7 6 5 4 3 2 1 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0
Table 4−1. Analog Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
7 Reserved R/W Reset to 0
6 Reserved R/W Reset to 0
5−4 Reserved R/W Reserved. Bits 5 and 4 return 0s when read. 3−2 DM(1−0) R/W De-emphasis control
00 = De-emphasis off (initial condition after reset) 01 = 48 kHz sample rate de-emphasis selected 10 = 44.1 kHz sample rate de-emphasis selected 11 = Reserved
1 INP R/W Analog input select
0 = LINA and RINA selected (initial condition after reset) 1 = LINB and RINB selected
0 APD R/W Analog power down
0 = Normal operation (initial condition after reset) 1 = Power down
4−4
4.9 Dynamic Loudness Contour
The necessity for applying loudness compensation to playback systems to compensate for the fact that the ear perceives bass and treble less audibly at low levels than at high ones has been established since the first data was published by Fletcher and Munson in 1933.
There are many equal-loudness contours in publication, like Steven’s contours, Robinson and Dadson contours. Some have even reached the acceptance level of ISO recommendation.
The TAS3002 device has a simplified loudness contour algorithm that diminishes the effect of weak bass at low listening levels. Since contour has volume level dependency, the user must define the relation between the gain of the contour circuit and the volume level.
Figure 4−3 is a block diagram of this circuit.
Volume
Biquad Gain
Figure 4−3. Dynamic Loudness Contour Block Diagram
2
The loudness contour is activated by sending an activation command via I contour gain command can be sent by an external device to provide tracking with the system volume control.
C from an external device. Optionally, a
4.9.1 Loudness Biquads
Loudness biquad filters for the left and right channels are independently programmable via I2C. Their subaddresses are 21h and 22h, respectively. The digital filters are written as five 24-bit (4.20) hex coefficients for each channel.
4.9.2 Loudness Gain
Loudness gain values for the left and right channels are independently programmable via I2C. Their subaddresses are 23h and 24h, respectively. The gain values are written as one 4.20 hex coefficient for each channel.
4.9.3 Loudness Contour Operation
When the frequency of the loudness contour is determined, a digital filter must be developed. Then, the gain of the filter is determined. These values are placed in the storage area of the system controller (microcontroller) and sent to the TAS3002 device when it is desired to activate the loudness contour.
If it is necessary to change the frequency or gain of the contour, new gain and filter coefficients are sent by the system controller. This function is performed normally when the volume control is changed (that is, more volume, less contour). The gain of the loudness contour filter then tracks the volume control.
The loudness contour biquad filters are provided in addition to the seven equalization biquad filters. See Section NO TAG for programming instructions.
4−5
4.10 Dynamic Range Compression/Expansion (DRCE)
(
T
The TAS3002 device provides the user with the ability to manage the dynamic range of the audio system. The DRCE receives data, and affects scaling after the volume/loudness block. As shown in Figure 4−4, the DRCE is applied after the volume/loudness control block as a DRCE scale factor. The DRCE must be adjusted such that the signal does not reach the hard limit value. However, if the signal does reach the maximum digital value, the saturation logic serves as a hard limiter that does not allow the signal to extend beyond the available range.
Loudness
(Left Channel Mixer)
SDIN1_L
LEFT_SUM
SDIN2_L
ANALOGIN_L
(Parametric
Equalization)
(7)
2nd Order
IIR Filters
(Tone)
Bass/
Treble
Soft
Volume/
(DRCE Scaling)
Saturation
Logic
LEFT_OUT
Analog in From ADC)
ANALOGIN_R
SDIN1_R
SDIN2_R
(Right Channel Mixer)
RIGHT_SUM
(7)
2nd Order
IIR Filters
(Parametric
Equalization)
Bass/
Treble
(Tone)
Dynamic
Range
Control
Soft
Volume/
Loudness
(DRCE Scaling)
Saturation
Logic
RIGHT_OU
Figure 4−4. TAS3002 Digital Signal Processing Block Diagram
The DRCE instruction consists of eight bytes that must be sent each time in the order shown in the example code of NO TAG. Each instruction downloaded must be eight bytes. If only one byte is changed, all eight bytes must be transmitted. The first two bytes remain the same for every instruction, however the last six bytes can be programmed using hexadecimal values from the corresponding tables referred to in Section NO TAG.
With high compression ratios and fast attack times available, this function is suited for a commercial killer in a television set application.
4.11 AllPass Function
This function is enabled by setting terminal 27 (ALLP ASS) on the TAS3002 device to 1. When asserted, the internal equalization filters are set into AllPass (flat) mode. When this terminal is reset to 0, the equalization filters are returned to the equalization that was in use before the terminal was asserted.
In AllPass mode, the bass and treble controls are still functional. This function is frequently used for headphones. When the headphone plug is inserted into its jack, a switched contact
in the jack enables the AllPass function. The AllPass function also can be activated by writing a 1 to bit 2 of the analog control register.
4−6
4.12 Main Control Register 1 (01h)
The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2 (MCR2). The MCR1 register contains the bits associated with load speed, SCLK frequency, serial-port mode, and serial-port word length. It is accessed via I
MCR1 (01h)
Bit b7 b6 b5 b4 b3 b2 b1 b0 Type R/W R/W R/W R/W R R R/W R/W Default 1 X X X X X X X
Table 4−2. Main Control Register 1 Description
BIT
7 FL R/W Fast load
6 SC R/W SCLK frequency
5−4 E R/W Serial port mode
3−2 Reserved R Reserved 1−0 W R/W Serial port word length
FIELD NAME
TYPE DESCRIPTION
2
C with the address 01h.
0 = Normal operation mode 1 = Fast -load mode (default)
0 = SCLK is 32 f 1 = SCLK is 64 fS.
00 = Left justified 01 = Right justified 10 = I2S 11 = Reserved
00 = 16-bit 01 = 18-bit
10 = 20-bit 11 = 24-bit
.
S
4.13 Main Control Register 2 (43h)
The TAS3002 device contains two main control registers: main control register 1 (MCR1) and main control register 2 (MCR2). The MCR2 register contains the bits associated with the AllPass function and the download of bass and treble control information, and it is accessed via I
MCR2 (43h)
Bit 7 6 5 4 3 2 1 0 Type R/W R R R R R R/W R Default 0 0 0 x x x 0 0
Table 4−3. Main Control Register 2 Description
BIT
7 Reserved R/W 0 = Normal operation (initial condition after reset)
6−5 Reserved R Reserved. Bits 6 and 5 return 0s when read. 4−2 Reserved R Undefined.
1 DM(1−0) R/W 0 = Normal operation (initial condition after reset)
0 INP R Reserved. Bit 0 returns 0 when read.
FIELD NAME
TYPE DESCRIPTION
1 = Download bass and treble
1 = AllPass mode (bass and treble are still functional)
2
C with the address 43h.
4−7
4−8
5 Filter Processor
(1)
5.1 Biquad Block
The biquad block consists of seven digital biquad filters per channel organized in a cascade structure, as shown in Figure 5−1. Each of these biquad filters has five downloadable 24-bit (4.20) coefficients. Each stereo channel has independent coefficients.
Biquad 1 ...Biquad 0 Biquad 6
Figure 5−1. Biquad Cascade Configuration
5.1.1 Filter Coefficients
The filter coefficients for the TAS3002 device are downloaded through the I2C port and loaded into the biquad memory space. Each biquad filter memory space has an independent address. Digital audio data coming into the device is processed by the biquad block and then converted into analog waveforms by the DAC. Alternatively, filters can be loaded by asserting terminals on the GPI port.
5.1.2 Biquad Structure
The biquad structure that is used for the parametric equalization filters is as follows:
H(z) +
b0) b1z*1) b2z a0) a1z*1) a2z
NOTE: a0 is fixed at value 1 and is not downloadable.
The coefficients for these filters are represented in 4.20 format—4 bits for the integer part and 20 bits for the fractional part. In order to transmit them over I of byte 2 comprise the integer part; the lower 4 bytes of byte 2 plus byte 1 and byte 0 comprise the fractional part.
The filters can be designed using the automatic loudspeaker equalization program (ALE) or a script running under MatLab named Filtermaker. Both of these tools are available from Texas Instruments.
*2 *2
2
C, it is necessary to separate each coefficient into three bytes. The upper 4 bits
5−1
5−2
6I2C Serial Control Interface
6.1 Introduction
Control parameters for the TAS3002 device can be loaded from an I2C serial EEPROM by using the T AS3002 master interface mode. If no EEPROM is found, the TAS3002 device becomes a slave device and loads from another I
2
master interface. Information loaded into the TAS3002 registers is defined in Appendix A.
2
C bus uses terminals 16 (SDA for data) and 15 (SCL for clock) to communicate between integrated circuits in
The I a system. These devices can be addressed by sending a unique 7-bit slave address plus R/W
bit (1 byte). All compatible devices share the same terminals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used to set the high level on the bus. The TAS3002 device operates in standard mode up to 100 kbps with as many devices on the bus as desired up to the capacitance load limit of 400 pF.
Furthermore, the TAS3002 device supports a subset of the SMBus protocol. When it is attached to the SMBus, then byte, word, and block transfers are supported. The SMBus NAK function is not supported and care must be taken with the sequence of the instructions sent to the TAS3002 device.
Additionally, the T AS3002 device operates in either master or slave mode; therefore, at least one device connected to the I
2
C bus must operate in master mode.
6.2 I2C Protocol
The bus standard uses transitions on SDA while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. Figure 6−1 shows these conditions. These start and stop conditions for the
2
I
C bus are required by standard protocol to be generated by the master. The master must also generate the 7-bit slave address and the read/write (R/W acknowledge condition. The slave holds SDA low during acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
) bit to open communication with another device and then wait for an
C
After each 8-bit word, an acknowledgment must be transmitted by the receiving device. There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. Figure 6−1 shows a generic data transfer sequence.
SDA
SCL
Start
7-Bit
Slave Address
R/ W
0
167
8-Bit Register Data
A
for Address (N)
0
167
8-Bit Register Data
A
for Address (N+1)
0
167
8-Bit Register Data
A
for Address (N+2)
A
0
167
Stop
Figure 6−1. Typical I2C Data Transfer Sequence
6−1
Table 6−1 lists the definitions used by the I2C protocol.
2
T able 6−1. I
DEFINITION DESCRIPTION
Transmitter The device that sends data Receiver The device that receives data Master The device that initiates a transfer, generates clock signals, and terminates the transfer Slave The device addressed by the master Multimaster More than one master can attempt to control the bus at the same time without corrupting the message. Arbitration Procedure to ensure the message is not corrupted when two masters attempt to control the bus. Synchronization Procedure to synchronize the clock signals of two or more devices
C Protocol Definitions
6.3 Operation
The 7-bit address for the TAS3002 device is 0110 10X R/W where X is a programmable address bit, set by terminal 7 (CS1). Combining CS1 and the R/W and two write). These two addresses are licensed I devices. In addition to the 7-bit device address, subaddresses direct communication to the proper memory location within the device. A complete table of subaddresses and control registers is provided in Appendix A. For example, to change bass to 10-dB gain, Section 6.3.1 shows the data that is written to the I
I2C ADDRESS BYTE A6 −A1 CS1 (A0) R/W
68h 011010 0 0
69h 011010 0 1 6Ah 011010 1 0 6Bh 011010 1 1
bit, the TAS3002 device can respond to four different I2C addresses (two read
2
C addresses that do not conflict with other licensed I2C audio
2
C port:
2
T able 6−2. I
C Address Byte Table
6.3.1 Write Cycle Example
Start Slave Address R/W A Subaddress A Data A Stop
FUNCTION DESCRIPTION
Start Start condition as defined in I2C Slave address 0110100 (CS1 = 0) R/W 0 (write) A Acknowledgement as defined in I2C (slave) Subaddress (treble control register) 0000 0101 Data (0 dB gain) 0111 0010 Stop Stop condition as defined in I2C
NOTE: Table is for serial data (SDA); serial clock (SCL) is not shown but conditions apply as well.
Whenever writing to a subaddress, the correct number of data bytes must follow in order to complete the write cycle. For example, if the volume control register with subaddress 04h is written to, six bytes of data must follow; otherwise, the cycle is incomplete and errors occur.
6−2
6.3.2 TAS3002 I2C Readback Example
The T AS3002 saves in a stack or first-in first-out (FIFO) buf fer the last 7 bytes that were sent to it. When an I2C read command is sent to the device (LSB=high), it answers by popping the first byte off the stack. The TAS3002 then expects either a Send Ack command or an I the host then the TAS3002 pops another byte off the stack. If an I transaction. The proper sequence for reading is described as follows:
I2C Start
Send I2C address byte with read bit set to 1 (LSB set equal to 1) Receive Byte 0 Send Ack Receive Byte 1 Send Ack Receive Byte 2 Send Ack Receive Byte 3 Send Ack Receive Byte 4 Send Ack Receive Byte 5 Send Ack Receive Byte 6 (if an ACK is sent after byte 6 it locks up the TAS3002) I2C Stop
2
C Stop command from the host. If a Send Ack command is sent from
2
C Stop is sent then the TAS3002 ends this
Where:
2
C Start is a valid I2C Start command.
I
Receive Byte is a valid I
Send Ack is a a valid I
2
C Stop is a valid I2C Stop command.
I
NOTES: 1. The TAS3002 will appear to be locked up, if a Send Ack is issued after the last byte read. It is required to send an I2C Stop command
after the last byte and not a Send Ack.
2. The I2C Start and I2C Stop commands are the same for both I2C read and I2C write.
2
C command which reads a byte from the TAS3002.
2
C command that informs the TAS3002 that a byte has been read.
6.3.3 I2C Wait States
The TAS3002 device performs interpolation algorithms for its volume and tone controls. If a volume or tone change is sent to the part via I state to occur. This wait state lasts from 41 ms to 231 ms, depending on the system clock rate, the command sent, and, in the case of bass or treble, the amount of the change.
Secondly, if a long series of commands is sent to the TAS3002 device, it may occasionally create a short wait state on the order of 150 µs to 300 µs while it loads and processes the commands.
When a sample rate of 32 kHz is used, longer wait states can occur, occasionally up to 15 ms. The preferred way to take care of wait states is to use an I
state period, it stops sending data over I be implemented in the system software to ensure that the controller is not trying to send more data while the TAS3002 device is busy. Sending I then be reset.
2
C, the command sent after the volume or tone (bass and treble) change causes an I2C wait
2
2
C. If this function is not available on the system controller, fixed delays can
2
C data while the T AS3002 device is busy causes errors and locks up the device, which must
C controller that recognizes wait states. During the wait
6−3
Table 6−3 gives typical values of the wait states that can be expected with the various functions of the part:
2
T able 6−3. I
SYSTEM SAMPLING FREQUENCY
32 kHz 44.1 kHz 48 kHz
Volume 62 ms 49 ms 41 ms Not dependent on size of change Bass 231 ms 167 ms 153 ms 0 to −18 dB Treble 231 ms 167 ms 153 ms 0 to −18 dB DRC on 300 µs 300 µs 300 µs Mixer None None None Loudness None None None Equalization 15 ms 190 µs 300 µs Can occur with each filter
C Wait States
Comment
6.4 SMBus Operation
The TAS3002 device supports a subset of the SMBus protocol. With proper programming techniques, it is possible to use the SMBus to set up the TAS3002 device.
6.4.1 Block Write Protocol
The TAS3002 device supports the block write protocol that allows up to 32 bytes to be sent as a block. To send a command using this format, the most significant bit (MSB) of the TAS3002 subaddress must be set high and the subaddress (also with MSB set high) must be programmed into the SMBus command byte. This operation signals the T AS3002 device that the next byte is the SMBus byte-count byte. The next byte after the byte count is then entered into the device as the first byte of data.
SMBus
Command Byte
68h 8rh xx dd dd dd
TAS3002
Address
Subaddress
(r = subaddress)
Byte Count
(Don’t Care)
Data Data Data
6.4.2 Write Byte Protocol
The TAS3002 device also supports the SMBus write byte protocol. Writing to the main control register (MCR), bass, and treble registers requires using the byte write protocol. To send a command using this protocol, the most significant bit (MSB) of the TAS3002 subaddress must be set high and the subaddress (also with MSB set high) must be programmed into the SMBus command byte. The next byte after the command byte is then entered into the device as the first byte of data.
SMBus
Command Byte
68h
TAS3002
Address
8rh dd
Subaddress
(r = subaddress)
Data
6−4
6.4.3 Wait States
If separate I2C/SMBus commands are sent too frequently, the TAS3002 device can generate a bus wait state. This happens when the device is busy while performing smoothing operations and changing volume, bass, and treble. The wait occurs after the bus acknowledge on the first data byte and can exceed the maximum allowable time allowed according to the SMBus specification (worst case 200 ms).
The following is a possible bus wait state scenario:
CODE Start 68 84 06 01 00 00 01 00 00 Stop
ACTUAL Start 68 84 06 01 Wait
If the master does not recognize bus waiting or if the master times out on a long wait, the master must not send consecutive I2C/SMBus commands without a time interval of 200 ms between transactions.
00 00 01 00 00 Stop
6.4.4 TAS3002 SMBus Readback
The TAS3002 device supports a subset of SMBus readback. When an SMBus read command is sent to the device (LSB = high), it answers with the subaddress and the last six bytes written.
SMBus
Command
Byte
SENT
RECEIVED Start 07h aah ddh ddh ddh ddh ddh ddh Stop
Start 69h xxh 07h Stop
Byte
Count
Byte
Count
Where:
xxh = Command byte. It is a don’t care because the response contains only the subaddress and the
last six bytes of data written to the TAS3002 device. aah = The last subaddress accessed in the device ddh = Data bytes from the TAS3002 device
NOTE: Use read sequence defined in 6.3.2
6−5
6−6
7 Microcontroller Operation
The TAS3002 device contains an internal microcontroller programmed by Texas Instruments to perform housekeeping and interface functions. Additionally, it handles I
2
C communication and general purpose input
functions.
7.1 General Description
The microcontroller uses a 256fS system clock and can access up to 8K bytes of memory . It interfaces with the digital audio interface I transferring coefficients and other information.
The TAS3002 coefficients are loaded through I (volume, bass, and treble) can be controlled/activated through external switches connected to the six GPI terminals. Upon reset, the internal microcontroller sets all coefficients and audio parameters to the default values. See Section 7.2.2 for default values.
If the TAS3002 address is 68h (ADDR_SEL=0), it becomes the bus master device and attempts to load parameters and coefficients from the external EEPROM. If no EEPROM is present, the TAS3002 device remains in its default condition. If addresses other than 68h/69h are set, the TAS3002 device only operates as an I
If the microcontroller determines the TAS3002 device has an I the microcontroller downloads coefficients from the EEPROM. Once the download is complete, it enables the serial audio in the mode defined by an I EEPROM, the serial audio port defaults to I
The TAS3002 device allows the user to update volume, bass, and treble dynamically by an I by a simple GPI input. The GPI can select volume up and down, bass/treble up and down, or digital equalizations. Up to five different equalizations (that is, flat, jazz, rock, voice, etc.) can be stored in the external EEPROM. Also, DRCE, MCR1, MCR2, and loudness contour are enabled and disabled by I
When the TAS3002 device operates in the I addresses that are defined in its external EEPROM. If no addresses are defined, it does not echo.
2
C master/slave for downloading data and coefficients. It also interfaces with two internal DSPs for
2
C in the master or slave mode. Standard audio processing functions
2
C slave device.
2
C address of 68h/69h and the EEPROM is present,
2
C write to the MCR to transfer data into and out of the device. Before reading the
2
S mode.
2
C slave command or
2
C.
2
C master mode, it echoes changes to all of its functions to other I2C
7.2 Power-Up/Power-Down Reset
7.2.1 Power-Up Sequence
An active low on terminal 6 (RESET) while MCLK is running resets the internal microcontroller and DSPs. RESET synchronizes internally and can be asserted asynchronously or with the simple RC circuit in Figure 7−1. On reset, SCL and SDA go to a high-impedance state. If the I returns to a 1 , the device sends a one-byte query via I2C to look for an EEPROM. If an EEPROM is found, the T AS3002 becomes an I
2
C master; otherwise, it becomes an I2C slave. When using address 68h in the slave mode, an external
master must wait until after the EEPROM query or else bus contention and improper operation occur.
2
I
C address x6Ah does not query the bus for an EEPROM. The address for the EEPROM is A0h.
7.2.2 Reset
The TAS3002 device has an asynchronous reset terminal (RESET). This reset is synchronized with various clocks used in this device to generate a synchronous internal reset. Upon reset, the TAS3002 device goes through the following process:
Clears all the RAM memory content
2
C address is set to 68h, approximately 400 µs after RESET
7−1
Clears all the registers in the circuits
Purges the codec
Selects analog input A (RINA and LINA) and sets the input A active indicator (INPA
) low
Initializes the equalization parameters to AllPass filters
Sets the digital audio interface to the I
2
S 18-bit mode
Sets the bass/treble to 0 dB
Sets the mixer gain to 0 dB SDIN1 and mutes both SDIN2 and analog-in
Sets the volume to –40 dB
Turns off all enhancement features (DRCE, etc.)
Reads the I
2
C address. If the address is 68h, the device reads its EEPROM. It is possible to load the user-defined bass/treble data and break points (optional). If there is no data, the device loads default bass/treble delta and break points from ROM.
If the address is 6Ah, the device puts the I
2
C interface in slave mode and waits for input.
7.2.3 Reset Circuit
Because the TAS3002 device has an internal power-on reset (POR), in many cases, additional components are not needed to reset the device. It resets internally at approximately 80% of V
In the case where the system power supplies are slow in reaching their final voltage or where there is a difference in the time the system power supplies take to become stable, the TAS3002 reset can be delayed by a simple RC circuit.
DD
.
DV
DD
10 k
TAS3002
6
RESET
0.1 µF
DV
SS
Figure 7−1. TAS3002 Reset Circuit
The reset delay for the above circuit can be calculated by the simple equation: t
= 0.8RC + 400 µs
rd
Where: t
= The delay before the TAS3002 device comes out of reset
rd
C = Value of the capacitance from RESET R = Value of the resistance from RESET (pin 6) to DV
(pin 6) to DV
DD
SS
The circuit described in Figure 7−1 delays the start-up of the TAS3002 device approximately 1.2 ms. When it is necessary to control the reset of the TAS3002 device with an external device, such as a microcontroller,
RESET
(pin 6) can be treated as a logic signal. It then brings the device out of reset when the voltage on RESET
reaches VDD/2.
7.2.4 Fast Load Mode
While in fast load mode—FL bit (bit 7 of main control register 1) = 0—it is possible to update the parametric equalization without any audio processing delay. The audio processor pauses while the RAM is updated in this mode.
7−2
Bass and treble cannot download in this mode. Mixer1 and Mixer2 registers can download in this mode or normal mode (FL bit = 0).
Once the download is complete, the fast load bit must be cleared by writing a 0 into bit 7 of main control register 1 (MCR1). This puts the TAS3002 device into normal mode.
7.2.5 Codec Reset
During initialization, the output of the codec is disabled. Throughout reset and initialization, the output of the DAC is muted to prevent extraneous noise being sent to the system output.
Data from the ADC and other internal processing is purged so that when reset/initialization is complete, only valid inputs are sent to the system output.
7.3 Power-Down Mode
The TAS3002 device has an asynchronous power-down mode. In the power-down mode, the internal control registers and equalization programming of the device are stored in the device.
To enter power-down mode:
1. Assert the power-down control signal (1)
2. Set the serial audio input clocks to 0 The TAS3002 device goes into power-down mode. To exit the power-down mode:
1. Assert RESET
2. Restart the serial audio clocks
3. Wait for a delay of 1.0 ms (to allow the PLL to lock)
4. Negate the power-down control signal (logic 0)
5. Negate RESET The device then returns to the state it was in before power down (resumes normal operation).
(logic 0)
(logic 1)
7−3
7.3.1 Power-Down Timing Sequence
PWR_DN
RESET
MCLK
SCLK
LRCLK
SDATA
Power-Down Mode
1 ms
Normal Operation
Figure 7−2. Power-Down Timing Sequence
In power-down mode, the TAS3002 device typically consumes less than 1 mA.
7.4 Test Mode
Terminal 9 (TEST) is tied low in normal operation. This function is reserved for factory test and must not be asserted.
7.5 Internal Interface
Figure 7−3 shows the flow chart of the interface between the microcontroller and its peripheral blocks.
7.6 GPI Terminal Programming
During initialization, the microcontroller fetches a control byte from its EEPROM or receives a command from I2C.
7.6.1 GPI Interface
The six GPI terminals are programmed to operate as indicated in Table 7−1.
7−4
Table 7−1. GPI Terminal Programming
GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
VOL_UP, +1 dB x VOL_DN, −1 dB x BASS_UP, +1 dB x BASS_DN, −1 dB x TREB_UP, +1 dB x TREB_DN, −1 dB x Shift 1 x x Mute x EQ1 x EQ2 x EQ3 x EQ4 x EQ5 x
Shift 2 x x
NOTE: x = Logic low
Initially (after reset), the TAS3002 GPI is set to control volume, bass, and treble. Simultaneously setting GPI bits 1 and 5 low for 1 second changes the function of the GPI terminals to control mute and equalization.
To return to volume, bass, and treble control, simultaneously set GPI terminals 2 and 3 low for 1 second.
2
When a GPI terminal is activated, the TAS3002 device echoes its function over I
C to a TAS3001 device mapped to address 6Ah. Therefore, a system with two audio equalization chips can be implemented without the need for a microcontroller.
7.6.2 GPI Architecture
The GPI provides simple but flexible input port to activate the input parameters. Each terminal input is an active logic low.
7−5
Start
Power Up
Restore Volume
and MCR
Initialize Default
EEPROM
Slave Write
GPI
Power Down
Initialize TAS3002
TAS3001
Load Parameters
and Coefficients
to DSP
Volume/Bass/Treble Up/Down
Echo to TAS3001
Switch BQ Set
Save Volume, Mute
Save PWR_DN
Stop PLL
7−6
DRC_OFF
Stop
DRC
Figure 7−3. Internal Interface Flow Chart
7.7 External EEPROM Memory Maps
Left channel
Right channel
Table 7−2 through Table 7−5 show the 512-byte and 2048-byte EEPROM memory maps.
Table 7−2. 512-Byte EEPROM Memory Map 2.0 Channels
ADDRESS BYTE NUMBER FUNCTION
000h 1 Signature (2Ah) 001h 1 ID byte = 0000 0000
002h 1 MCR 003h−00Bh 9 Mixer left gain 00Ch−014h 9 Mixer right gain 015h−01Ah 2 DRC (ratio, threshold, energyα, attackα, decayα)
01Bh 1 Bass 01Ch 1 Treble
01Dh−022h 6 Volume
031h−03Fh 15 Biquad 0 040h−04Eh 15 Biquad 1 04Fh−05Dh 15 Biquad 2 05Eh−06Ch 15 Biquad 3 06Dh−07Bh 15 Biquad 4 07Ch−08Ah 15 Biquad 5 08Bh−099h 15 Biquad 6
09Ah 1 0 dB/bass
09Bh 1 0 dB/treble 09Ch−0A1h 6 Bass break 0A2h−0A7h 6 Treble break
0A8h−110h 105 Bass delta
111h−179h 105 Treble delta
17Ah−17Fh 6 Bass set point
180h−185h 6 Treble set point
186h−194h 15 Biquad 0 195h−1A3h 15 Biquad 1 1A4h−1B2h 15 Biquad 2 1B3h−1C1h 15 Biquad 3 1C2h−1D0h 15 Biquad 4
1D1h−1DFh 15 Biquad 5
1E0h−1EEh 15 Biquad 6
NOTE: Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.
Left channel
Right channel
7−7
Table 7−3. 512-Byte EEPROM Memory Map 2.1 Channels (with TAS3001)
TAS3002
right and left
TAS3001
right and left
ADDRESS BYTE NUMBER FUNCTION
000h 1 Signature (2Ah) 001h 1 ID byte = 0000 0011
TAS3002
002h 1 MCR 003h−00Bh 9 Mixer left gain 00Ch−014h 9 Mixer right gain 015h−01Ah 6 DRC (ratio, threshold, energyα, attackα, decayα)
01Bh 1 Bass
01Ch 1 Treble 01Dh−022h 6 Volume 031h−03Fh 15 Biquad 0 040h−04Eh 15 Biquad 1
04Fh−05Dh 15 Biquad 2 05Eh−06Ch 15 Biquad 3 06Dh−07Bh 15 Biquad 4 07Ch−08Ah 15 Biquad 5
08Bh−099h 15 Biquad 6
09Ah 1 0 dB/bass
09Bh 1 0 dB/treble
09Ch−0A1h 6 Bass break 0A2h−0A7h 6 Treble break
0A8h−110h 105 Bass delta
111h−179h 105 Treble delta 17Ah−17Fh 6 Bass set point 180h−185h 6 Treble set point 186h−194h 15 Biquad 0 195h−1A3h 15 Biquad 1
1A4h−1B2h 15 Biquad 2 1B3h−1C1h 15 Biquad 3 1C2h−1D0h 15 Biquad 4 1D1h−1DFh 15 Biquad 5 1E0h−1EEh 15 Biquad 6
TAS3001
1EFh 1 MCR 1F0h−1F2h 3 SDIN1 gain 1F3h−1F5h 3 SDIN2 gain 1F6h−1F7h 2 DRC (ratio, threshold, energyα, attackα, decayα)
1F8h 1 Bass 1F9h 1 Treble
1FAh−1FFh 6 Volume
NOTE: In this mode, the TAS3002 and the TAS3001 devices both use the same equalization coefficients for their right and left channels.
Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.
right and left
channel
right and left
channel
7−8
Table 7−4. 2048-Byte EEPROM Memory Map—2.0 Speakers With Multiple Equalizations
Set 0
Set 1
Set 2
Set 3
Set 4
TAS3002 ADDRESS
LEFT BIQUAD
000h 1 Signature (2Ah) 001h 1 1 0 0 0 0 0 1 0
002h 1 MCR 1EFh 003h−00Bh 9/3 Mixer left gain 1F0h−1F2h 00Ch−014h 9/3 Mixer right gain 1F3h−1F5h
015h−019h 6/2 DRC (ratio, threshold, energyα, attackα, decayα) 1F6h−1F7h
01Ah 1 Bass 1F8h
01Bh 1 Treble 1F9h 01Ch−021h 6 Volume 1FAh−1FFh 031h−03Fh 15 Biquad 0 3A4h−3B2h 186h−194h
040h−04Eh 15 Biquad 1 3B3h−3C1h 195h−1A3h 04Fh−05Dh 15 Biquad 2 3C2h−3D0h 1A4h−1B2h 05Eh−06Ch 15 Biquad 3 06Dh−07Bh 15 Biquad 4 07Ch−08Ah 15 Biquad 5 3EFh−3FDh 1D1h−1DFh 08Bh−099h 15 Biquad 6 3FEh−40Ch 1E0h−1EEh 09Ah−185h 236 Bass treble table
200h−20Eh 15 Biquad 0 40Dh−41Bh 5B1h−5BFh 20Fh−21Dh 15 Biquad 1 41Ch−42Ah 5C0h−5CEh 21Eh−22Ch 15 Biquad 2 42Bh−439h 5CFh−5DDh 22Dh−23Bh 15 Biquad 3 23Ch−24Ah 15 Biquad 4 24Bh−259h 15 Biquad 5 458h−466h 5FCh−60Ah 25Ah−268h 15 Biquad 6 467h−475h 60Bh−619h
269h−277h 15 Biquad 0 476h−484h 61Ah−628h 278h−286h 15 Biquad 1 485h−493h 629h−637h
287h−295h 15 Biquad 2 494h−4A2h 638h−646h 296h−2A4h 15 Biquad 3 2A5h−2B3h 15 Biquad 4 2B4h−2C2h 15 Biquad 5 4C1h−4CFh 665h−673h
2C3h−2D1h 15 Biquad 6 4D0h−4DEh 674h−682h
2D2h−2E0h 15 Biquad 0 4DFh−4EDh 683h−691h 2E1h−2EFh 15 Biquad 1 4EEh−4FCh 692h−6A0h 2F0h−2FEh 15 Biquad 2 4FDh−50Bh 6A1h−6AFh 2FFh−30Dh 15 Biquad 3 30Eh−31Ch 15 Biquad 4 31Dh−32Bh 15 Biquad 5 52Ah−538h 6CEh−6DCh 32Ch−33Ah 15 Biquad 6 539h−547h 6DDh−6EBh 33Bh−349h 15 Biquad 0 548h−556h 6ECh−6FAh 34Ah−358h 15 Biquad 1 557h−565h 6FBh−709h
359h−367h 15 Biquad 2 566h−574h 70Ah−718h
368h−376h 15 Biquad 3
377h−385h 15 Biquad 4
386h−394h 15 Biquad 5 593h−5A1h 737h−745h 395h−3A3h 15 Biquad 6 5A2h−5B0h 746h−754h
NUMBER
OF BYTES
FUNCTION CATEGORY
Set 0
Set 1
Set 2
Set 3
Set 4
TAS3002 ADDRESS
RIGHT BIQUAD
3D1h−3DFh 1B3h−1C1h 3E0h−3EEh 1C2h−1D0h
43Ah−448h 5DEh−5ECh 449h−457h 5EDh−5FBh
4A3h−4B1h 647h−655h 4B2h−4C0h 656h−664h
50Ch−51Ah 6B0h−6BEh
51Bh−529h 6BFh−6CDh
575h−583h 719h−727h 584h−592h 728h−736h
TAS3001
NOTE: Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.
7−9
Table 7−5. 2048-Byte EEPROM Memory Map—2.1 Speakers With Multiple Equalizations
Set 0
Set 1
Set 2
Set 3
Set 4
TAS3002 ADDRESS
000h 1 Signature (2Ah) 001h 1 1 0 0 0 0 0 0 1 002h 1 MCR 1EFh
003h−00Bh 9/3 Mixer left gain 1F0h−1F2h
00Ch−014h 9/3 Mixer right gain 1F3h−1F5h
015h−019h 6/2 DRC (ratio, threshold, energyα, attackα, decayα) 1F6h−1F7h
01Ah 1 Bass 1F8h 01Bh 1 Treble 1F9h
01Ch−021h 6 Volume 1FAh−1FFh
031h−03Fh 15 Biquad 0 186h−194h 3A4h−3B2h
040h−04Eh 15 Biquad 1 195h−1A3h 3B3h−3C1h 04Fh−05Dh 15 Biquad 2 1A4h−1B2h 3C2h−3D0h 05Eh−06Ch 15 Biquad 3 06Dh−07Bh 15 Biquad 4 07Ch−08Ah 15 Biquad 5 1D1h−1DFh 3EFh−3FDh
08Bh−099h 15 Biquad 6 1E0h−1EEh 3FEh−40Ch
09Ah−185h 236 Bass treble table
200h−20Eh 15 Biquad 0 5B1h−5BFh 40Dh−41Bh 20Fh−21Dh 15 Biquad 1 5C0h−5CEh 41Ch−42Ah 21Eh−22Ch 15 Biquad 2 5CFh−5DDh 42Bh−439h 22Dh−23Bh 15 Biquad 3 23Ch−24Ah 15 Biquad 4
24Bh−259h 15 Biquad 5 5FCh−60Ah 458h−466h
25Ah−268h 15 Biquad 6 60Bh−619h 467h−475h
269h−277h 15 Biquad 0 61Ah−628h 476h−484h
278h−286h 15 Biquad 1 629h−637h 485h−493h
287h−295h 15 Biquad 2 638h−646h 494h−4A2h
296h−2A4h 15 Biquad 3 2A5h−2B3h 15 Biquad 4 2B4h−2C2h 15 Biquad 5 665h−673h 4C1h−4CFh 2C3h−2D1h 15 Biquad 6 674h−682h 4D0h−4DEh 2D2h−2E0h 15 Biquad 0 683h−691h 4DFh−4EDh 2E1h−2EFh 15 Biquad 1 692h−6A0h 4EEh−4FCh 2F0h−2FEh 15 Biquad 2 6A1h−6AFh 4FDh−50Bh 2FFh−30Dh 15 Biquad 3 30Eh−31Ch 15 Biquad 4 31Dh−32Bh 15 Biquad 5 6CEh−6DCh 52Ah−538h 32Ch−33Ah 15 Biquad 6 6DDh−6EBh 539h−547h
33Bh−349h 15 Biquad 0 6ECh−6FAh 548h−556h
34Ah−358h 15 Biquad 1 6FBh−709h 557h−565h
359h−367h 15 Biquad 2 70Ah−718h 566h−574h
368h−376h 15 Biquad 3
377h−385h 15 Biquad 4
386h−394h 15 Biquad 5 737h−745h 593h−5A1h
395h−3A3h 15 Biquad 6 746h−754h 5A2h−5B0h
NUMBER
OF BYTES
FUNCTION CATEGORY
Set 0
Set 1
Set 2
Set 3
Set 4
TAS3001 ADDRESS
LEFT CHANNEL
1B3h−1C1h 3D1h−3DFh 1C2h−1D0h 3E0h−3EEh
5DEh−5ECh 43Ah−448h
5EDh−5FBh 449h−457h
647h−655h 4A3h−4B1h 656h−664h 4B2h−4C0h
6B0h−6BEh 50Ch−51Ah 6BFh−6CDh 51Bh−529h
719h−727h 575h−583h 728h−736h 584h−592h
TAS3001 ADDRESS
RIGHT CHANNEL
NOTE: Bytes are in the same order as they appear in the I2C register map. The EEPROM address is A0h.
7−10
8 Electrical Characteristics
Power dissipation
8.1 Absolute Maximum Ratings Over Operating Temperature Ranges
Supply voltage range: AVDD −0.3 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DV
−0.3 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range: −0.3 to AV Digital input voltage range: −0.3 to DV Operating free-air temperature, T Storage temperature range, T
DD
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
DD DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds +122°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature from case for 10 seconds +97.8°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (see Note 1) 2000 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Human body model per Method 3015.2 of MIL-STD-833B.
8.2 Recommended Operating Conditions
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V Voltages at analog inputs and outputs and at AV
Supply voltage, AV Supply voltage, DV
Supply current, analog
Supply current, digital
NOTE 2: If the clocks are turned off.
DD
DD
are with respect to ground.
DD
MIN NOM MAX UNIT
3.0 3.3 3.6 V
3.0 3.3 3.6 V Operating 34 mA Power down (see Note 2) 88 µA Operating 47 mA Power down (see Note 2) 942 µA Operating 267 mW Power down (see Note 2) 3.5 mW
8.3 Static Digital Specifications
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V
PARAMETER TEST CONDITIONS MIN MAX UNIT
V V V V
High-level input voltage 2.0 3.6 V
IH
Low-level input voltage −0.3 0.8 V
IL
High-level output voltage IO = −1 mA 2.4 V
OH
Low-level output voltage IO = +4 mA 0.4 V
OL
Input leakage current −10 10 µA Output load capacitance 50 pF
8−1
8.4 ADC Digital Filter
ADC decimation filter (LPF)
ADC high-pass filter (HPF)
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, fS = 48 kHz, 20-bit I2S mode All terms characterized by frequency are scaled with the chosen sampling frequency, f Figure 8−4 for performance curves of the ADC digital filter.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC decimation filter (LPF)
ADC high-pass filter (HPF)
−50
−100
Amplitude − dB
−150
Pass band 0.0 20.0 kHz Pass band ripple ±0.01 dB Stop band 24.1 kHz Stop band attenuation 80 dB Group delay 720 µs Pass band (−3 dB) 0.87 Hz Deviation from linear phase 20 Hz to 20 kHz 1.23 degrees
50
0
. See Figure 8−1 through
S
−200 02 fs4 f
Figure 8−1. ADC Digital Filter Characteristics
0
−20
−40
−60
Amplitude − dB
−80
−100 0
Figure 8−2. ADC Digital Filter Stop-Band Characteristics
0.2 f
s
f − Frequency − Hz
s
6 f
s
0.4 f
s
f − Frequency − Hz
0.6 f
8 f
s
s
10 f
0.8 f
s
s
12 f
s
1 f
s
8−2
0.008
0.006
0.004
0.002
Amplitude − dB
0
−0.002 0
Figure 8−3. ADC Digital Filter Pass-Band Characteristics
0.2
0
−0.2
−0.4
−0.6
Amplitude − dB
−0.8
0.1 f
s
0.2 f
s
f − Frequency − Hz
0.3 f
s
0.4 f
s
0.5 f
s
−1 0
1 f
s
2 f
f − Frequency − Hz
s
3 f
s
4 f
s
Figure 8−4. ADC High-Pass Filter Characteristics
8.5 Analog-to-Digital Converter
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, fS = 48 kHz, 20-bit I2S mode All terms characterized by frequency are scaled with the chosen sampling frequency, f
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNR (EIAJ) A weighted 93 dB Dynamic range −60 dB, 1 kHz 88 dB Signal to (noise + distortion) ratio −1 dB, 1 kHz, 20 Hz to 20 kHz 82 dB Power supply rejection ratio 1 kHz (see Note 3) 50 dB Idle channel tone rejection +110 dB Intermodulation distortion −80 dB ADC crosstalk −93 dB Overall ADC frequency response 20 Hz to 20 kHz ±0.1 dB Gain error 5% Gain matching ±0.02 dB
NOTE 3: Measured with a 50-mV peak sine curve.
.
S
8−3
8.6 Input Multiplexer
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, fS = 48 kHz, 20-bit I2S mode
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input impedance 20 k Crosstalk 85 dB Full-scale input voltage range 1.7 V
8.7 DAC Interpolation Filter
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, fS = 48 kHz, 20-bit I2S mode All terms characterized by frequency are scaled with the normal mode sampling frequency, f Figure 8−6 for performance curves of the DAC digital filter.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Pass band 0.0 20.0 kHz Pass-band ripple ±0.005 dB Stop band 24.1 kHz Stop-band attenuation 28.8 kHz to 3 MHz 75 dB Group delay 700 µs
0
R
−20
. See Figure 8−5 and
S
PP
−40
−60
Amplitude − dB
−80
−100 0f
Figure 8−5. DAC Filter Overall Frequency Characteristics
0.1
0.05
0
Amplitude − dB
−0.05
−0.1
0
s/2
0.1 f
1 f
s
s
2 f
s
f − Frequency − Hz
0.2 f
s
f − Frequency − Hz
3 f
0.3 f
s
s
4 f
0.4 f
s
s
5 f
0.5 f
s
s
8−4
Figure 8−6. DAC Digital Filter Pass-Band Ripple Characteristics
8.8 Digital-to-Analog Converter
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, fS = 48 kHz, input = 0 dB-fS sine wave at 1 kHz
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNR (EIAJ) A weighted 94 99 dB Dynamic range −60 dB, 1 kHz 92 96 dB Signal to (noise + distortion) ratio 0 dB, 1 kHz, 20 Hz to 20 kHz 83 dB Power supply rejection ratio 1 kHz 50 dB Idle channel tone rejection +118 dB Intermodulation distortion −75 dB Frequency response −0.5 +0.5 dB Deviation from linear phase ±1.4 degree DAC crosstalk −96 dB Jitter tolerance 150 ps Full scale, single-ended, output voltage range 1.9 V DC offset −7.0 7.0 mV
8.9 DAC Output Performance Data
TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V The output load resistance is connected through a dc blocking capacitor.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output load resistance 10 k Output load capacitance 25 pF VCOM internal resistance (see Note 4) 1 k VCOM output CLOAD 10 100 µF VRFILT internal resistance (see Note 5) 1 k
NOTES: 4. VCOM may vary during power down.
5. VRFILT must never be used as a voltage reference.
PP
8−5
8.10 I2C Serial Port Timing Characteristics
MIN MAX UNIT
f
(SCL)
t
(buf)
t
(low)
t
(high)
t
h(sta)
t
su(sta)
t
h(dat)
t
su(dat)
t
r
t
f
t
su(sto)
C
NOTE 6: A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL clock frequency 0 100 kHz Bus free time between start and stop 4.7 µs Low period of SCL clock 4.7 µs High period of SCL clock 4.0 µs Hold time repeated start 4.0 µs Setup time repeated start 4.7 20 µs Data hold time (See Note 6) 0 µs Data setup time 250 ns Rise time for SDA and SCL 1000 ns Fall time for SDA and SCL 300 ns Setup time for stop condition 4.0 µs Capacitive load for each bus line 400 pF
(b)
SCL.
PS
P
NOTE: t
SDA
t
(buf)
SCL
is measured from the end of tf to the beginning of tr.
(low)
t
is measured from the end of tr to the beginning of tf.
(high)
Stable
t
h(sta)
Valid
Data Line
t
r
Figure 8−7. I2C Bus Timing
t
Change
of Data
Allowed
h(dat)
t
su(dat)
t
su(sta)
t
su(sto)
t
f
t
h(sta)
8−6
9 System Diagrams
Figure 9−1 and Figure 9−2 show the TAS3002 stereo and 2.1-channel applications, respectively.
+3.3 V
DD
RESET
Analog Out
Analog In
SPDIF
or
USB
EEPROM
NOTE: Items such as the PLL network and power supplies are omitted for clarity.
I2S
I2C
Master
TAS3002
Clock Select Logic
B-T-V-EQ Switches
Figure 9−1. Stereo Application
9−1
Analog In
+3.3 V
t
DD
RESET
Analog Out (To Satellite Amplifiers)
SPDIF
or
USB
EEPROM
Echoes
Switches
on GPIO
NOTE: Items such as the PLL network and power supplies are omitted for clarity.
I2S
I2C
Master
TAS3002
Clock Select Logic
B-T-V-EQ-Sub Vol
SDOUT2
L+R Mix
I2C
Figure 9−2. TAS3002 Device, 2.1 Channels
I2S_OUT
Slave
TAS3001
Address = 6Ah
I2S
PCM1744
Analog Ou
9−2
10 Mechanical Information
The TAS3002 device is packaged in a 48-terminal PFB package. The following illustration shows the mechanical dimensions for the PFB package.
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
37
48
1,05 0,95
0,50
36
0,27 0,17
25
24
13
1
5,50 TYP
7,20
SQ
6,80 9,20
SQ
8,80
12
M
0,08
0,05 MIN
Seating Plane
0,13 NOM
Gage Plane
0,25
0°ā 7°
0,75 0,45
1,20 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
0,08
4073176/B 10/96
10−1
10−2
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