TEXAS INSTRUMENTS TAS3001C Technical data

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Data M anua

March 2004 DAV−Audio Products

SLAS226B

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Contents

Section Title Page

1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Description 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Overview 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Features 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.1 Stereo Digital Audio Processing 1−1. . . . . . . . . . . . . . . . . . . . . .

1.3.2 Interfaces 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.3 Electrical and Physical 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Applications 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.1 Digital Audio Controls 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.2 Equalization 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.3 Loudspeaker Active Crossovers 1−2. . . . . . . . . . . . . . . . . . . . . .

1.5 Functional Block Diagram 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Mixing/Input Scaling 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 High-Precision, Second-Order Biquad Filter Structure 1−4. . . . . . . . . . . .

1.8 Bass and Treble Controls 1−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.9 Soft Volume and True Soft Mute 1−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.10 Reliability and Flexibility of Digital Filtering 1−7. . . . . . . . . . . . . . . . . . . . . .

1.11 Pin Assignments 1−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.12 Pin Functions 1−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.13 Ordering Information 1−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.14 Power Supply 1−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Audio Data Formats 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Serial Audio Interface 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 I

2.1.2 Left-Justified Serial Format 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 Right-Justified Serial Format 2−4. . . . . . . . . . . . . . . . . . . . . . . . .

2.2 LRCLKOUT and SCLKOUT 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Serial Control Interface (I

3.1 I

C Protocol 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Operation 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Write Cycle Example 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 I

3.2.3 Resetting the TAS3001 I

3.2.4 Power-Up Conditions 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.5 I

4 Digital Audio Processor 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Input Mixer Control 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

S Serial Format 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C) 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Timing and Wait Cycles 3−2. . . . . . . . . . . . . . . . . . . . . . . . . .

C Interface 3−3. . . . . . . . . . . . . . . . . .

C Serial Port Timing 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

4.2 Biquad Block 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Filter Coefficients 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Volume Control Functions 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 Soft Volume Update 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2 Software Soft Mute 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Tone Controls 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1 Treble Control 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.2 Bass Control 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.3 Frequency Dependence of Treble and Bass Controls 4−2. . . .

5 Device Operation 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Device Initialization 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.1 Reset 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2 Device Power On and System Reset 5−1. . . . . . . . . . . . . . . . . .

5.1.3 Fast Load 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Power Consumption 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Power Down and Start-Up 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Electrical Characteristics 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Absolute Maximum Ratings Over Operating Free-Air

Temperature Range 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Recommended Operating Conditions 6−1. . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Power Consumption 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Static Digital Specifications 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Measured Audio Performance for Some Typical Examples 7−1. . . . . . . . . . .

8 Using the TAS3001 in a System 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 TAS3001 Applications 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 Measurement-Based Speaker Correction 8−2. . . . . . . . . . . . . . . . . . . . . . .

8.3 Sound-Based Speaker Correction 8−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 Loudspeaker Equalization Example 8−3. . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5 Speaker Correction and Equalization 8−5. . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6 The TAS3001 Can Implement Nearly Any Second-Order IIR Filter 8−5.

8.7 Converting Analog Filters to Digital 8−7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 Automatic Loudspeaker Equalizer (ALE) 9−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 Automatic Generation of Equalization Filters Given a Measurement 9−1

9.2 Automatic Approximation of an Equalization Curve 9−1. . . . . . . . . . . . . . .

9.3 Manual Filter Design 9−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4 Conversion of Decimal Filter Coefficients to the TAS3001 Format 9−1. .

9.5 Editing of TAS3001 File Format 9−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6 Examples of the Filter Types Available From ALE 2.1 9−1. . . . . . . . . . . .

10 FilterBuilder and FilterMaker 10−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Software Interface A−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1 Main Control Register (MCR) A−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B Mechanical Information B−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

1−1 TAS3001 Signal Flow 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−2 Examples of High-Pass Filters 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−3 Examples of Equalization Filters 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−4 Bass and Treble Shelves 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−5 Multiple Filter Response 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−6 Combed Response of the Multiple Filters 1−5. . . . . . . . . . . . . . . . . . . . . . . . . .

1−7 Bass and Treble Filters 1−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−8 TAS3001 Pin Location Diagram 1−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 I 2−2 For Right/Left Justified, I

2−3 Left-Justified Serial Format 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 Right-Justified Serial Format 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 Master Mode 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 Slave Mode 2−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 Typical I

3−2 Write Cycle Example 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 Wait Cycle Example 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 I2C Serial Port Timing 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 Cascaded Biquad Filters 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 Audio Processing Architecture 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 Main Control Register (MCR) 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 Power-Down Timing 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−3 Start-Up Timing 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1 Typical TAS3001 Connection 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1 Audio Performance Measurement System 7−1. . . . . . . . . . . . . . . . . . . . . . . . .

7−2 Audio Performance Test Filters 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−1 TAS3001 as a System Equalizer 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−2 TAS3001 as a Crossover and Equalizer 8−2. . . . . . . . . . . . . . . . . . . . . . . . . . .

8−3 Typical Small Loudspeaker Response 8−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−4 Preparation for Equalization 8−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−5 After Equalization 8−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−7 Equalization Filters 8−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8−8 Individual Filters 8−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

S-Compatible Serial Format 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

S, Left/Left Justified Serial Protocols 2−3. . . . . . . .

C Data Transfer Sequence 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations (Continued)

8−9 Combined Response 8−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−1 Equalization Filters 9−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−2 High- and Low-Pass Filters 9−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−3 Treble and Bass Shelf Filters 9−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9−4 Notch Filters 9−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2−1 Serial Interface Input Options 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Serial Interface Output Options 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 I 3−2 TAS3001 I

3−3 Write Cycle Example 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 I

4−1 Bass Control Corner Frequencies 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 Treble Control Corner Frequencies 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1 Audio Filter Performance 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−1 Register Map A−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−2 Main Control Register (MCR) A−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−3 Main Control Register (MCR) Description A−2. . . . . . . . . . . . . . . . . . . . . . . . . .

A−4 Volume Gain Values A−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−5 Treble Control Register A−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−6 Bass Control Register A−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−7 Mixer1 and Mixer2 Gain Values A−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Protocol Definitions 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Address 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Wait States 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Introduction

1.1 Description

The TAS3001 is a high-quality, fixed-function, 32-bit digital audio processor. This device contains a number of built-in processing functions including mixing/scaling of two digital inputs, bass and treble controls, six cascaded stereo high-precision, limit-cycle-free, second-order IIR filters, soft volume, and soft mute.

These functions can be controlled by specifying the desired operating parameters using the I The TAS3001 architecture preserves high-quality audio by using a 32-bit data path, 24 × 32-bit multiplies, and up to

56 bits of precision for some internal calculations. By using 24-bit filter coefficients, the TAS3001 can implement practically any second-order IIR filter with outstanding fidelity.

1.2 Overview

The TAS3001 is a 32-bit audio signal processor that provides mixing of two digital inputs and digital parametric equalization. In addition, this device provides high-quality, soft digital volume, bass, and treble controls. All control parameters are uploaded through the I

The TAS3001 has four audio processing blocks as shown in Figure 1−1.

• Two digital stereo audio inputs that can be scaled and mixed prior to processing.

• Parametric EQ that consists of six cascaded independent second-order IIR filters for each of the left and

right independent channels. Each filter has five 24-bit coefficients that can be configured into many different filter functions, such as band-pass, high-pass, low-pass, shelves, notch, all-pass, high-/low-pass with shelf, etc.

C port from an outside MCU.

C interface.

• Digital bass and treble controls

• Digital soft volume and mute

The TAS3001 device uses a system clock that is generated by the internal phase-locked loop (PLL). An external master clock (MCLK) of 256 times the sampling frequency provides the reference clock for the PLL.

The TAS3001 device supports several serial data formats (I 16, 18, or 20. The sampling frequencies (f

) that are supported include 32 kHz, 44.1 kHz, 48 kHz and 96 kHz.

S, left justified, right justified) with data word lengths of

1.3 Features

1.3.1 Stereo Digital Audio Processing

• Supports nine serial data formats. Receive and transmit serial data formats may be different.

• Programmable two-input digital mixer

• Programmable six-band digital parametric EQ

• Programmable digital bass and treble controls

• Programmable digital volume control with soft mute

• 108-dB dynamic range

• Sample rates from 32 kHz to 96 kHz

1.3.2 Interfaces

• Two serial digital input channels

• Single serial digital output channel

• Serial I

C control channel

1−1

1.3.3 Electrical and Physical

• Single 3.3-V power supply

• 28-pin PW package

• Low-power standby

1.4 Applications

1.4.1 Digital Audio Controls

The TAS3001 can be used to provide a high-quality digital system control of volume, bass, treble, and parametric equalization.

1.4.2 Equalization

The TAS3001 can be used to perform parametric equalization to correct the frequency response of loudspeakers or microphones. The TAS3001 corrects the response by applying filters to compensate for the response irregularities of the transducers.

1.4.3 Loudspeaker Active Crossovers

The TAS3001 can be used to implement an active crossover for multi-way loudspeaker systems.

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1.5 Functional Block Diagram

SDA

SCL

CS1 CS2

SDIN1 SDIN2

LRCLK

SCLK

MCLK

4 5

28 1

6 7 10 11 9

I2C

Slave

Address

Select

Serial Audio

Input

Port

Clock

Generator

PLL

2-Channel

Stereo Mixer

Internal Clocks

6 Biquad

Filters

System Control

Treble/

Bass

Volume

23 24

SDOUT

LRCLKOUT SCLKOUT

Figure 1−1. TAS3001 Signal Flow

Figure 1−1 shows the signal flow from the inputs (SDIN1 and SDIN2) though each processing stage to the output (SDOUT) where it is passed to an external DAC, digital amplifier, or other subsequent digital data processing stage.

Each of these audio processing functions is discussed in more detail in the following sections.

1.6 Mixing/Input Scaling

The TAS3001 is equipped with a dual-input stereo digital mixer. Thi s m ixe r pe rmi ts eac h i nput to sc ale d ( −∞ to +18 dB) independently. A stereo sum of the scaled results is produced.

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1.7 High-Precision, Second-Order Biquad Filter Structure

The TAS3001 has six cascaded biquad filters for the left and right channels to permit parametric equalization and filtering of the input signal. Each biquad is able to specify a wide variety of first- and second-order filter types, including high-pass, low-pass, band-pass, band-block, notch, and all-pass filter types. Examples of a few of the filters that can be implemented by the TAS3001 shapes are illustrated in Figure 1−2 though Figure 1−6.

ATTENUATION

FREQUENCY

−5

Attenuation − dB

−10

−15

−20 100 1k 10k

f − Frequency − Hz

Figure 1−2. Examples of High-Pass Filters

The biquad structure is of the form:

ATTENUATION

FREQUENCY

Attenuation − dB

−5

−10

−15 100 1k 10k

f − Frequency − Hz

Figure 1−3. Examples of Equalization Filters

H(z) +

b0) b1Z–1) b2Z

1 ) a1Z–1) a2Z

–2

Coefficients are downloaded to the TAS3001 registers in 4.20 format.

1−4

ATTENUATION

FREQUENCY

−2

Attenuation − dB

−4

−6

−8

−10 100 1k 10k

f − Frequency − Hz

−5

−10

Attenuation − dB

−15

−20

−25

−30 10 1k 10k1 100

f − Frequency − Hz

Figure 1−4. Bass and Treble Shelves Figure 1−5. Multiple Filter Response

The TAS3001 provides a zero-input limit-cycle-free second-order IIR filtering structure that implements a direct form I filter structure. This architecture preserves high-quality audio by using a 32-bit data path, 24 × 32-bit multiplies, and 56 bits of precision for some internal calculations. By using 24-bit filter coefficients, the TAS3001 can implement practically any second-order IIR filter with outstanding fidelity.

Texas Instruments has several tools that provide a powerful and flexible means to develop applications using the TAS3001. Chapter 8 provides examples of how the TAS3001 can be used to meet various system needs.

ATTENUATION

FREQUENCY

−5

−10

Attenuation − dB

−15

−20

−25

−30 10 1k 10k1 100

f − Frequency − Hz

Figure 1−6. Combed Response of the Multiple Filters

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1.8 Bass and Treble Controls

The TAS3001 has bass and treble controls that can be adjusted dynamically. These controls can be adjusted throughout their entire range of 18 dB to –18 dB without experiencing any pops, clicks, or other audible artifacts. This permits the user to have a listening experience much like what is experienced when adjusting high-quality analog controls.

Figure 1−7 shows the response for the bass and treble filters plotted at 3-dB intervals for 44.1-kHz sample-rate data.

ATTENUATION

FREQUENCY

−5

Attenuation − dB

−10

−15

−20 100 1k 10k

f − Frequency − Hz

Figure 1−7. Bass and Treble Filters

1.9 Soft Volume and True Soft Mute

The TAS3001 contains a Texas Instruments proprietary soft volume update. This allows a smooth and pleasant-sounding change from one volume level to another over the entire range of volume (18 dB to mute). The

volume is adjustable by downloading a 4.20 gain coefficient through the I

C interface.

Mute is implemented by loading all zeros in the volume control register. This causes the volume to ramp down over 2048 samples to a final output of zero (−∞ dB).

1.10 Reliability and Flexibility of Digital Filtering

Digital filtering provides outstanding consistency, reliability, and flexibility. Once a digital filter is designed and tested in the system, it continues to perform in the same manner without change. Because digital filters are computed, their performance is exceedingly consistent and does not change due to variations in component matching, tolerances, environmental conditions, aging, or the effects of moisture and dust. Analog filters, however, are affected by all of these. The performance of analog filters can be improved, in part, by using high-quality precision components but this comes with a higher comparable cost.

One of the greatest strengths of a digital filter is its flexibility. Each filter is completely specified by five 24-bit coefficients. By modifying the value of one or more of the filter coefficients, both the filter value and filter type are changed. In a system, these modifications produce different crossover curves, different equalization curves, different sound effects (by changing the relative phase of the left and right loudspeakers) or different user graphical equalization settings.

1−6

Attempting similar changes in an analog filter would require component changes and potentially a new circuit layout. The flexibility of digital filtering provides a particular advantage to digital equalization. Because of its programmability, a single design using digital filtering can provide a wide range of filtering functions. As a result, this one design can span a number of applications.

For a product that is in production, digital filtering can permit equalization changes with minimal cost impact because of this programmability.

One concern about digital filters is that some implementations have been prone to zero-input limit cycles. This is a condition where the filter oscillates at a low level when no signal is presented. In a digital audio system, this condition may present itself as a tone or low-level noise. The TAS3001 has a patent-pending technique to combat this problem.

1.11 Pin Assignments

PW PACKAGE

(TOP VIEW)

CS2

SDIN1 SDIN2

SDOUT

MCLK

LRCLK

SCLK

_PLL

CAP_PLL

NC − No internal connection

SDA

SCL

2 3 4 5 6 7 8 9 10 11 12 13 14

CS1

RESERVED

SCLKOUT

LRCLKOUT

RESET

POWERDOWN

16 15

RESERVED

Figure 1−8. TAS3001 Pin Location Diagram

1−7

1.12 Pin Functions

I/O

DESCRIPTION

TERMINAL

NAME NO.

AVDD_PLL 13 I Analog power supply for the PLL AVSS_PLL 12 I Analog ground for the PLL CAP_PLL 14 I C1 = 1500 pF // R1 = 27 Ω + C2 = 0.068 µF (recommended) CS1 28 I I2C address bit A0; low = 0, high = 1 CS2 1 I I2C address bit A1; low = 0, high = 1 DV

LRCLK 10 I I2S left/right clock sampling frequency (fs) LRCLKOUT 23 O MCLK 9 I Master clock (256 x fs) NC POWERDOWN 16 I Powerdown input

RESET 19 I Reset, high = normal operation, low = reinitialize the device RESERVED 15, 27 Reserved − digital ground for normal operation SCL 5 I/O Slave serial I2C clock SCLK 11 I Shift clock (bit clock)

SCLKOUT 24 O SDA 4 I/O Slave serial I2C data

SDIN1 6 I Serial audio data input one SDIN2 7 I Serial audio data input two SDOUT 8 O Serial audio data output

NOTE: Reset and other control functions require MCLK to be running. The system reset operation is a synchronous operation and requires a

minimum of four MCLK cycles to reset the device.

3 I Digital power supply 2 I Digital ground

LRCLK generated from input MCLK (usually 256 fs) − normally routed on PCB to pin 10 (LRCLK) as input fs sample clock.

17, 18, 20−22,

25, 26

Reserved − No connection for normal operation

SCLK generated from input MCLK (usually 256 fs) − normally routed on PCB to pin 11 (SCLK) as input 64 fs bit clock.

1.13 Ordering Information

0°C to 70°C TAS3001CPW

PACKAGE

SMALL OUTLINE (PW)

1.14 Power Supply

• Digital supply voltage—DVDD, DVSS of 3.3 V

• Analog supply voltage—AV

NOTE: AV

1−8

and AVSS for the PLL are derived from the digital supply and digital ground.

DD−

PLL, AV

PLL of 3.3 V

SS−

2 Audio Data Formats

2.1 Serial Audio Interface

The TAS3001 operates in digital audio slave mode only. The TAS3001 supports three serial audio data formats: I2S, left-justified, and right-justified. Data word lengths of 16, 18, and 20 bits are supported.

Data is input into SDIN1 and SDIN2 under the influence of the master clock (MCLK), left/right clock (LRCLK), and shift clock (SCLK) inputs.

Data is output on the SDOUT pin under the influence of the master clock (MCLK) input plus the left/right clock (LRCLKOUT) and shift clock (SCLKOUT) outputs. LRCLKOUT and SCLKOUT are generated from the MCLK input (usually at 256 × f the input 64 × f

The TAS3001 device is compatible with 10 different serial interfaces. Available interface options are I right-justified, and left-justified. Table 2−1 and Table 2−2 indicate how the 10 options are selected using the I and the main control register (MCR, I with SCLK at 64 × f

Figure 2−1 through Figure 2−4 illustrate the relationship between the SCLK, LRCLK, and the serial data input and output protocol options.

). Typically these are routed on the PCB to LRCLK (as the input fs sample clock) and SCLK (as

bit clock).

C address 01h). All serial interface options at either 16, 18, or 20 bits operate

. The 16-bit mode, left-justified, can operate at 32 × fs or 64 × fs.

Table 2−1. Serial Interface Input Options

MODE

0 0 00 00 16-bit, left-justified, 32 × f 1 1 00 00 16-bit, left-justified, 64 × f 2 1 01 00 16-bit, right-justified, 64 × f 3 1 10 00 16-bit, I2S, 64 × f 4 1 00 01 18-bit, left-justified, 64 × f 5 1 01 01 18-bit, right-justified, 64 × f 6 1 10 01 18-bit, I2S, 64 × f 7 1 00 10 20-bit, left-justified, 64 × f 8 1 01 10 20-bit, right-justified, 64 × f 9 1 10 10 20-bit, I2S, 64 × f

MCR BIT 6SCMCR BITS 3−2

F(1,0)

MCR BITS 1−0

W(1,0)

SERIAL INTERFACE

SDIN1, SDIN2

s s

Table 2−2. Serial Interface Output Options

MODE

MCR BIT 6SCMCR BITS 5−4

E(1,0)

MCR BITS 1−0

W(1,0)

SERIAL INTERFACE

SDOUT

s s

C bus

2−1

2.1.1 I2S Serial Format

The following are characteristics of this protocol:

• LRCLK is the left/right clock. The left channel is transmitted when LRCLK is low. The right channel is transmitted when LRCLK is high.

• SDIN is sampled with the rising edge of SCLK.

• SDOUT is transmitted on the falling edge of SCLK.

• LRCK must have a 50% duty cycle.

SCLK

LRCLK = f

SDIN

SDOUT

MSB

MSBX

Left Channel Right Channel

Figure 2−1. I2S-Compatible Serial Format

2.1.1.1 I2S Signal Timing

PARAMETER MIN TYP MAX UNIT

c(SCLK)

d(SLR)

d(SDOUT)

su(SDIN)

h(SDIN)

NOTE 1: Maximum of 50-pF external load on SDOUT.

SCLK frequency 6.144 MHz SCLK rising to LRCLK edge 20 ns SDOUT valid from SCLK falling (see Note 1) 1/(256 × fs) +10 ns SDIN setup before SCLK rising edge 20 ns SDIN hold after SCLK rising edge 100 ns LRCLK 32 44.1/48 96 kHz Duty cycle 50%

LSB

MSBX

LSB

2−2

SCLK

c(SCLK)

r(SCLK)

f(SCLK)

LRCLK

SDOUT1 SDOUT2 SDOUT0

SDIN1 SDIN2

d(SDOUT)

su(SDIN)

d(SLR)

h(SDIN)

d(SLR)

Figure 2−2. For Right/Left Justified, I2S, Left/Left Justified Serial Protocols

2.1.2 Left-Justified Serial Format

The following are characteristics of this protocol:

• LRCLK is the left/right clock. The left channel is transmitted when LRCLK is high. The right channel is transmitted when LRCLK is low.

• The SDIN data is justified to the leading edge of LRCLK.

• The MSBs are transmitted at the same time as the LRCLK edge and captured at the very next rising edge

of SCLK.

• Serial data is sampled into the device on the rising edge of SCLK.

• Serial data is transmitted out of the device on the falling edge of SCLK.

• SCLK = 32 × LRCLK (32 × fs SCLK is only supported for 16-bit data) or 64 × LRCLK

• In this mode, LRCLK does not have to be a 50% duty-cycle clock. The number of bits used in the interface

sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.

SCLK

LRCLK = f

SDIN

SDOUT

MSB

LSB

Left Channel Right Channel

MSB

LSB

Figure 2−3. Left-Justified Serial Format

2−3

2.1.3 Right-Justified Serial Format

The following are characteristics of this protocol:

• LRCLK is the left/right clock. The left channel is transmitted when LRCLK is high. The right channel is transmitted when LRCLK is low.

• The SDIN data (recorded data) is justified to the trailing edge of the LRCLK.

• Serial data is sampled on the rising edge of SCLK.

• Serial data is transmitted on the falling edge of SCLK.

• In this mode, LRCLK does not have to be a 50% duty-cycle clock. The number of bits used in the interface

sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.

SCLK

LRCLK = f

SDIN1

SDOUT

MSBX

Left Channel Right Channel

LSB

MSBX

LSB

Figure 2−4. Right-Justified Serial Format

2.2 LRCLKOUT and SCLKOUT

The digital audio processor and on-chip logic are sequenced using an internal system clock that is derived from MCLK (master clock). Also derived from MCLK are the LRCLKOUT and SCLKOUT signals that provide clocks to the TAS3001 and other devices in the system.

The TAS3001 allows multiple system clocking schemes. In Figure 2−5, the TAS3001 provides system clocks (LRCLK and SCLK) to other parts of the system. In Figure 2−6, a system master other than the TAS3001, provides system clocks (LRCLK and SCLK) to the TAS3001.

2−4

+ 39 hidden pages

TEXAS INSTRUMENTS TAS3001C Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual