The TAS2505 is a low power digital input speaker amp with support for 24-bit digital I2S data mono
playback.
In addition to driving a speaker amp upto 4-Ω, the device also features a mono headphone driver and a
programmable digital-signal processing block. The digital audio data format is programmable to work with
popular audio standard protocols (I2S, left/right-justified) in master, slave, DSP and TDM modes. The
programmable digital-signal processing block can support Bass boost, treble, or EQ functions. An on-chip
PLL provides the high-speed clock needed by the digital signal-processing block. The volume level can be
controlled by register control. The audio functions are controlled using the I2C™ serial bus or SPI bus. The
device includes an on-board LDO that runs off the speaker power supply to handle all internal device
analog and digital power needs. The included POR as power-on-resetcircuit reliably resets the device into
its default state so no external reset is required at normal usage; however, the device does have a reset
pin for more complex system initialization needs. The device also includes two analog inputs for mixing
and muxing in both speaker and headphone analog paths.
Description
Figure 1-1. Simplified Block Diagram
The device can cover operations from 8kHz mono playback to mono 96kHz DAC playback, making it ideal
for portable battery-powered audio and telephony applications. The playback path offers signal processing
blocks for filtering and effects, flexible mixing of analog input signals as well as programmable volume
controls. The voltage supply range for theTAS2505 for analog is 1.5V–1.95V, and for digital it is
1.65V–1.95V. To ease system-level design, a low-dropout regulator (LDO) is integrated to generate the
appropriate analog supply from input voltages ranging from 2.7V to 5.5V. Digital I/O voltages are
supported in the range of 1.1V–3.6V. The required internal clock of the TAS2505 can be derived from
multiple sources, including the MCLK, BCLK or GPIO/DOUT pins or the output of the internal PLL, where
the input to the PLL again can be derived from the MCLK, BCLK or GPIO/DOUT pins. Although using the
internal, fractional PLL ensures the availability of a suitable clock signal, it is not recommended for the
lowest power settings. The PLL is highly programmable and can accept available input clocks in the range
of 512kHz to 50MHz.
The device is available in the 4mm × 4mm, 24-pin QFN package.
Only a small number of digital pins are dedicated to a single function; whenever possible, the digital pins
have a default function, and also can be reprogrammed to cover alternative functions for various
applications.
The fixed-function pins are RST LDO_SEL and the SPI_SEL pin, which are HW control pins. Depending
on the state of SPI_SEL, the two control-bus pins SCL/SSZ and SDA/MOSI are configured for either I2C or
SPI protocol.
Other digital IO pins can be configured for various functions via register control. An overview of available
functionality is given in Section 2.1.3.
2.1.2 Analog Pins
Analog functions can also be configured to a large degree. For minimum power consumption, analog
blocks are powered down by default. The blocks can be powered up with fine granularity according to the
application needs.
Chapter 2
SLAU472–February 2013
TAS2505 Application
2.1.3 Multifunction Pins
Table 2-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).
: The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.
(2)S(2)
: The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.
(3)S(3)
: The GPIO/DOUT pin can drive the PLL and Codec Clock inputs simultaneously.
(4)
D: Default Function
(5)
E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has
been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)
To configure the settings seen in Table 2-1, please see the letter-number combination in Table 2-2 for the
appropriate registers to modify. In Table 2-2, the letter/number combination represents the row and the
column number from Table 2-1 in bold type.
Please be aware that more settings may be necessary to obtain a full interface definition matching the
application requirement (see Page 0, Register 25 to 33).
The TAS2505 features a mono audio DAC. It supports a wide range of analog interfaces to support
different headsets such as 16-Ω to 200-Ω impedance and analog line outputs. TheTAS2505 can drive a
speaker upto 4-Ω impedance.
•Analog inputs AINR and AINL, which can be used to pass-through or mix analog signals to output
stages
•Analog outputs class-D speaker driver and headphone/lineout driver providing output capability for the
DAC, AINR, AINL, or a mix of the three
2.3.1 Analog Inputs AINL and AINR
AINL (pin 3 or C2) and AINR (pin 4 or B2) are inputs to Mixer P and Mixer M along with the DAC output.
Also AINL and AINR can be configured inputs to HP driver. Page1 / register 12 provides control signals for
determining the signals routed through Mixer P, Mixer M and HP driver. Input of Mixer P can be
attenuated by Page1 / register 24, input of Mixer M can be attenuated by Page1 / register 25 and input of
HP driver can be attenuated by Page1 / register 22. Also AINL and AINR can be configured to a monaural
differential input with use Mixer P and Mixer M by Page1 / register 12 setting. All the options can be
viewed in the functional block diagram, Figure 2-6.
2.4Audio DAC and Audio Analog Outputs
The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital
delta-sigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is
between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated
within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include
mono headphone and lineout and mono class-D speaker outputs. Because the TAS2505 contains a mono
DAC, it inputs the mono data from the left channel, the right channel, or a mix of the left and right
channels as [(L + R) ÷ 2], selected by page 0, register 63, bits D5–D4. See Figure 1-1 for the signal flow.
2.4.1 DAC
The TAS2505 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of the
mono DAC consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter,
multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide
enhanced performance at low sampling rates through increased oversampling and image filtering, thereby
keeping quantization noise generated within the delta-sigma modulator and observed in the signal images
strongly suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize
power dissipation and performance, the TAS2505 allows the system designer to program the
oversampling rates over a wide range from 1 to 1024 by configuring page 0, register 13 and page 0 /
register 14. The system designer can choose higher oversampling ratios for lower input data rates and
lower oversampling ratios for higher input data rates.
The TAS2505 DAC channel includes a built-in digital interpolation filter to generate oversampled data for
the delta-sigma modulator. The interpolation filter can be chosen from three different types, depending on
required frequency response, group delay, and sampling rate.
DAC power up is controlled by writing to page 0, register 63, bit D7 for the mono channel. The monochannel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D7.
The DAC path of the TAS2505 features many options for signal conditioning and signal routing:
•Digital volume control with a range of -63.5 to +24dB
•Mute function
In addition to the standard set of DAC features the TAS2505 also offers the following special features:
•Digital auto mute
•Adaptive filter mode
2.4.1.1DAC Processing Blocks
The TAS2505 implements signal-processing capabilities and interpolation filtering via processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they
may use and which interpolation filter is applied.
The choices among these processing blocks allows the system designer to balance power conservation
and signal-processing flexibility. Table 2-3 gives an overview of all available processing blocks of the DAC
channel and their properties. The resource-class column gives an approximate indication of power
consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog
power consumption of the drivers (AVDD) may differ.
The signal-processing blocks available are:
•First-order IIR
•Scalable number of biquad filters
The processing blocks are tuned for common cases and can achieve high image rejection or low group
delay in combination with various signal-processing effects such as audio effects and frequency shaping.
The available first-order IIR and biquad filters have fully user-programmable coefficients.
2.4.1.2DAC Processing Blocks – Signal Chain Details
2.4.1.2.1 Three Biquads, Filter A
Figure 2-1. Signal Chain for PRB_P2
2.4.1.2.2 Six Biquads, First-Order IIR, Filter A or B
Figure 2-2. Signal Chain for PRB_P1 and PRB_P3
Audio DAC and Audio Analog Outputs
2.4.1.3DAC User-Programmable Filters
Depending on the selected processing block, different types and orders of digital filtering are available. Up
to six biquad sections are available for specific processing blocks.
The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If
adaptive filtering is chosen, the coefficient banks can be switched in real time.
When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed
for either read or write.
However, the TAS2505 offers an adaptive filter mode as well. Setting page 8, register 1, bit D2 = 1 turns
on double buffering of the coefficients. In this mode, filter coefficients can be updated through the host and
activated without stopping and restarting the DAC. This enables advanced adaptive filtering applications.
In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC
is running and adaptive filtering mode is turned on, setting page 44, register 1, bit D0 = 1 switches the
coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the switch occurs. At
the same time, page 44, register 1, bit D1 toggles.
The flag in page 44, register 1, bit D1 indicates which of the two buffers is actually in use.
Page 44, register 1, bit D1 = 0: buffer A is in use by the DAC engine; bit D1 = 1: buffer B is in use.
While the device is running, coefficient updates are always made to the buffer not in use by the DAC,
regardless of the buffer to which the coefficients have been written.
No0NoneC1, buffer AC1, buffer A
No0NoneC1, buffer BC1, buffer B
Yes0Buffer AC1, buffer AC1, buffer B
Yes0Buffer AC1, buffer BC1, buffer B
Yes1Buffer BC1, buffer AC1, buffer A
Yes1Buffer BC1, buffer BC1, buffer A
Page 44, Reg 1, Bit D1I2C Writes toWill Updates
The user-programmable coefficients C1 to C70 for the DAC processing blocks are defined on pages 44 to
46 for buffer A and pages 62 to 64 for buffer B.
The coefficients of these filters are each 24-bit, 2s-complement format, occupying three consecutive 8-bit
registers in the register space. Specifically, the filter coefficients are in 1.23 (one dot 23) format with a
range from –1.0 (0x800000) to 0.99999988079071044921875 (0x7FFFFF) .
2.4.1.3.1 First-Order IIR Section
The IIR is of first order and its transfer function is given by
The frequency response for the first-order IIR section with default coefficients is flat.
As part of the PowerTune strategy, the analog properties of the DAC are adjusted. As a consequence, the
full-scale signal swing achieved at the headphone and line outputs must be adjusted. Please see Table 2-
9 for the proper gain compensation values across the different combinations.
Table 2-9. DAC Gain vs. PowerTune Modes
DAC PowerTune ModePowerTune ModeHeadphone Gain
Control
Page 1,Register 3, Bits (D4-CM = 0.75V, Gain forCM = 0.9V, Gain for
D2)375mV
000PTM_P3, PTM_P400
001PTM_P244
010PTM_P11414
2.4.2.2DAC Digital-Volume Control
The DAC has a digital volume-control block which implements programmable gain. Each channel has an
independent volume control that can be varied from 24 dB to –63.5 dB in 0.5-dB steps. The mono-channel
DAC volume can be controlled by writing to page 0, register 65, bits D7–D0. DAC muting and setting up a
master gain control to control the mono channel is done by writing to page 0, register 64, bits D3. The
gain is implemented with a soft-stepping algorithm, which only changes the actual volume by 0.125 dB per
input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be
slowed to one step per two input samples by writing to page 0, register 63, bits D1–D0. Note that the
default source for volume-control level settings is controlled by register writes to page 0, register 65.
During soft-stepping, the host does not receive a signal when the DAC has been completely muted. This
may be important if the host must mute the DAC before making a significant change, such as changing
sample rates. In order to help with this situation, the device provides a flag back to the host via a readonly register, page 0, register 38, bit D4 for the mono channel. This information alerts the host when the
part has completed the soft-stepping, and the actual volume has reached the desired volume level. The
soft-stepping feature can be disabled by writing to page 0, register 63, bits D1–D0.
If soft-stepping is enabled, the CODEC_CLKIN signal should be kept active until the DAC power-up flag is
cleared. When this flag is cleared, the internal DAC soft-stepping process is complete, and
CODEC_CLKIN can be stopped if desired. (The analog volume control can be ramped down using an
internal oscillator.)
Audio DAC and Audio Analog Outputs
output swing at500mV
RMS
0dB full scale input0dB full scale input
output swing at
RMS
2.4.3 Interrupts
Some specific events in the TAS2505, which may require host-processor intervention, can be used to
trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The
TAS2505 has two defined interrupts, INT1 and INT2, that can be configured by programming page 0,
register 48 and page 0, register 49. A user can configure interrupts INT1 and INT2 to be triggered by one
or many events, such as:
•Overcurrent condition in headphone drivers/speaker drivers
•Data overflow in the DAC processing blocks and filters
Each of these INT1 and INT2 interrupts can be routed to output pin GPIO. These interrupt signals can
either be configured as a single pulse or a series of pulses by programming page 0, register 48, bit D0
and page 0, register 49, bit D0. If the user configures the interrupts as a series of pulses, the events
trigger the start of pulses that stop when the flag registers in page 0, register 42 and page 0, register 44
are read by the user to determine the cause of the interrupt.
The digital filter coefficients must be programmed through the control interface. All digital filtering for the
DAC signal path must be loaded into the RAM before the DAC is powered on. (Note that default
ALLPASS filter coefficients for programmable biquads are located in boot ROM. The boot ROM
automatically loads the default values into the RAM following a hardware reset (toggling the RST pin) or
after a software reset. After resetting the device, loading boot ROM coefficients into the digital filters
requires 100 μs of programming time. During this time, reading or writing to page 8 through page 15 for
updating DAC filter coefficient values is not permitted. (The DAC should not be powered up until after all
of the DAC configurations have been done by the system microprocessor.)
2.4.5 Updating DAC Digital Filter Coefficients During PLAY
When it is required to update the DAC digital filter coefficients during play, care must be taken to avoid
click and pop noise or even a possible oscillation noise. These artifacts can occur if the DAC coefficients
are updated without following the proper update sequence. The correct sequence is shown in Figure 2-5.
The values for times listed in Figure 2-5 are conservative and should be used for software purposes.
There is also an adaptive mode, in which DAC coefficients can be updated while the DAC is on. For
details, see Section 2.4.1.3.
Audio DAC and Audio Analog Outputs
Figure 2-5. Example Flow For Updating DAC Digital Filter Coefficients During Play
The TAS2505 has four digital mixing blocks. Each mixer can provide either mixing or multiplexing of the
digital audio data. The first mixer/multiplexer can be used to select input data for the mono DAC from left
channel, right channel, or (left channel + right channel) / 2 mixing. This digital routing can be configured by
writing to page 0, register 63, bits D5–D4.
2.4.7 Analog Audio Routing
The TAS2505 has the capability to route the DAC output to either the headphone or the speaker output. If
desirable, both output drivers can be operated at the same time while playing at different volume levels.
The TAS2505 provides various digital routing capabilities, allowing digital mixing or even channel
swapping in the digital domain. All analog outputs other than the selected ones can be powered down for
optimal power consumption.
2.4.7.1Analog Output Volume Control
The output volume control can be used to fine-tune the level of the mixer amplifier signal supplied to the
headphone driver or the speaker driver. This architecture supports separate and concurrent volume levels
for each of the four output drivers. This volume control can also be used as part of the output pop-noise
reduction scheme. This feature is available even if the DAC is powered down.
2.4.7.2Headphone Analog Output Volume Control
For the headphone output, the analog volume control has a range from 0 dB to –78 dB in 0.5-dB steps for
most of the useful range plus mute, as shown in Table 2-10. This volume control includes soft-stepping
logic.
Changing the analog volume for the headphone is controlled by writing to page 1, register 22, bits D6–D0.
Routing the signal from the output of the analog volume control to the input of the headphone power
amplifier via Mixer P and Mixer M is done by writing to page 1, register 12, bit D2.
The analog volume-control soft-stepping time is based on the setting in page 0, register 63, bits D1–D0.
2.4.7.3Class-D Speaker Analog Output Volume Control
For the speaker outputs, the analog volume control has a range from 0 dB to –78 dB in 0.5-dB steps for
most of the useful range plus mute, as seen in Table 2-10. The implementation includes soft-stepping
logic.
Routing the DAC output signal to the analog volume control via Mixer P and Mixer M is done by writing to
page 1, register 12, bits D3. Changing the analog volume for the speaker is controlled by writing to page 1
/ register 46, bits D6–D0.
The analog volume-control soft-stepping time is based on the setting in page 0, register 63, bits D1–D0.
2.4.8 Analog Outputs
Various analog routings are supported for playback. All the options can be viewed in the functional block
diagram, Figure 2-6.
Note: If only use analog input from AINL or, and AINR to
HPOUT as P1/R12/D1=1 or, and P1/R12/D0=1, need to
set P1/R24/D7=1 as HP Out mixer forcedly powered-up.
Mixer P
P1/R12/D1
P1/R12/D0
P1/R12/D2
P1/R12/D7
P1/R12/D6
P1/R12/D5
P1/R12/D4
P1/R12/D3
P1/R22
HP Volume Control
Audio DAC and Audio Analog Outputs
2.4.8.1Headphone Drivers
The TAS2505 features a mono headphone driver (HPOUT) that can deliver up to 28 mW channel, at 1.8-V
supply voltage, into a 16-Ω load. The headphones are used in a single-ended configuration where an accoupling (dc-blocking) capacitor is connected between the device output pins and the headphones. The
headphone driver also supports 32-Ω and 10-kΩ loads without changing any control register settings.
The headphone driver can be configured to reduce the power consumption in the half drive ability mode
by writing 1 to page 1, register 10, bits D2 = 1, also in this mode the headphone driver can support
lineout-drive as well.
The common-mode voltage is set to ≤ AVDD/2.
The headphone driver can be powered on by writing to page 1, register 9, bit D5. The HPOUT output
driver gain can be controlled by writing to page 1 / register 16 bits D5–D0, and it can be muted by writing
to page 1, register 16, bit D6.
The TAS2505 has a short-circuit protection feature for the headphone drivers, which is always enabled to
provide protection. The output condition of the headphone driver during short circuit can be programmed
by writing to page 1, register 11, bit D1. If D1 = 0 when a short circuit is detected, the device limits the
maximum current to the load. If D1 = 1 when a short circuit is detected, the device powers down the
output driver. The default condition for headphones is the current-limiting mode. For a short circuit on the
channel, the output is disabled and a status flag is provided as read-only bits on page 0 / register 45,
bit D5. If shutdown mode is enabled, then as soon as the short circuit is detected, page 0, register 9,
bit D5 (for HPOUT) clears automatically. Next, the device requires a reset to re-enable the output stage.
Resetting can be done in two ways. First, the device master reset can be used, which requires either
toggling the RST pin or using the software reset. If master reset is used, it resets all of the registers.
Second, a dedicated headphone power-stage reset can also be used to re-enable the output stage, and
that keeps all of the other device settings. The headphone power stage reset is done by setting page 1,
register 9, bit D5 for HPOUT. If the fault condition has been removed, then the device returns to normal
operation. If the fault is still present, then another shutdown occurs. Repeated resetting (more than three
times) is not recommended, as this could lead to overheating.
The TAS2505 has an integrated class-D mono speaker driver (SPKP/SPKM) capable of driving an 8-Ω or
4-Ω differential load. The speaker driver can be powered directly from the battery supply (2.7 V to 5.5 V)
on the SPKVDD pins; however, the voltage (including spike voltage) must be limited below the absolutemaximum voltage of 6 V.
The speaker driver is capable of supplying 800 mW per channel with a 3.6-V power supply. Through the
use of digital mixing, the device can connect one or both digital audio playback data channels to either
speaker driver; this also allows digital channel swapping if needed.
The class-D speaker driver can be powered on by writing to page 1, register 45, bit D1. The class-D
output-driver gain can be controlled by writing to page 1, register 48, bits D6–D4, and it can be muted by
writing to page 1, register 48, bit D6 - D4 = 000.
The TAS2505 has a short-circuit protection feature for the speaker drivers that is always enabled to
provide protection. If the output is shorted, the output stage shuts down on the overcurrent condition.
(Current limiting is not an available option for the higher-current speaker driver output stage.) In case of a
short circuit, the output is disabled and a status flag is provided as a read-only bit on page 0, register 46,
bit D7.
If shutdown occurs due to an overcurrent condition, then the device requires a reset to re-enable the
output stage. Resetting can be done in two ways. First, the device master reset can be used, which
requires either toggling the RST pin or using the software reset. If master reset is used, it resets all of the
registers. Second, a dedicated speaker power-stage reset can be used that keeps all of the other device
settings. The speaker power-stage reset is done by setting page 1, register 45, bit D1 for SPKP and
SPKM. If the fault condition has been removed, then the device returns to normal operation. If the fault is
still present, then another shutdown occurs. Repeated resetting (more than three times) is not
recommended, as this could lead to overheating.
To minimize battery current leakage, the SPKVDD voltage level should not be less than the AVDD
voltage level.
The TAS2505 has a thermal protection (OTP) feature for the speaker driver which is always enabled to
provide protection. If the device is overheated, then the output stops switching. When the device cools
down, the output resumes switching. An overtemperature status flag is provided as a read-only bit on
page 0, register 45, bit D7. The OTP feature is for self-protection of the device. If die temperature can be
controlled at the system/board level, then overtemperature does not occur.
Audio DAC and Audio Analog Outputs
2.4.9 Audio Output-Stage Power Configurations
After the device has been configured (following a RST) and the circuitry has been powered up, the audio
output stage can be powered up and powered down by register control.
These functions soft-start automatically. By using these register controls, it is possible to turn all four
stages on at the same time without turning two of them off.
See Table 2-11 for register control of audio output stage power configurations.
Table 2-11. Audio Output Stage Power Configurations
Audio Output PinsDesired FunctionPage 1 / Register, Bit Value
The TAS2505 has a built-in LDO which can generate the analog supply (AVDD) also the digital supply
(DVDD) from input voltage range of 2.7 V to 5.5 V with high PSRR. If combined power supply current is
50 mA or less, then this LDO can deliver power to both analog and digital power supplies. If the only
speaker power supply is present and LDO Select pin is enabled, the LDO can power up without requiring
other supplies. This LDO requires a minimum dropout voltage of 300 mV and can support load currents up
to 50 mA. For stability reasons the LDO requires a minimum decoupling capacitor of 1 µF (±50%) on the
analog supply (AVDD) pin and the digital supply (DVDD) pin. If use this LDO output voltage for the digital
supply (DVDD) pin, the analog supply (AVDD) pin connected to the digital supply (DVDD) externally is
required.
The LDO is by default powered down for low sleep mode currents and can be enabled driving the
LDO_SEL pin to SPKVDD (Speaker power supply). When the LDO is disabled the AVDD pin is tri-stated
and the device AVDD needs to be powered using external supply. In that case the DVDD pin is also tristated and the device DVDD needs to be powered using external supply. The output voltage of this LDO
can be adjusted to a few different values as given in the Table 2-12. A Circuit Configuration with Internal
LDO is shown in Section 1.3
2) POR_RTB resets I C, I S, Signal Processing and all registers.
22
3) SW_
registers but not digital interfaces
RSTB from register bit resets only the Signal Processing
and all
.
POR_RSTB
After
15
SCLs
1.8V
Default
IOVDD
DVDD
POR_RSTB
time
time
time
SCLK
www.ti.com
2.4.11 POR
TAS2505 has a POR (Power On Reset) function as shown Figure 2-7. This function insures that all
registers are automatically set to defaults when a proper power up sequence is executed. The function
consume approximately 35uA from the DVDD so if needed this can be disabled by page 1, register 1, bit
D3 = 1.
The following paragraphs are intended to guide a user through the steps necessary to configure the
TAS2505.
Step 1
The system clock source (master clock) and the targeted DAC sampling frequency must be identified.
Depending on the targeted performance, the decimation filter type (A or B) and DOSR value can be
determined:
•Filter A should be used for 48-kHz high-performance operation; DOSR must be a multiple of 8.
•Filter B should be used for up to 96-kHz operations; DOSR must be a multiple of 4.
In all cases, DOSR is limited in its range by the following condition:
2.8 MHz < DOSR x DAC_fS < 6.2 MHz(3)
Based on the identified filter type and the required signal processing capabilities, the appropriate
processing block can be determined from the list of available processing blocks (PRB_P1, PRB_P2 and
PRB_P3).
Based on the available master clock, the chosen DOSR and the targeted sampling rate, the clock divider
values NDAC and MDAC can be determined. If necessary, the internal PLL can add a large degree of
flexibility.
In summary, CODEC_CLKIN (derived directly from the system clock source or from the internal PLL)
divided by MDAC, NDAC, and DOSR must be equal to the DAC sampling rate DAC_fS. The
CODEC_CLKIN clock signal is shared with the DAC clock generation block.
CODEC_CLKIN = NDAC × MDAC × DOSR × DAC_fS(4)
NDAC and MDAC can be chosen independently in the range of 1 to 128. In general, NDAC should be as
large as possible as long as the following condition can still be met:
MDAC × DOSR / 32 ≥ RC(5)
RC is a function of the chosen processing block and is listed in Table 2-3.
The common-mode voltage setting of the device is determined by the available analog power supply. This
common-mode (input common-mode) value is common across the ADC, DAC and analog bypass path.
The output common-mode setting is determined by the available analog power supplies (AVdd and ) and
the desired output-signal swing.
At this point, the following device specific parameters are known:
PRB_Rx, DOSR, NDAC, MDAC, input and output common-mode values.
If the PLL is used, the PLL parameters P, J, D and R are determined as well.
Step 2
Setting up the device via register programming:
The following list gives a sequence of items that must be executed in the time between powering the
device up and reading data from the device:
1. Define starting point:
(a) Power up applicable external power supplies
(b) Set register page to 0
(c) Initiate SW reset
2. Program Clock Settings
(a) Program PLL clock dividers P, J, D and R (if PLL is necessary)
(b) Power up PLL (if PLL is necessary)
(c) Program and power up NDAC
(d) Program and power up MDAC
(e) Program OSR value
(f) Program I2S word length if required (16, 20, 24, or 32 bits)
(g) Program the processing block to be used
(h) Micellaneous page 0 controls
At this point, at the latest, the analog power supply must be applied to the device
3. Program Analog Blocks
(a) Set register page to 1
(b) Disable coarse AVDD generation
(c) Enable Master Analog Power Control
(d) Program common-mode voltage
(e) Program headphone-specific de-pop settings (if a headphone driver is used)
(f) Program routing of DAC output to the output amplifier (headphone and lineout or speaker)
(g) Unmute and set gain of output drivers
(h) Power up output drivers
4. Apply waiting time determined by the de-pop settings and the soft-stepping settings of the driver gain
or poll page 1, register 63
5. Power up DAC
(a) Set register page to 0
(b) Power up DAC channels and set digital gain
(c) Unmute digital volume control
Detailed examples can be found from Section 4.0.7 to Section 4.0.12.
2.5PowerTune
PowerTune
The TAS2505features PowerTune, a mechanism to balance power-versus-performance tradeoffs at the
time of device configuration. The device can be tuned to minimize power dissipation, to maximize
performance, or to an operating point between the two extremes to best fit the application.
2.5.1 PowerTune Modes
2.5.1.1DAC - Programming PTM_P1 to PTM_P4
On the playback side, the performance is determined by a combination of register settings and the audio
data word length applied. For the highest performance setting (PTM_P4), an audio-data word length of 20
bits is required, while for the modes PTM_P1 to PTM_P3 a word length of 16 bits is sufficient.
PTM_P1PTM_P2PTM_P3PTM_P4
Pg 1, Reg 3, D(4:2)0x20x10x00x0
Audio Data word length16 bits16 bits16 bits20 or more bits
Pg 0, Reg 27, D(5:4)0x000x000x000x1, 0x2, 0x3
2.5.1.2Processing Blocks
The choice of processing blocks, PRB_P1 to PRB_P3 for playback, also influences the power
consumption. In fact, the numerous processing blocks have been implemented to offer a choice between
power-optimization and configurations with more signal-processing resources.
The tables in this section give recommendations for various DAC PowerTune modes. Typical performance
and power-consumption numbers for line-out signals are listed.
All measurements were taken with the PLL turned off, no signal is present, and the DAC modulator is fully
running. PowerTune modes which are not supported are marked with an ‘X’.
To consider Speaker output power consumption on the TAS2505, the tables in this section to be may
useful to know the power consumption for each power rail. The tables shows selected as representable
combination of PRB mode and PTM mode.
All measurements were taken with the PLL turned off, no signal is present, and the DAC modulator is fully
running.
To consider Headphone output power consumption on the TAS2505, the tables in this section to be may
useful to know the power consumption for each power rail. The tables shows selected as representable
combination of PRB mode and PTM mode.
All measurements were taken with the PLL turned off, no signal is present, and the DAC modulator is fully
running.
The TAS2505 supports a wide range of options for generating clocks for the DAC sections as well as
interface and other control blocks as shown in . The clocks for the DAC require a source reference clock.
This clock can be provided on a variety of device pins, such as the MCLK, BCLK, or GPIO pins. The
source reference clock for the codec can be chosen by programming the CODEC_CLKIN value on page
0, register 4, bits D1–D0. The CODEC_CLKIN can then be routed through highly-flexible clock dividers
shown in to generate the various clocks required for the DAC and the Digital Effects section. In the event
that the desired audio clocks cannot be generated from the reference clocks on MCLK, BCLK, or GPIO,
the TAS2505 also provides the option of using the on-chip PLL which supports a wide range of fractional
multiplication values to generate the required clocks. Starting from CODEC_CLKIN, the TAS2505 provides
several programmable clock dividers to help achieve a variety of sampling rates for the DAC and clocks
for the Digital Effects sections.
The DAC modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC channel,
these clocks must be enabled by configuring the NDAC and MDAC clock dividers (page 0, register 11,
bit D7 = 1 and page 0, register 12, bit D7 = 1). When the DAC channel is powered down, the device
internally initiates a power-down sequence for proper shut-down. During this shutdown sequence, the
NDAC and MDAC dividers must not be powered down, or else a proper low-power shutdown may not take
place. The user can read back the power-status flag at page 0, register 37, bit D7 and page 0, register 37,
bit D3. When both the flags indicate power-down, the MDAC divider may be powered down, followed by
the NDAC divider.
In general, all the root clock dividers should be powered down only after the child clock dividers have been
powered down for proper operation.
The TAS2505 also has options for routing some of the internal clocks to the GPIO output pin to be used
as general-purpose clocks in the system. The feature is shown in Figure 2-10.
In the mode when TAS2505 is configured to drive the BCLK pin (page 0, register 27, bit D3 = 1), it can be
driven as a divided value of BDIV_CLKIN. The division value can be programmed in page 0, register 30,
bits D6–D0 from 1 to 128 (see Figure 2-9). The BDIV_CLKIN can itself be configured to be one of
DAC_CLK (DAC DSP clock) or DAC_MOD_CLK by configuring the BDIV_CLKIN multiplexer in page 0,
register 29, bits D1-D0. Additionally, a general-purpose clock can be driven out on GPIO.
This clock can be a divided-down version of CDIV_CLKIN. The value of this clock divider can be
programmed from 1 to 128 by writing to page 0, register 26, bits D6–D0. The CDIV_CLKIN can itself be
programmed as one of the clocks among the list shown in Figure 2-10. This can be controlled by
programming the multiplexer in page 0, register 25, bits D2–D0.
ClockDVDD ≥ 1.65 V
CODEC_CLKIN≤ 110 MHz
DAC_CLK≤ 49.152 MHz
DAC_MOD_CLK6.758 MHz
DAC_f
BDIV_CLKIN55 MHz
CDIV_CLKIN100 MHz when M is odd
Figure 2-10. General-Purpose Clock Output Options
Table 2-14. Maximum TAS2505 Clock Frequencies
S
0.192 MHz
110 MHz when M is even
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2.6.1 PLL
For lower power consumption, it is best to derive the internal audio processing clocks using the simple
dividers. When the input MCLK or other source clock is not an integer multiple of the audio processing
clocks, then it is necessary to use the on-board PLL. The TAS2505 fractional PLL can be used to
generate an internal master clock used to produce the processing clocks needed by the DAC and Digital
Effects. The programmability of this PLL allows operation from a wide variety of clocks that may be
available in the system.
The PLL input supports clocks varying from 512 kHz to 20 MHz and is register programmable to enable
generation of required sampling rates with fine resolution. The PLL can be turned on by writing to page 0 /
register 5, bit D7. When the PLL is enabled, the PLL output clock PLL_CLK is given by the following
equation:
where
R = 1, 2, 3, ..., 16 (page 0 / register 5, default value = 1)
J = 1, 2, 3, …, 63, (page 0 / register 6, default value = 4)
D = 0, 1, 2, …, 9999 (page 0 / register 7 and 8, default value = 0)
P = 1, 2, 3, …, 8 (page 0 / register 5, default value = 1)
The PLL can be turned on via page 0, register 5, bit D7. The variable P can be programmed via page 0,
register 5, bits D6–D4. The variable R can be programmed via page 0, register 5, bits D3–D0. The
variable J can be programmed via page 0, register 6, bits D5–D0. The variable D is 14 bits and is
programmed into two registers. The MSB portion can be programmed via page 0, register 7, bits D5–D0,
and the LSB portion is programmed via page 0, register 8, bits D7–D0. For proper update of the D-divider
value, page 0, register 7 must be programmed first, followed immediately by page 0, egister 8. Unless the
write to page 0, register 8 is completed, the new value of D does not take effect.
When the PLL is enabled, the following conditions must be satisfied.
•When the PLL is enabled and D = 0, the following conditions must be satisfied for PLL_CLKIN:
In the TLV320AIC3256, the PLL_CLK supports a wide range of output clock, based on register settings
and power-supply conditions.
CLOCK Generation and PLL
(8)
(11)
Table 2-15. PLL_CLK Frequency Range
AVDDPLL ModeMin PLL_CLKMax PLL_CLK
≥1.5V075110
≥1.65V075130
≥1.80V075140
Page 0, Reg 4, D6frequency (MHz)frequency (MHz)
190119
190130
190150
The PLL can be powered up independently from the ADC and DAC blocks, and can also be used as a
general purpose PLL by routing its output to the GPIO output. After powering up the PLL, PLL_CLK is
available typically after 10ms. The PLL output frequency is controlled by J.D and R dividers
The D-divider value is 14-bits wide and is controlled by 2 registers. For proper update of the D-divider
value, Page 0, Register 7 must be programmed first followed immediately by Page 0, Register 8. Unless
the write to Page 0, Register 8 is completed, the new value of D will not take effect
The clocks for codec and various signal processing blocks, CODEC_CLKIN can be generated from MCLK
input, BCLK input, GPIO input or PLL_CLK (Page 0, Register 4, Bit D1 to D0) ).
If the CODEC_CLKIN is derived from the PLL, then the PLL must be powered up first and powered down
last.
Audio data is transferred between the host processor and the TAS2505 via the digital audio data serial
interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data
options, support for I2S or PCM protocols, programmable data-length options, a TDM mode for
multichannel operation, flexible master/slave configurability for each bus clock line, and the ability to
communicate with multiple devices within a system directly.
The audio bus of the TAS2505 can be configured for left- or right-justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM
mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by
configuring page 0, register 27, bits D5–D4. In addition, the word clock and bit clock can be independently
configured in either master or slave mode for flexible connectivity to a wide variety of processors. The
word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a
square-wave signal. The frequency of this clock corresponds to the maximum of the selected DAC
sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in master
mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider
in page 0, register 30 (see ). The number of bit-clock pulses in a frame may need adjustment to
accommodate various word lengths as well as to support the case when multiple TAS2505 may share the
same audio bus.
The TAS2505 also includes a feature to offset the position of start of data transfer with respect to the word
clock. This offset can be controlled in terms of number of bit clocks and can be programmed in page 0,
register 28.
The TAS2505 also has the feature of inverting the polarity of the bit clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode
of audio interface chosen. This can be configured via page 0, register 29, bit D3.
By default, when the word clocks and bit clocks are generated by the TAS2505, these clocks are active
only when the DAC is powered up within the device. This is done to save power. However, it also supports
a feature when both the word clocks and bit clocks can be active even when the codec in the device is
powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when
word clocks or bit clocks are used in the system as general-purpose clocks.
2.7.1.1Right-Justified Mode
The audio interface of the TAS2505 can be put into right-justified mode by programming page 0, register
27, bits D7–D6 = 10. In right-justified mode, the LSB of the left channel is valid on the rising edge of the
bit clock preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the
rising edge of the bit clock preceding the rising edge of the word clock.
Digital Audio and Control Interface
Figure 2-11. Timing Diagram for Right-Justified Mode
For right-justified mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data.
The audio interface of the TAS2505 can be put into left-justified mode by programming page 0, register
27, bits D7–D6 = 11. In left-justified mode, the MSB of the right channel is valid on the rising edge of the
bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid on the
rising edge of the bit clock following the rising edge of the word clock.
Figure 2-12. Timing Diagram for Left-Justified Mode
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Figure 2-13. Timing Diagram for Left-Justified Mode With Offset = 1
Figure 2-14. Timing Diagram for Left-Justified Mode With Offset = 0 and Inverted Bit Clock
For left-justified mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
2.7.1.3I2S Mode
The audio interface of the TAS2505 can be put into I2S mode by programming page 0, register 27, bits
D7–D6 = to 00. In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock
after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising
edge of the bit clock after the rising edge of the word clock.
Figure 2-17. Timing Diagram for I2S Mode With Offset = 0 and Bit Clock Inverted
For I2S mode, the number of bit clocks per channel should be greater than or equal to the programmed
word length of the data. Also the programmed offset value should be less than the number of bit clocks
per frame by at least the programmed word length of the data.
2.7.1.4DSP Mode
The audio interface of the TAS2505 can be put into DSP mode by programming page 0, register 27, bits
D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the left-channel
data first and immediately followed by the right-channel data. Each data bit is valid on the falling edge of
the bit clock.
Figure 2-16. Timing Diagram for I2S Mode With Offset = 2
Figure 2-19. Timing Diagram for DSP Mode With Offset = 1
Figure 2-20. Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted
For DSP mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
2.7.1.5Primary and Secondary Digital Audio Interface Selection
The audio serial interface on the TAS2505 has I/O control to allow communication with two independent
processors for audio data. The processors can communicate with the device one at a time. This feature is
enabled by register programming of the various pin selections.
Digital Audio and Control Interface
Figure 2-21. Audio Serial Interface Multiplexing
The secondary audio interface uses multifunction pins. For an overview on multifunction pins please see
Section 2.1.3 Table 2-1 and Table 2-2 illustrates possible audio interface routing. The multifunction pins
SCLK and MISO are only available in I2C communication mode. This multiplexing capability allows the
TAS2505 to communicate with two separate devices with independent I2S/PCM busses, one at a time.
2.7.2 Control Interface
The TAS2505 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SEL pin. For SPI, SPI_SEL should be tied high; for I2C, SPI_SEL should be tied low. It is
not recommended to change the state of SPI_SEL during device operation.
The TAS2505 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is
driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously,
there is no driver contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the
other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under
the direction of the master. Some I2C devices can act as masters or slaves, but the TAS2505 can only act
as a slave device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data, and the SCL signal provides the clock.
All data is transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line
is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is 0, while a HIGH
indicates the bit is 1).
Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on the SCL line
clocks the SDA bit into the receiver shift register.
The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master
reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the
data line.
Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When
communication is taking place, the bus is active. Only master devices can start communication on the bus.
Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes
state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A
START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP
condition is when the clock line is HIGH and the data line goes from LOW to HIGH.
After the master issues a START condition, it sends a byte that selects the slave device for
communication. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit
address to which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for
details.) The master sends an address in the address byte, together with a bit that indicates whether it
wishes to read from or write to the slave device.
Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an
acknowledge bit. When a master has finished sending a byte (8 data bits) to a slave, it stops driving SDA
and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW.
The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished
reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to clock the
bit. (Remember that the master always drives the clock line.)
A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is
not present on the bus, and the master attempts to address it, it will receive a not-acknowledge because
no device is present at that address to pull the line LOW.
When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When
a START condition is issued while the bus is active, it is called a repeated START condition.
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The TAS2505 can also respond to and acknowledge a general call, which consists of the master issuing a
command with a slave address byte of 00h. This feature is disabled by default, but can be enabled via
page 0, register 34, bit D5.
For a I2C register write, if the master does not issue a STOP condition, then the device enters autoincrement mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental
register.
Similarly, for a I2C register read, after the device has sent out the 8-bit data from the addressed register, if
the master issues a ACKNOWLEDGE, the slave takes over control of SDA bus and transmit for the next 8
clocks the data of the next incremental register.
Digital Audio and Control Interface
Figure 2-22. I2C Write
Figure 2-23. I2C Read
2.7.2.2SPI Digital Interface
In the SPI control mode,the TAS2505 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO,
SDA/MOSI=MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI
control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host
processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor)
generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices
(such as the TAS2505) depend on a master to start and synchronize transmissions. A transmission begins
when initiated by an SPI master.The byte from the SPI master begins shifting in on the slave MOSI pin
under the control of the master serial clock(driven onto SCLK). As the byte shifts in on the MOSI pin, a
byte shifts out on the MISO pin to the master shif tregister.
The TAS2505 interface is designed so that with a clock-phase bit setting of 1 (typical microprocessor SPI
control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on
the first serial clock edge. The SSZ pin can remain low between transmissions; however, the TAS2505
only interprets the first 8 bits transmitted after the falling edge of SSZ as a command byte, and the next 8
bits as a data byte only if writing to a register. Reserved register bits should be written to their default
values. The TAS2505 is entirely controlled by registers. Reading and writing these registers is
accomplished by an 8-bit command sent to the MOSI pin of the part prior to the data for that register. The
command is structured as shown in Table 2-18. The first 7 bits specify the register address which is being
written or read, from 0 to 127 (decimal). The command word ends with an R/W bit, which specifies the
direction of data flow on the serial bus. In the case of a register write, the R/W bit should be set to 0. A
second byte of data is sent to the MOSI pin and contains the data to be written to the register. Reading of
registers is accomplished in similar fashion. The 8-bit command word sends the 7-bit register address,
followed by R/W bit = 1 to signify a register read is occurring. The 8-bit register data is then clocked out of
the part on the MISO pin during the second 8 SCLK clocks in the frame.
Figure 2-24. SPI Timing Diagram for Register Write
Figure 2-25. SPI Timing Diagram for Register Read
2.8Power Supply
The TAS2505 integrates a large amount of digital and analog functionality, and each of these blocks can
be powered separately to enable the system to select appropriate power supplies for desired performance
and power consumption. The device has separate power domains for digital IO, digital core, analog core,
analog input, headphone driver, and speaker drivers. If desired, all of the supplies (except for the supplies
for speaker drivers, which can directly connect to the battery) can be connected together and be supplied
from one source in the range of 1.65 to 1.95V. Individually, the IOVDD voltage can be supplied in the
range of 1.1V to 3.6V. For improved power efficiency, the digital core power supply can range from 1.26V
to 1.95V. The analog core supply can either be derived from the internal LDO accepting an SPKVDD
voltage in the range of 2.7V to 5.5V, or the AVDD pin can directly be driven with a voltage in the range of
1.5V to 1.95V. The speaker driver voltages (SPKVDD) can range from 2.7V to 5.5V.
•IOVDD
42
The IOVDD pin supplies the digital IO cells of the device. The voltage of IOVDD can range from 1.1 to
3.6V and is determined by the digital IO voltage of the rest of the system.
•DVDD
This pin supplies the digital core of the device. Lower DVDD voltages cause lower power dissipation. If
efficient switched-mode power supplies are used in the system, system power can be optimized using
low DVDD voltages. the full clock range is only supported with DVDD in the range of 1.65 to 1.95V.
This pin supply the analog core of the device and the headphone amplifier of the device. The analog
core voltage (AVDD) should be in the range of 1.5 to 1.95V for specified performance. For AVDD
voltages above 1.8V, the internal common mode voltage can be set to 0.9V (Page 1, Register 10, D6 =
0, default) resulting in 500mVrms full-scale voltage internally. For analog voltages below 1.8V, the
internal common mode voltage should be set to 0.75V (Page 1, Register 10, D6 = 1), resulting in
375mVrms internal full scale voltage.
NOTE: At powerup, PLL and HP Level Shifters powered down to save leakage current issue when
DVDD is powered up and AVDD is powered down. This powered down must be powered up
by writing Page 1, Reg 2, D3 = 0 at the time AVDD is applied, either from internal LDO or
through external LDO.
•SPKVDD
This pin supply the Class-D speaker driver of the device. The speaker supply voltages should be in the
range of 2.7 to 5.5V for specified performance. This pin also can be an input supply for the internal
LDO. More detail on the internal LDO, please refer to Section 2.4.10. Note that, even if the integrated
speaker drivers are not utilized on the device, these supplies should still be connected (typically to
battery voltage) and at a greater or equal voltage to all the other power supplies.
2.8.1 System Level Considerations
While there is flexibility in supplying the device through multiple options of power supplies, care must be
taken to stay within safe areas when going to standby and shutdown modes. In summary, the lowest
shutdown current is achieved when all supplies to the device are turned off, implying that all settings must
be reapplied to the device after bringing the power back up. In order to retain settings in the device, the
SPKVDD, the DVDD voltage and either internally or externally the AVDD voltage also must be maintained.
Power Supply
2.8.1.1All Supplies from Single Voltage Rail with using the internal LDO (2.75V to 5.5V)
The device can be powered directly from a single of from 2.75V to 5.5V rail through the SPKVDD
(Speaker power supply) pin. During operation the AVDD LDO is activated via the LDO_SEL pin to connect
the SPKVDD pin. Also in this case, the AVDD pin as the LDO output must be connected to the DVDD pin
externally.
2.8.1.1.1 Standby Mode
To put the device in standby mode, the LDO bandgap (Page 1, Register 1, D1 = 0) must stay on, and all
other blocks powered down. This state results in a standby current of approximately 100uA from the
SPKVDD supply at 5V. In standby mode, the device responds quickly to playback requests.
2.8.1.1.2 Shutdown Mode
To shut down the device, the external supply as the SPKVDD supply can be turned off completely.
2.8.1.2Supply from Dual Voltage Rails (2.75V to 5.5V and 1.8V)
If a single 1.8V rail is used for the AVDD supply and the DVDD supply, generating the 1.8V from a higher
battery voltage via a DC-DC converter results in good system-level efficiency. The 1.8V rail connected to
the DVDD pin can also be connected to the AVDD pin. The device operates with this connection, but the
achievable performance is a function of the voltage ripple typically found on DCDC converter outputs. To
achieve specified performance, an external low-input-voltage 1.6V LDO must be connected between the
1.8V rail and the AVDD input. During operation, the LDO is deactivated via the LDO_SEL pin to connect
the SPKVSS pin.
2.8.1.2.1 Standby Mode
To put the device in standby mode, the SPKVDD supply and both 1.8V voltages (AVDD and DVDD) must
stay on, all other blocks should be powered down. This state results in standby current of approximately
1.5μA from the AVDD supply. In standby mode the device responds very quickly to playback requests.
To shut down the device, the external supplies can be turned off completely. If the 1.8V rail cannot be
turned off, the PLL and HP Level Shifters must be powered down (Page 1, Register 2, D3 = 1), the LDO
bandgap must be powered down (Page 1, Register 1, D1 = 1), power down the POR circuit (Page 1,
Register 1, D3 = 1) and the Master Reference must be powered down (Page 1, Register 1, D4 = 0).This
state results in a device shutdown current < 1.5μA.
2.8.1.3Other Supply Options
There are other options to power the device. Apply the following rules:
•During normal operation all supply pins must be connected to a supply (via internal LDO or external).
•Whenever the LDO supply is present,
•Power Supplies:
– The SPKVDD supply must be present as well
– The DVDD supply must be present as well
– If the AVDD supply is not present, then the PLL and HP Level Shifters must be powered down
(Page 1, Register 2, D3 = 1) and the Master Reference must be powered down (Page 1, Register
1, D4 = 0). Also all other blocks should be powered down.
2.9Device Special Functions
2.9.1 Interrupts
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Some specific events in the TAS2505 which may require host processor intervention, can be used to
trigger interrupts to the host processor. This avoids polling the status-flag registers continuously. The
TAS2505 has two defined interrupts; INT1 and INT2 that can be configured by programming Page 0,
Register 48 and 49. A user can configure the interrupts INT1 and INT2 to be triggered by one or many
events such as
•Over-current condition in headphone driver
•Data Overflow in AC Processing Blocks and Filters
Each of these INT1 and INT2 interrupts can be routed to output pins like GPIO/DOUT and MISO by
configuring the respective output control registers in Page 0, Register 52, 53 and 55. These interrupt
signals can either be configured as a single pulse or a series of pulses by programming Page 0, Register
48, D(0) and Page 0, Register 49, D(0). If the user configures the interrupts as a series of pulses, the
events will trigger the start of pulses that will stop when the flag registers in Page 0, Register 42 and 44
are read by the user to determine the cause of the interrupt.
Powered up PLL and HP Level Shifters
(Write þ0ÿ to Page 0, Reg 2, D3)
Device Initialization
The requirements of the application circuit determine device setup details such as clock generation, power
sources, references voltage, and special functions that may add value to the end application. Example
device setups are described in the next chapter.
3.1Power On Sequence
There are two recommended power sequence possible for TAS2505:
1. Speaker Supplies, then Digital Supplies, then Analog Supplies
2. Speaker Supplies, then Digital and Analog Supplies
The first power on sequence is useful if the end system uses separate analog and digital supplies. This is
useful to improve the efficiency of the digital rails by using a DC/DC converter, while keeping the analog
supplies clean by using a low-dropout regulator(s) (LDO). While it is recommended to separate analog
and digital supplies, if all the 1.8 V supplies (analog and digital) must be tied together, the second power
sequence can be utilized and this sequence can adopt in case of using the internal LDO.
3.1.1 Power On Sequence 1 – Separate Digital and Analog Supplies
Chapter 3
SLAU472–February 2013
Figure 3-1 shows a timing diagram for the case where all supplies are provided separately. If the depicted
sequence should be used.
Figure 3-1. Analog Supply provided after Digital Supply
Powered up PLL and HP Level Shifters
(Write þ0ÿ to Page 0, Reg 2, D3)
Power On Sequence
SPKVDD should be provided first. Next, IOVDD should be provided, and DVDD can be provided at the
same time as IOVDD. Since, by default, the PLL and HP Level Shifters which work from the DVDD rail to
the AVDD rail is powered down so that even if rising up AVDD is delayed from rising up DVDD, the
shifters can help the leakage currents from DVDD to AVDD. After RST is released (or a software reset is
performed), no register writes should be performed within 1 ms.
Table 3-1. Power Supply Timing Parameters
ParameterMinimumTypicalMaximumComments
t
S-I
t
I-D
t
D-A
t
D-R
t
R-P
0Time between SPKVDD is provided and IOVDD is provided.
0Time between IOVDD is provided and DVDD is provided.
0Time between DVDD is provided and AVDD is provided.
10 ns
1 ms
Time between DVDD (and IOVDD) is provided and reset can
be released.
Time between release of the reset and when registers can be
written (that is, Powered up PLL and HP Level Shifters).
3.1.2 Power On Sequence 2 – Shared 1.8 V Analog Supply to DVDD
If desired, the analog supply of AVDD could also be supplied at the same time as DVDD if the one supply
is from the internal LDO or is external. This is shown in the Figure 3-2.
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Figure 3-2. Digital and Analog 1.8 V Supplies provided Together
After RST is released (or a software reset is performed), no register writes should be performed within 1
ms.
0Time between SPKVDD is provided and IOVDD is provided.
0
10 ns
1 ms
3.2Device Initialization
3.2.1 Reset by RST pin and POR
The TAS2505 internal logic must be initialized to a known condition for proper device function. This can be
accomplished in two ways:
1. The first way is to take no action and let the internal POR circuit that detects the minimum DVDD and
IOVDD levels automatically reset the device into its default condition.
2. If required, the RST pin can be used. To initialize the device to its default operating condition, the
hardware reset pin (RST) can be pulled low for at least 10 ns. For this initialization to work, both the
IOVDD and DVDD supplies must be powered up. It is recommended that while the DVDD supply is
being powered up, the RST pin be pulled low.
The device can also be reset via software reset. Writing a 1 into page 0, register 1, bit D0 resets the
internal registers, but not the digital interface.
Device Initialization
Time between IOVDD is provided and, AVDD and DVDD are
provided.
Time between DVDD (and IOVDD) is provided and reset can
be released.
Time between release of the reset and when registers can be
written (that is Powered up PLL and HP Level Shifters).
3.2.2 Device Start-Up Lockout Times
After the TAS2505 is initialized through the power up process, the internal memories are initialized to
default values. This initialization takes place within 1 ms after the power up process. During this
initialization phase, no register-read or register-write operation should be performed on the DAC
coefficient buffers. Also, no block within the codec should be powered up during the initialization phase.
3.2.3 PLL Start-Up
Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up
command of the PLL and before the clocks are available to the codec. This delay is to ensure stable
operation of the PLL and clock-divider logic.
3.2.4 Power-Stage Reset
The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has
occurred. Using this reset re-enables the output stage without resetting all of the registers in the device.
Each of the two power stages has its own dedicated reset bit. The headphone power-stage reset is
performed by setting page 1, register 9, bit D5 for HPOUT. If a short circuit is detected at Headphone
output, page 1, register 11, bit D0 will power down the driver. The speaker power-stage reset is performed
by setting page 1 / register 45, bit D1 for SPKP and SPKM.
3.2.5 Software Power Down
By default, all circuit blocks are powered down following a reset condition. Hardware power up of each
circuit block can be controlled by writing to the appropriate control register. This approach allows the
lowest power-supply current for the functionality required. However, when a block is powered down, all of
the register settings are maintained as long as power is still being applied to the device.
The TAS2505 allows the user to set the common mode voltage for analog inputs to 0.75V or 0.9V by
programming Page 1, Register 10, D(6). The input common-mode voltage of 0.9V works best when the
analog supply voltage is centered around 1.8V or above, and offers the highest possible performance. For
analog supply voltages below 1.8V, a common mode voltage of 0.75V must be used.
Table 3-3. Input Common Mode voltage and Input Signal Swing
Input Common ModeAVdd (V)Channel Gain (dB)Single-Ended InputDifferential Input
Voltage (V)Swing for 0dBFSSwing for 0dBFS
0.75>1.5–20.3750.75
0.901.8 … 1.9500.51.0
NOTE: The input common mode setting is common for DAC playback and Analog Bypass path
The following example EVM I2C register control scripts can be taken directly for the TAS2505 EVM setup.
The # marks a comment line, w marks an I2C write command followed by the device address, the I2C
register address and the value. The EVM I2C register control scripts follows to show how to set up the
TAS2505 in playback mode with fS= 44.1 kHz and MCLK = 11.2896 MHz.
4.0.7 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker
Outputs
# I2C Script to Setup the device in Playback Mode
# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY
# This script set DAC output routed to HP Driver and Class-D driver via Mixer
# # ==> comment delimiter
# Page switch to Page 0
W 30 00 00
# Assert Software reset (P0, R1, D0=1)
W 30 01 01
# Page Switch to Page 1
W 30 00 01
# LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0)
W 30 02 00
# Page switch to Page 0
W 30 00 00
#PLL_clkin = MCLK, codec_clkin = PLL_CLK, MCLK should be 11.2896MHz (P0, R4, D1-D0=03)
w 30 04 03
# Power up PLL, set P=1, R=1, (Page-0, Reg-5)
w 30 05 91
# Set J=4, (Page-0, Reg-6)
w 30 06 04
# D = 0000, D(13:8) = 0, (Page-0, Reg-7)
w 30 07 00
#D(7:0) = 0, (Page-0, Reg-8)
w 30 08 00
# add delay of 15 ms for PLL to lock
d 15
#DAC NDAC Powered up, NDAC=4 (P0, R11, D7=1, D6-D0=0000100)
W 30 0B 84
#DAC MDAC Powered up, MDAC=2 (P0, R12, D7=1, D6-D0=0000010)
W 30 0C 82
#DAC OSR(9:0)-> DOSR=128 (P0, R12, D1-D0=00)
W 30 0D 00
#DAC OSR(9:0)-> DOSR=128 (P0, R13, D7-D0=10000000)
W 30 0E 80
# Codec Interface control Word length = 16bits, BCLK&WCLK inputs, I2S mode. (P0, R27, D7D6=00, D5-D4=00, D3-D2=00)
W 30 1B 00
# Data slot offset 00 (P0, R28, D7-D0=0000)
W 30 1C 00
# Dac Instruction programming PRB #2 for Mono routing. Type interpolation (x8) and 3 programmable
Biquads. (P0, R60, D4-D0=0010)
W 30 3C 02
W 30 00 01
# Master Reference Powered on (P1, R1, D4=1)
W 30 01 10
# Output common mode for DAC set to 0.9V (default) (P1, R10)
W 30 0A 00
# Mixer P output is connected to HP Out Mixer (P1, R12, D2=1)
w 30 0C 04
# HP Voulme, 0dB Gain (P1, R22, D6-D0=0000000)
W 30 16 00
# No need to enable Mixer M and Mixer P, AINL Voulme, 0dB Gain (P1, R24, D7=1, D6-D0=0000000)
W 30 18 00
# Power up HP (P1, R9, D5=1)
w 30 09 20
# Unmute HP with 0dB gain (P1, R16, D4=1)
w 30 10 00
#SPK attn. Gain =0dB (P1, R46, D6-D0=000000)
W 30 2E 00
#SPK driver Gain=6.0dB (P1, R48, D6-D4=001)
W 30 30 10
#SPK powered up (P1, R45, D1=1)
W 30 2D 02
# Page switch to Page 0
W 30 00 00
# DAC powered up, Soft step 1 per Fs. (P0, R63, D7=1, D5-D4=01, D3-D2=00, D1-D0=00)
W 30 3F 90
# DAC digital gain 0dB (P0, R65, D7-D0=00000000)
W 30 41 00
# DAC volume not muted. (P0, R64, D3=0, D2=1)
W 30 40 04
#
4.0.8 Example Register Setup to Play Digital Data Through DAC and Headphone Output
# I2C Script to Setup the device in Playback Mode
# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY
# This script set DAC output routed to only HP Driver
# # ==> comment delimiter
#
# Page switch to Page 0
W 30 00 00
# Assert Software reset (P0, R1, D0=1)
W 30 01 01
# Page Switch to Page 1
W 30 00 01
# LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0)
W 30 02 00
Page switch to Page 0
W 30 00 00
#CODEC_CLKIN=MCLK, MCLK should be 11.2896MHz (P0, R4, D1-D0=00)
W 30 04 00
#DAC NDAC Powered up, NDAC=1 (P0, R11, D7=1, D6-D0=0000001)
W 30 0B 81
#DAC MDAC Powered up, MDAC=2 (P0, R12, D7=1, D6-D0=0000010)
W 30 0C 82
#DAC OSR(9:0)-> DOSR=128 (P0, R12, D1-D0=00)
W 30 0D 00
#DAC OSR(9:0)-> DOSR=128 (P0, R13, D7-D0=10000000)
W 30 0E 80
# Codec Interface control Word length = 16bits, BCLK&WCLK inputs, I2S mode. (P0, R27, D7D6=00, D5-D4=00, D3-D2=00)
W 30 1B 00
# Data slot offset 00 (P0, R28, D7-D0=0000)
W 30 1C 00
# Dac Instruction programming PRB #2 for Mono routing. Type interpolation (x8) and 3 programmable
Biquads. (P0, R60, D4-D0=0010)
W 30 3C 02
# Page Switch to Page 1
W 30 00 01
# Master Reference Powered on (P1, R1, D4=1)
W 30 01 10
# Output common mode for DAC set to 0.9V (default) (P1, R10)
W 30 0A 00
# DAC output is routed directly to HP driver (P1, R12, D3=1)
w 30 0C 08
# HP Voulme, 0dB Gain (P1, R22, D6-D0=0000000)
W 30 16 00
# Power up HP (P1, R9, D5=1)
w 30 09 20
# Unmute HP with 0dB gain (P1, R16, D4=1)
w 30 10 00
# Page switch to Page 0
W 30 00 00
# DAC powered up, Soft step 1 per Fs. (P0, R63, D7=1, D5-D4=01, D3-D2=00, D1-D0=00)
W 30 3F 90
# DAC digital gain 0dB (P0, R65, D7-D0=00000000)
W 30 41 00
# DAC volume not muted. (P0, R64, D3=0, D2=1)
W 30 40 04
#
4.0.9 Example Register Setup to Play AINL and AINR Through Headphone/Speaker Outputs
# I2C Script to Setup the device in Playback Mode
# This script set AINL and AINR inputs routed to HP Driver and Class-D driver via Mixer
# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# Page switch to Page 0
W 30 00 00
# Assert Software reset (P0, R1, D0=1)
W 30 01 01
# Page Switch to Page 1
W 30 00 01
# LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0)
W 30 02 00
# Master Reference Powered on (P1, R1, D4=1)
W 30 01 10
# Enable AINL and AINR (P1, R9, D1-D0=11)
w 30 09 03
# AINL/R to HP driver via Mixer P (P1, R12, D7-D6=11, D2=1)
w 30 0C C4
# HP Voulme, 0dB Gain (P1, R22, D6-D0=0000000)
W 30 16 00
# Enable Mixer P and Mixer M, AINL Voulme, 0dB Gain (P1, R24, D7=1, D6-D0=0000000)
W 30 18 80
# Enable AINL and AINR and Power up HP (P1, R9, D5=1, D1-D0=11)
w 30 09 23
# Unmute HP with 0dB gain (P1, R16, D4=1)
w 30 10 00
#SPK attn. Gain =0dB (P1, R46, D6-D0=000000)
W 30 2E 00
#SPK driver Gain=6.0dB (P1, R48, D6-D4=001)
W 30 30 10
#SPK powered up (P1, R45, D1=1)
W 30 2D 02
#
4.0.10 Example Register Setup to Play AINL and AINR Through Headphone Output
# I2C Script to Setup the device in Playback Mode
# This script set AINL and AINR inputs routed to only HP Driver
# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# Page switch to Page 0
W 30 00 00
# Assert Software reset (P0, R1, D0=1)
W 30 01 01
# Page Switch to Page 1
W 30 00 01
# LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0)
W 30 02 00
# Master Reference Powered on (P1, R1, D4=1)
W 30 01 10
# Enable AINL and AINR (P1, R9, D1-D0=11)
w 30 09 03
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# AINL/R to HP driver not via Mixer P (P1, R12, D1-D0=11)
w 30 0C 03
# HP Voulme, 0dB Gain (P1, R22, D6-D0=0000000)
W 30 16 00
# Not enable HP Out Mixer, AINL Voulme, 0dB Gain (P1, R24, D7=0, D6-D0=0000000)
W 30 18 00
# Enable AINL and AINR and Power up HP (P1, R9, D5=1, D1-D0=11)
w 30 09 23
# Unmute HP with 0dB gain (P1, R16, D4=1)
w 30 10 00
#
4.0.11 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker
Outputs with 3 programmable Biquads
# I2C Script to Setup the device in Playback Mode #2
# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY
# This script set DAC output routed to HP Driver and ClassD driver via Mixer with 3 programmable Biquads.
# # ==> comment delimiter
#
# Page switch to Page 0
W 30 00 00
# Assert Software reset (P0, R1, D0=1)
W 30 01 01
# Page Switch to Page 1
W 30 00 01
# LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0)
W 30 02 00
##########--------------- END COEFFICIENTS OF Notch Filters-----------------------#######################################################
# Page Switch to Page 1
W 30 00 01
# Master Reference Powered on (P1, R1, D4=1)
W 30 01 10
# Output common mode for DAC set to 0.9V (default) (P1, R10)
W 30 0A 00
# Mixer P output is connected to HP Out Mixer (P1, R12, D2=1)
w 30 0C 04
# HP Voulme, 0dB Gain (P1, R22, D6-D0=0000000)
W 30 16 00
# Power up HP (P1, R9, D5=1)
w 30 09 20
# Unmute HP with 0dB gain (P1, R16, D4=1)
w 30 10 00
#SPK attn. Gain =0dB (P1, R46, D6-D0=000000)
W 30 2E 00
#SPK driver Gain=6.0dB (P1, R48, D6-D4=001)
W 30 30 10
#SPK powered up (P1, R45, D1=1)
W 30 2D 02
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# Page switch to Page 0
W 30 00 00
# DAC powered up, Soft step 1 per Fs. (P0, R63, D7=1, D5-D4=01, D3-D2=00, D1-D0=00)
W 30 3F 90
# DAC digital gain 0dB (P0, R65, D7-D0=00000000)
W 30 41 00
# DAC volume not muted. (P0, R64, D3=0, D2=1)
W 30 40 04
#
4.0.12 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker
Outputs with 6 programmable Biquads
# I2C Script to Setup the device in Playback Mode #3
# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY
# This script set DAC output routed to HP Driver and ClassD driver via Mixer with 6 programmable Biquads.
# # ==> comment delimiter
#
# Page switch to Page 0
W 30 00 00
# Assert Software reset (P0, R1, D0=1)
W 30 01 01
# Page Switch to Page 1
W 30 00 01
# LDO output programmed as 1.8V and Level shifters powered up. (P1, R2, D5-D4=00, D3=0)
W 30 02 00
# Page switch to Page 0
W 30 00 00
#CODEC_CLKIN=MCLK, MCLK should be 11.2896MHz (P0, R4, D1-D0=00)
W 30 04 00
#DAC NDAC Powered up, NDAC=1 (P0, R11, D7=1, D6-D0=0000001)
W 30 0B 81
#DAC MDAC Powered up, MDAC=2 (P0, R12, D7=1, D6-D0=0000010)
W 30 0C 82
#DAC OSR(9:0)-> DOSR=128 (P0, R12, D1-D0=00)
W 30 0D 00
#DAC OSR(9:0)-> DOSR=128 (P0, R13, D7-D0=10000000)
W 30 0E 80
# Codec Interface control Word length = 16bits, BCLK&WCLK inputs, I2S mode. (P0, R27, D7D6=00, D5-D4=00, D3-D2=00)
W 30 1B 00
# Data slot offset 00 (P0, R28, D7-D0=0000)
W 30 1C 00
# Dac Instruction programming PRB #3 for Mono routing. Type B nterpolation (x4) and 6
programmable Biquads. (P0, R60, D4-D0=0011)
W 30 3C 03
##########--------------- BEGIN COEFFICIENTS -------------------------------------# reg 00 - Page Select Register = 46
# sets active page to page 46 for First-Order IIR
w 30 00 2E
#----------------------------------------------------------------------# First-Order IIR = 100Hz HP
#-----------------------------------------------------------------------
# reg 28/29/30 - N0 Coefficient
w 30 1C 7F 18 36
# reg 32/33/34 - N1 Coefficient
w 30 20 80 E7 CA
# reg 36/37/38 - N2 Coefficient
w 30 24 7E 30 6D
# reg 00 - Page Select Register = 44
# sets active page to page 44 for 6-BQs (BQ-A, BQ-B, BQ-C, BQ-D, BQ-E, BQ-F)
w 30 00 2C
#
#----------------------------------------------------------------------# BQ-A = 500Hz Notch BW = 25
#-----------------------------------------------------------------------
# sets active page to page 45 for BQ-F D2
w 30 00 2D
# reg 8/9/10 - D2 Coefficient
w 30 08 80 74 84
##########--------------- END COEFFICIENTS OF Notch Filters-----------------------#######################################################
# Page Switch to Page 1
W 30 00 01
# Master Reference Powered on (P1, R1, D4=1)
W 30 01 10
# Output common mode for DAC set to 0.9V (default) (P1, R10)
W 30 0A 00
# Mixer P output is connected to HP Out Mixer (P1, R12, D2=1)
w 30 0C 04
# HP Voulme, 0dB Gain (P1, R22, D6-D0=0000000)
W 30 16 00
# Power up HP (P1, R9, D5=1)
w 30 09 20
# Unmute HP with 0dB gain (P1, R16, D4=1)
w 30 10 00
#SPK attn. Gain =0dB (P1, R46, D6-D0=000000)
W 30 2E 00
#SPK driver Gain=6.0dB (P1, R48, D6-D4=001)
W 30 30 10
#SPK powered up (P1, R45, D1=1)
W 30 2D 02
# Page switch to Page 0
W 30 00 00
# DAC powered up, Soft step 1 per Fs. (P0, R63, D7=1, D5-D4=01, D3-D2=00, D1-D0=00)
W 30 3F 90
# DAC digital gain 0dB (P0, R65, D7-D0=00000000)
W 30 41 00
# DAC volume not muted. (P0, R64, D3=0, D2=1)
W 30 40 04
#
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5.1TAS2505 Register Map
All features on this device are addressed using the I2C bus or SPI. All of the writable registers can be read
back. However, some registers contain status information or data, and are available for reading only.
The TAS2505 contains several pages of 8-bit registers, and each page can contain up to 128 registers.
The register pages are divided up based on functional blocks for this device. Page 0 is the default home
page after RST. Page control is done by writing a new page value into register 0 of the current page.
The control registers for the TAS2505 are described in detail as follows. All registers are 8 bits in width,
with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit.
Pages0, 1, 44-52 and 62-70 are available for use; however, all other pages and registers are reserved. Do
not read from or write to reserved pages and registers. Also, do not write other than the Reset Values for
the reserved bits and read-only bits of non-reserved registers; otherwise, device functionality failure can
occur.
Chapter 5
SLAU472–February 2013
Register Map
Table 5-1. Summary of Register Map
Page NumberDescription
0
1
8 - 43Page 8 - 43: Reserved Registers
44Page 44: DAC Programmable Coefficients RAM. See Section 5.1.4 and Section 5.1.9.
45 - 52Page 45 - 52: DAC Programmable Coefficients RAM. See Section 5.1.5 and Section 5.1.9.
53 - 61Page 53 - 61: Reserved Registers
62 - 70Page 62 - 70: DAC Programmable Coefficients RAM. See Section 5.1.7 and Section 5.1.9.
71 - 255Page 71 -255: Reserved Registers
58
Register MapSLAU472–February 2013
Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and
GPIOs. See Section 5.1.1.
Control Registers, Page 1: DAC Routing, Power-Controls and MISC Logic Related Programmabilities. See
D7–D6R00Reserved. Write only default values.
D5–D0R/W00 0000PLL divider D value (MSB)
PLL divider D value(MSB) and PLL divider D value(LSB)
00 0000 0000 0000: D=0000
00 0000 0000 0001: D=0001
…
10 0111 0000 1110: D=9998
10 0111 0000 1111: D=9999
10 0111 0001 0000…11 1111 1111 1111: Do not use
Note: This register will be updated only when the Page-0, Reg-8 is written immediately after
Page-0, Reg-7.
PLL divider D value(MSB) and PLL divider D value(LSB)
00 0000 0000 0000: D=0000
00 0000 0000 0001: D=0001
…
10 0111 0000 1110: D=9998
10 0111 0000 1111: D=9999
10 0111 0001 0000…11 1111 1111 1111: Do not use
Note: Page-0, Reg-8 should be written immediately after Page-0, Reg-7.
1: Overflow condition is present in DAC at the time of reading the register"
D6R0Reserved. Write only default value.
D5R0Reverved. Write only default value.
D3R0Reserved. Write only default value.
D2R0Reserved. Write only default value.
D1R0Reverved. Write only default value.
D0R0Reserved. Write only default value.
0: Over Current not detected on HPOUT
1: Over Current detected on HPOUT (will be cleared when the register is read)"
Page 0 / Register 45: Reserved - 0x00 / 0x2D
BITRead/WriteReset ValueDESCRIPTION
D7-D0R0000 0000Reserved. Write only default values.
D3R0Reserved. Write only default value.
D2R0Reserved. Write only default value.
D1R0Reserved. Write only default value.
D0R0Reserved. Write only default value.
0: Over Current not detected on HPOUT
1: Over Current detected on HPOUT
BITRead/WriteReset ValueDESCRIPTION
D7-D0R0000 0000Reserved. Write only default value.
D5R0Reserved. Write only default value.
D4R0Reserved. Write only default value.
D3R/W0INT1 Interrupt for Over Current Condition
0: Headphone Over Current condition will not generate a INT1 interrupt.
1: Headphone Over Current condition will generate a INT1 interrupt.
D2R0Reverved. Write only default value.
D1R0Reserved. Write only default value.
D0R/W0INT1 pulse control
0: INT1 is active high interrupt of 1 pulse of approx. 2ms duration
1: INT1 is active high interrupt of multiple pulses, each of duration 2ms. To stop the pulse
D5R0Reserved. Write only default value.
D4R0Reserved. Write only default value.
D3R/W0INT2 Interrupt for Over Current Condition
0: Headphone Over Current condition will not generate a INT2 interrupt.
1: Headphone Over Current condition will generate a INT2 interrupt.
D2R0Reserved. Write only default value.
D1R0Reserved. Write only default value.
D0R/W0INT2 pulse control
0: INT2 is active high interrupt of 1 pulse of approx. 2ms duration
1: INT2 is active high interrupt of multiple pulses, each of duration 2ms. To stop the pulse
1: Mixer P and Mixer M forcedly enabled
Note: This a bit need to set "1" when not powered-on DAC and need to route AINL or AINR
signal input to HP driver and SPK driver via Mixer P.
D6-D0R/W000 0000AINL Volume Control
000 0000: Volume Control = 0.0dB000 1010: Volume Control = -5.0dB
000 0001: Volume Control = -0.5dB000 1011: Volume Control = -5.5dB
000 0010: Volume Control = -1.0dB000 1100: Volume Control = -6.0dB
000 0011: Volume Control = -1.5dB000 1101: Volume Control = -6.5dB
000 0100: Volume Control = -2.0dB000 1110: Volume Control = -7.0dB
000 0101: Volume Control = -2.5dB000 1111: Volume Control = -7.5dB
000 0110: Volume Control = -3.0dB001 0000: Volume Control = -8.0dB
000 0111: Volume Control = -3.5dB001 0001: Volume Control = -8.5dB
000 1000: Volume Control = -4.0dB001 0010: Volume Control = -9.0dB
000 1001: Volume Control = -4.5dB001 0011: Volume Control = -9.5dB
001 0100: Volume Control = -10.0dB001 1110: Volume Control = -15.1dB
001 0101: Volume Control = -10.5dB001 1111: Volume Control = -15.6dB
001 0110: Volume Control = -11.0dB010 0000: Volume Control = -16.0dB
001 0111: Volume Control = -11.5dB010 0001: Volume Control = -16.5dB
001 1000: Volume Control = -12.0dB010 0010: Volume Control = -17.1dB
001 1001: Volume Control = -12.5dB010 0011: Volume Control = -17.5dB
001 1010: Volume Control = -13.0dB010 0100: Volume Control = -18.1dB
001 1011: Volume Control = -13.5dB010 0101: Volume Control = -18.6dB
001 1100: Volume Control = -14.1dB010 0110: Volume Control = -19.1dB
001 1101: Volume Control = -14.6dB010 0111: Volume Control = -19.6dB
010 1000: Volume Control = -20.1dB011 0010: Volume Control = -25.1dB
010 1001: Volume Control = -20.6dB011 0011: Volume Control = -25.6dB
010 1010: Volume Control = -21.1dB011 0100: Volume Control = -26.1dB
010 1011: Volume Control = -21.6dB011 0101: Volume Control = -26.6dB
010 1100: Volume Control = -22.1dB011 0110: Volume Control = -27.1dB
010 1101: Volume Control = -22.6dB011 0111: Volume Control = -27.6dB
010 1110: Volume Control = -23.1dB011 1000: Volume Control = -28.1dB
010 1111: Volume Control = -23.6dB011 1001: Volume Control = -28.6dB
011 0000: Volume Control = -24.1dB011 1010: Volume Control = -29.1dB
011 0001: Volume Control = -24.6dB011 1011: Volume Control = -29.6dB
011 1100: Volume Control = -30.1dB100 0110: Volume Control = -35.2dB
011 1101: Volume Control = -30.6dB100 0111: Volume Control = -35.7dB
011 1110: Volume Control = -31.1dB100 1000: Volume Control = -36.1dB
011 1111: Volume Control = -31.6dB100 1001: Volume Control = -36.7dB
100 0000: Volume Control = -32.1dB100 1010: Volume Control = -37.2dB
100 0001: Volume Control = -32.6dB100 1011: Volume Control = -37.7dB
100 0010: Volume Control = -33.1dB100 1100: Volume Control = -38.2dB
100 0011: Volume Control = -33.6dB100 1101: Volume Control = -38.7dB
100 0100: Volume Control = -34.1dB100 1110: Volume Control = -39.2dB
100 0101: Volume Control = -34.6dB100 1111: Volume Control = -39.7dB
101 0000: Volume Control = -40.2dB101 1010: Volume Control = -45.2dB
101 0001: Volume Control = -40.7dB101 1011: Volume Control = -45.8dB
101 0010: Volume Control = -41.2dB101 1100: Volume Control = -46.2dB
101 0011: Volume Control = -41.8dB101 1101: Volume Control = -46.7dB
101 0100: Volume Control = -42.1dB101 1110: Volume Control = -47.4dB
101 0101: Volume Control = -42.7dB101 1111: Volume Control = -47.9dB
101 0110: Volume Control = -43.2dB110 0000: Volume Control = -48.2dB
101 0111: Volume Control = -43.8dB110 0001: Volume Control = -48.7dB
101 1000: Volume Control = -44.3dB110 0010: Volume Control = -49.3dB
101 1001: Volume Control = -44.8dB110 0011: Volume Control = -50.0dB
110 0100: Volume Control = -50.3dB110 1101: Volume Control = -56.7dB
110 0101: Volume Control = -51.0dB110 1110: Volume Control = -58.3dB
110 0110: Volume Control = -51.4dB110 1111: Volume Control = -60.1dB
110 0111: Volume Control = -51.8dB111 0000: Volume Control = -62.7dB
110 1000: Volume Control = -52.3dB111 0001: Volume Control = -64.3dB
110 1001: Volume Control = -52.7dB111 0010: Volume Control = -66.2dB
110 1010: Volume Control = -53.7dB111 0011: Volume Control = -66.7dB
110 1011: Volume Control = -54.2dB111 0100: Volume Control = -72.3dB
110 1100: Volume Control = -55.4dB111 0101: Volume Control = Mute
000 0000: Volume Control = 0.00 dB000 1010: Volume Control = -5.0 dB
000 0001: Volume Control = -0.5 dB000 1011: Volume Control = -5.5 dB
000 0010: Volume Control = -1.0 dB000 1100: Volume Control = -6.0 dB
000 0011: Volume Control = -1.5 dB000 1101: Volume Control = -6.5 dB
000 0100: Volume Control = -2.0 dB000 1110: Volume Control = -7.0 dB
000 0101: Volume Control = -2.5 dB000 1111: Volume Control = -7.5 dB
000 0110: Volume Control = -3.0 dB001 0000: Volume Control = -8.0 dB
000 0111: Volume Control = -3.5 dB001 0001: Volume Control = -8.5 dB
000 1000: Volume Control = -4.0 dB001 0010: Volume Control = -9.0 dB
000 1001: Volume Control = -4.5 dB001 0011: Volume Control = -9.5 dB
001 0100: Volume Control = -10.0 dB001 1110: Volume Control = -15.1dB
001 0101: Volume Control = -10.5 dB001 1111: Volume Control = -15.6 dB
001 0110: Volume Control = -11.0 dB010 0000: Volume Control = -16.0 dB
001 0111: Volume Control = -11.5 dB010 0001: Volume Control = -16.5 dB
001 1000: Volume Control = -12.0 dB010 0010: Volume Control = -17.1 dB
001 1001: Volume Control = -12.5 dB010 0011: Volume Control = -17.5 dB
001 1010: Volume Control = -13.0 dB010 0100: Volume Control = -18.1 dB
001 1011: Volume Control = -13.5 dB010 0101: Volume Control = -18.6 dB
001 1100: Volume Control = -14.1 dB010 0110: Volume Control = -19.1 dB
001 1101: Volume Control = -14.6 dB010 0111: Volume Control = -19.6 dB
010 1000: Volume Control = -20.1 dB011 0010: Volume Control = -25.1 dB
010 1001: Volume Control = -20.6 dB011 0011: Volume Control = -25.6 dB
010 1010: Volume Control = -21.1 dB011 0100: Volume Control = -26.1 dB
010 1011: Volume Control = -21.6 dB011 0101: Volume Control = -26.6 dB
010 1100: Volume Control = -22.1 dB011 0110: Volume Control = -27.1 dB
010 1101: Volume Control = -22.6 dB011 0111: Volume Control = -27.6 dB
010 1110: Volume Control = -23.1 dB011 1000: Volume Control = -28.1 dB
010 1111: Volume Control = -23.6 dB011 1001: Volume Control = -28.6 dB
011 0000: Volume Control = -24.1 dB011 1010: Volume Control = -29.1 dB
011 0001: Volume Control = -24.6 dB011 1011: Volume Control = -29.6 dB
011 1100: Volume Control = -30.1 dB100 0110: Volume Control = -35.2dB
011 1101: Volume Control = -30.6 dB100 0111: Volume Control = -35.7 dB
011 1110: Volume Control = -31.1 dB100 1000: Volume Control = -36.1 dB
011 1111: Volume Control = -31.6 dB100 1001: Volume Control = -36.7 dB
100 0000: Volume Control = -32.1 dB100 1010: Volume Control = -37.1 dB
100 0001: Volume Control = -32.7 dB100 1011: Volume Control = -37.7 dB
100 0010: Volume Control = -33.1 dB100 1100: Volume Control = -38.2 dB
100 0011: Volume Control = -33.6 dB100 1101: Volume Control = -38.7 dB
100 0100: Volume Control = -34.1 dB100 1110: Volume Control = -39.2 dB
100 0101: Volume Control = -34.6 dB100 1111: Volume Control = -39.7 dB
101 0000: Volume Control = -40.2 dB101 1010: Volume Control = -45.2 dB
101 0001: Volume Control = -40.7 dB101 1011: Volume Control = -45.8 dB
101 0010: Volume Control = -41.2 dB101 1100: Volume Control = -46.2 dB
101 0011: Volume Control = -41.8 dB101 1101: Volume Control = -46.7 dB
101 0100: Volume Control = -42.1 dB101 1110: Volume Control = -47.4 dB
101 0101: Volume Control = -42.7 dB101 1111: Volume Control = -47.9 dB
101 0110: Volume Control = -43.2 dB110 0000: Volume Control = -48.2 dB
101 0111: Volume Control = -43.8 dB110 0001: Volume Control = -48.7 dB
101 1000: Volume Control = -44.3 dB110 0010: Volume Control = -49.3 dB
101 1001: Volume Control = -44.8 dB110 0011: Volume Control = -50.0 dB
110 0100: Volume Control = -50.3 dB110 1101: Volume Control = -56.7 dB
110 0101: Volume Control = -51.0 dB110 1110: Volume Control = -58.3 dB
110 0110: Volume Control = -51.4 dB110 1111: Volume Control = -60.2 dB
110 0111: Volume Control = -51.8 dB111 0000: Volume Control = -62.7 dB
110 1000: Volume Control = -52.3 dB111 0001: Volume Control = -64.3 dB
110 1001: Volume Control = -52.7 dB111 0010: Volume Control = -66.2 dB
110 1010: Volume Control = -53.7 dB111 0011: Volume Control = -68.7 dB
110 1011: Volume Control = -54.2 dB111 0100: Volume Control = -72.3 dB
110 1100: Volume Control = -55.4 dB111 0101 - 1111110: Reserved
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