TEXAS INSTRUMENTS-ADVANCE INFORMATION
Stellaris® LM3S1R21 Microcontroller
DATA SHEET
DS-LM3S1R21-6790
Copyright © 2007-2010 Texas Instruments
Incorporated
Copyright
Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specications
are subject to change without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
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108 Wild Basin, Suite 350
Austin, TX 78746
http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Stellaris® LM3S1R21 Microcontroller
Table of Contents
Revision History .............................................................................................................................23
About This Document .................................................................................................................... 27
Audience .............................................................................................................................................. 27
About This Manual ................................................................................................................................ 27
Related Documents ............................................................................................................................... 27
Documentation Conventions .................................................................................................................. 27
1 Architectural Overview .......................................................................................... 30
1.1 Functional Overview ...................................................................................................... 32
1.1.1 ARM Cortex™-M3 ......................................................................................................... 32
1.1.2 On-Chip Memory ........................................................................................................... 34
1.1.3 External Peripheral Interface ......................................................................................... 35
1.1.4 Serial Communications Peripherals ................................................................................ 36
1.1.5 System Integration ........................................................................................................ 39
1.1.6 Analog .......................................................................................................................... 44
1.1.7 JTAG and ARM Serial Wire Debug ................................................................................ 46
1.1.8 Packaging and Temperature .......................................................................................... 47
1.2 Target Applications ........................................................................................................ 47
1.3 High-Level Block Diagram ............................................................................................. 47
1.4 Additional Features ....................................................................................................... 49
1.4.1 Memory Map ................................................................................................................ 49
1.4.2 Hardware Details .......................................................................................................... 49
2 ARM Cortex-M3 Processor Core ........................................................................... 50
2.1 Block Diagram .............................................................................................................. 51
2.2 Functional Description ................................................................................................... 51
2.2.1 Programming Model ...................................................................................................... 51
2.2.2 Serial Wire and JTAG Debug ......................................................................................... 58
2.2.3 Embedded Trace Macrocell (ETM) ................................................................................. 58
2.2.4 Trace Port Interface Unit (TPIU) ..................................................................................... 58
2.2.5 ROM Table ................................................................................................................... 59
2.2.6 Memory Protection Unit (MPU) ....................................................................................... 59
2.2.7 Nested Vectored Interrupt Controller (NVIC) .................................................................... 59
2.2.8 System Timer (SysTick) ................................................................................................. 60
3 Memory Map ........................................................................................................... 63
4 Interrupts ................................................................................................................. 66
5 JTAG Interface ........................................................................................................ 69
5.1 Block Diagram .............................................................................................................. 70
5.2 Signal Description ......................................................................................................... 70
5.3 Functional Description ................................................................................................... 71
5.3.1 JTAG Interface Pins ...................................................................................................... 71
5.3.2 JTAG TAP Controller ..................................................................................................... 73
5.3.3 Shift Registers .............................................................................................................. 73
5.3.4 Operational Considerations ............................................................................................ 74
5.4 Initialization and Configuration ....................................................................................... 76
5.5 Register Descriptions .................................................................................................... 77
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5.5.1 Instruction Register (IR) ................................................................................................. 77
5.5.2 Data Registers .............................................................................................................. 79
6 System Control ....................................................................................................... 81
6.1 Signal Description ......................................................................................................... 81
6.2 Functional Description ................................................................................................... 81
6.2.1 Device Identification ...................................................................................................... 82
6.2.2 Reset Control ................................................................................................................ 82
6.2.3 Non-Maskable Interrupt ................................................................................................. 86
6.2.4 Power Control ............................................................................................................... 86
6.2.5 Clock Control ................................................................................................................ 87
6.2.6 System Control ............................................................................................................. 93
6.3 Initialization and Configuration ....................................................................................... 95
6.4 Register Map ................................................................................................................ 95
6.5 Register Descriptions .................................................................................................... 96
7 Hibernation Module .............................................................................................. 172
7.1 Block Diagram ............................................................................................................ 173
7.2 Signal Description ....................................................................................................... 173
7.3 Functional Description ................................................................................................. 174
7.3.1 Register Access Timing ............................................................................................... 175
7.3.2 Clock Source .............................................................................................................. 175
7.3.3 Battery Management ................................................................................................... 176
7.3.4 Real-Time Clock .......................................................................................................... 177
7.3.5 Non-Volatile Memory ................................................................................................... 177
7.3.6 Power Control Using HIB ............................................................................................. 177
7.3.7 Power Control Using VDD3ON Mode ........................................................................... 178
7.3.8 Initiating Hibernate ...................................................................................................... 178
7.3.9 Interrupts and Status ................................................................................................... 178
7.4 Initialization and Configuration ..................................................................................... 179
7.4.1 Initialization ................................................................................................................. 179
7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 180
7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 180
7.4.4 External Wake-Up from Hibernation .............................................................................. 180
7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 180
7.4.6 Register Reset ............................................................................................................ 181
7.5 Register Map .............................................................................................................. 181
7.6 Register Descriptions .................................................................................................. 182
8 Internal Memory ................................................................................................... 199
8.1 Block Diagram ............................................................................................................ 199
8.2 Functional Description ................................................................................................. 199
8.2.1 SRAM ........................................................................................................................ 200
8.2.2 ROM .......................................................................................................................... 200
8.2.3 Flash Memory ............................................................................................................. 200
8.3 Flash Memory Initialization and Configuration ............................................................... 202
8.3.1 Flash Memory Programming ........................................................................................ 202
8.3.2 32-Word Flash Memory Write Buffer ............................................................................. 203
8.3.3 Nonvolatile Register Programming ............................................................................... 204
8.4 Register Map .............................................................................................................. 205
8.5 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 206
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8.6 Memory Register Descriptions (System Control Offset) .................................................. 217
9 Micro Direct Memory Access (μDMA) ................................................................ 233
9.1 Block Diagram ............................................................................................................ 234
9.2 Functional Description ................................................................................................. 234
9.2.1 Channel Assignments .................................................................................................. 235
9.2.2 Priority ........................................................................................................................ 236
9.2.3 Arbitration Size ............................................................................................................ 236
9.2.4 Request Types ............................................................................................................ 236
9.2.5 Channel Configuration ................................................................................................. 237
9.2.6 Transfer Modes ........................................................................................................... 239
9.2.7 Transfer Size and Increment ........................................................................................ 247
9.2.8 Peripheral Interface ..................................................................................................... 247
9.2.9 Software Request ........................................................................................................ 247
9.2.10 Interrupts and Errors .................................................................................................... 248
9.3 Initialization and Configuration ..................................................................................... 248
9.3.1 Module Initialization ..................................................................................................... 248
9.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 248
9.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 250
9.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 251
9.3.5 Configuring Alternate Channels .................................................................................... 254
9.4 Register Map .............................................................................................................. 254
9.5 μDMA Channel Control Structure ................................................................................. 255
9.6 μDMA Register Descriptions ........................................................................................ 262
10 General-Purpose Input/Outputs (GPIOs) ........................................................... 291
10.1 Signal Description ....................................................................................................... 291
10.2 Functional Description ................................................................................................. 296
10.2.1 Data Control ............................................................................................................... 297
10.2.2 Interrupt Control .......................................................................................................... 298
10.2.3 Mode Control .............................................................................................................. 299
10.2.4 Commit Control ........................................................................................................... 299
10.2.5 Pad Control ................................................................................................................. 300
10.2.6 Identification ............................................................................................................... 300
10.3 Initialization and Configuration ..................................................................................... 300
10.4 Register Map .............................................................................................................. 301
10.5 Register Descriptions .................................................................................................. 304
11 External Peripheral Interface (EPI) ..................................................................... 347
11.1 EPI Block Diagram ...................................................................................................... 348
11.2 Signal Description ....................................................................................................... 349
11.3 Functional Description ................................................................................................. 351
11.3.1 Non-Blocking Reads .................................................................................................... 352
11.3.2 DMA Operation ........................................................................................................... 353
11.4 Initialization and Configuration ..................................................................................... 353
11.4.1 SDRAM Mode ............................................................................................................. 354
11.4.2 Host Bus Mode ........................................................................................................... 358
11.4.3 General-Purpose Mode ............................................................................................... 367
11.5 Register Map .............................................................................................................. 375
11.6 Register Descriptions .................................................................................................. 376
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12 General-Purpose Timers ...................................................................................... 419
12.1 Block Diagram ............................................................................................................ 420
12.2 Signal Description ....................................................................................................... 420
12.3 Functional Description ................................................................................................. 423
12.3.1 GPTM Reset Conditions .............................................................................................. 423
12.3.2 32-Bit Timer Operating Modes ...................................................................................... 424
12.3.3 16-Bit Timer Operating Modes ...................................................................................... 425
12.3.4 DMA Operation ........................................................................................................... 431
12.4 Initialization and Configuration ..................................................................................... 431
12.4.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 431
12.4.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 432
12.4.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 432
12.4.4 16-Bit Input Edge-Count Mode ..................................................................................... 433
12.4.5 16-Bit Input Edge Timing Mode .................................................................................... 433
12.4.6 16-Bit PWM Mode ....................................................................................................... 434
12.5 Register Map .............................................................................................................. 434
12.6 Register Descriptions .................................................................................................. 435
13 Watchdog Timers ................................................................................................. 466
13.1 Block Diagram ............................................................................................................ 467
13.2 Functional Description ................................................................................................. 467
13.2.1 Register Access Timing ............................................................................................... 468
13.3 Initialization and Configuration ..................................................................................... 468
13.4 Register Map .............................................................................................................. 468
13.5 Register Descriptions .................................................................................................. 469
14 Analog-to-Digital Converter (ADC) ..................................................................... 491
14.1 Block Diagram ............................................................................................................ 492
14.2 Signal Description ....................................................................................................... 492
14.3 Functional Description ................................................................................................. 493
14.3.1 Sample Sequencers .................................................................................................... 493
14.3.2 Module Control ............................................................................................................ 494
14.3.3 Hardware Sample Averaging Circuit ............................................................................. 496
14.3.4 Analog-to-Digital Converter .......................................................................................... 496
14.3.5 Differential Sampling ................................................................................................... 498
14.3.6 Internal Temperature Sensor ........................................................................................ 501
14.3.7 Digital Comparator Unit ............................................................................................... 501
14.4 Initialization and Configuration ..................................................................................... 506
14.4.1 Module Initialization ..................................................................................................... 506
14.4.2 Sample Sequencer Configuration ................................................................................. 507
14.5 Register Map .............................................................................................................. 507
14.6 Register Descriptions .................................................................................................. 509
15 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 565
15.1 Block Diagram ............................................................................................................ 566
15.2 Signal Description ....................................................................................................... 566
15.3 Functional Description ................................................................................................. 568
15.3.1 Transmit/Receive Logic ............................................................................................... 569
15.3.2 Baud-Rate Generation ................................................................................................. 569
15.3.3 Data Transmission ...................................................................................................... 570
15.3.4 Serial IR (SIR) ............................................................................................................. 570
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15.3.5 ISO 7816 Support ....................................................................................................... 571
15.3.6 Modem Handshake Support ......................................................................................... 571
15.3.7 LIN Support ................................................................................................................ 573
15.3.8 FIFO Operation ........................................................................................................... 574
15.3.9 Interrupts .................................................................................................................... 574
15.3.10 Loopback Operation .................................................................................................... 575
15.3.11 DMA Operation ........................................................................................................... 575
15.4 Initialization and Configuration ..................................................................................... 576
15.5 Register Map .............................................................................................................. 577
15.6 Register Descriptions .................................................................................................. 578
16 Synchronous Serial Interface (SSI) .................................................................... 627
16.1 Block Diagram ............................................................................................................ 628
16.2 Signal Description ....................................................................................................... 628
16.3 Functional Description ................................................................................................. 629
16.3.1 Bit Rate Generation ..................................................................................................... 630
16.3.2 FIFO Operation ........................................................................................................... 630
16.3.3 Interrupts .................................................................................................................... 630
16.3.4 Frame Formats ........................................................................................................... 631
16.3.5 DMA Operation ........................................................................................................... 638
16.4 Initialization and Configuration ..................................................................................... 639
16.5 Register Map .............................................................................................................. 640
16.6 Register Descriptions .................................................................................................. 641
17 Inter-Integrated Circuit (I2C) Interface ................................................................ 669
17.1 Block Diagram ............................................................................................................ 670
17.2 Signal Description ....................................................................................................... 670
17.3 Functional Description ................................................................................................. 671
17.3.1 I2C Bus Functional Overview ........................................................................................ 671
17.3.2 Available Speed Modes ............................................................................................... 673
17.3.3 Interrupts .................................................................................................................... 674
17.3.4 Loopback Operation .................................................................................................... 675
17.3.5 Command Sequence Flow Charts ................................................................................ 675
17.4 Initialization and Configuration ..................................................................................... 682
17.5 Register Map .............................................................................................................. 683
17.6 Register Descriptions (I2C Master) ............................................................................... 684
17.7 Register Descriptions (I2C Slave) ................................................................................. 697
18 Analog Comparators ............................................................................................ 706
18.1 Block Diagram ............................................................................................................ 706
18.2 Signal Description ....................................................................................................... 707
18.3 Functional Description ................................................................................................. 708
18.3.1 Internal Reference Programming .................................................................................. 708
18.4 Initialization and Configuration ..................................................................................... 710
18.5 Register Map .............................................................................................................. 710
18.6 Register Descriptions .................................................................................................. 710
19 Pin Diagram .......................................................................................................... 718
20 Signal Tables ........................................................................................................ 720
20.1 100-Pin LQFP Package Pin Tables ............................................................................... 720
20.2 108-Pin BGA Package Pin Tables ................................................................................ 743
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21 Operating Characteristics ................................................................................... 767
22 Electrical Characteristics .................................................................................... 768
22.1 DC Characteristics ...................................................................................................... 768
22.1.1 Maximum Ratings ....................................................................................................... 768
22.1.2 Recommended DC Operating Conditions ...................................................................... 768
22.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 769
22.1.4 Hibernation Module Characteristics .............................................................................. 769
22.1.5 Flash Memory Characteristics ...................................................................................... 769
22.1.6 GPIO Module Characteristics ....................................................................................... 770
22.1.7 Current Specifications .................................................................................................. 770
22.2 AC Characteristics ....................................................................................................... 771
22.2.1 Load Conditions .......................................................................................................... 771
22.2.2 Clocks ........................................................................................................................ 771
22.2.3 JTAG and Boundary Scan ............................................................................................ 774
22.2.4 Reset ......................................................................................................................... 775
22.2.5 Sleep Modes ............................................................................................................... 777
22.2.6 Hibernation Module ..................................................................................................... 777
22.2.7 General-Purpose I/O (GPIO) ........................................................................................ 778
22.2.8 External Peripheral Interface (EPI) ............................................................................... 778
22.2.9 Analog-to-Digital Converter .......................................................................................... 783
22.2.10 Synchronous Serial Interface (SSI) ............................................................................... 785
22.2.11 Inter-Integrated Circuit (I2C) Interface ........................................................................... 786
22.2.12 Ethernet Controller ...................................................................................................... 787
22.2.13 Analog Comparator ..................................................................................................... 788
A Boot Loader .......................................................................................................... 789
A.1 Boot Loader Overview ................................................................................................. 789
A.2 Serial Interfaces .......................................................................................................... 789
A.2.1 Serial Configuration ..................................................................................................... 789
A.2.2 Serial Packet Handling ................................................................................................ 790
A.2.3 Serial Commands ........................................................................................................ 791
B ROM DriverLib Functions .................................................................................... 794
B.1 DriverLib Functions Included in the Integrated ROM ...................................................... 794
C Register Quick Reference ................................................................................... 828
D Ordering and Contact Information ..................................................................... 850
D.1 Ordering Information .................................................................................................... 850
D.2 Part Markings .............................................................................................................. 850
D.3 Kits ............................................................................................................................. 851
D.4 Support Information ..................................................................................................... 851
E Package Information ............................................................................................ 852
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List of Figures
Figure 1-1. Stellaris®LM3S1R21 Microcontroller High-Level Block Diagram ............................ 48
Figure 2-1. CPU Block Diagram ............................................................................................. 51
Figure 2-2. TPIU Block Diagram ............................................................................................ 59
Figure 5-1. JTAG Module Block Diagram ................................................................................ 70
Figure 5-2. Test Access Port State Machine ........................................................................... 73
Figure 5-3. IDCODE Register Format ..................................................................................... 79
Figure 5-4. BYPASS Register Format .................................................................................... 79
Figure 5-5. Boundary Scan Register Format ........................................................................... 80
Figure 6-1. Basic RST Configuration ...................................................................................... 83
Figure 6-2. External Circuitry to Extend Power-On Reset ........................................................ 84
Figure 6-3. Reset Circuit Controlled by Switch ........................................................................ 84
Figure 6-4. Power Architecture .............................................................................................. 87
Figure 6-5. Main Clock Tree .................................................................................................. 89
Figure 7-1. Hibernation Module Block Diagram ..................................................................... 173
Figure 7-2. Clock Source Using Crystal ................................................................................ 176
Figure 7-3. Clock Source Using Dedicated Oscillator and VDD3ON Mode .............................. 176
Figure 8-1. Internal Memory Block Diagram .......................................................................... 199
Figure 9-1. μDMA Block Diagram ......................................................................................... 234
Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 240
Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 242
Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 243
Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 245
Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 246
Figure 10-1. Digital I/O Pads ................................................................................................. 296
Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 297
Figure 10-3. GPIODATA Write Example ................................................................................. 298
Figure 10-4. GPIODATA Read Example ................................................................................. 298
Figure 11-1. EPI Block Diagram ............................................................................................. 349
Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 356
Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 357
Figure 11-4. SDRAM Write Cycle ........................................................................................... 358
Figure 11-5. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 365
Figure 11-6. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 365
Figure 11-7. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 1, RDHIGH = 1 ............................................................................................... 366
Figure 11-8. Continuous Read Mode Accesses ...................................................................... 366
Figure 11-9. Write Followed by Read to External FIFO ............................................................ 367
Figure 11-10. Two-Entry FIFO ................................................................................................. 367
Figure 11-11. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 371
Figure 11-12. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,
WRCYC=1 ........................................................................................................ 371
Figure 11-13. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 372
Figure 11-14. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 372
Figure 11-15. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 372
Figure 11-16. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 373
Figure 11-17. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 373
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Figure 11-18. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 373
Figure 11-19. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 373
Figure 11-20. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 374
Figure 11-21. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 374
Figure 11-22. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 375
Figure 12-1. GPTM Module Block Diagram ............................................................................ 420
Figure 12-2. 16-Bit Input Edge-Count Mode Example .............................................................. 427
Figure 12-3. 16-Bit Input Edge-Time Mode Example ............................................................... 429
Figure 12-4. 16-Bit PWM Mode Example ................................................................................ 430
Figure 12-5. Timer Daisy Chain ............................................................................................. 430
Figure 13-1. WDT Module Block Diagram .............................................................................. 467
Figure 14-1. ADC Module Block Diagram ............................................................................... 492
Figure 14-2. Internal Voltage Conversion Result ..................................................................... 497
Figure 14-3. External Voltage Conversion Result .................................................................... 498
Figure 14-4. Differential Sampling Range, V
Figure 14-5. Differential Sampling Range, V
Figure 14-6. Differential Sampling Range, V
Figure 14-7. Internal Temperature Sensor Characteristic ......................................................... 501
Figure 14-8. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 504
Figure 14-9. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 505
Figure 14-10. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 506
Figure 15-1. UART Module Block Diagram ............................................................................. 566
Figure 15-2. UART Character Frame ..................................................................................... 569
Figure 15-3. IrDA Data Modulation ......................................................................................... 571
Figure 15-4. LIN Message ..................................................................................................... 573
Figure 15-5. LIN Synchronization Field ................................................................................... 574
Figure 16-1. SSI Module Block Diagram ................................................................................. 628
Figure 16-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 632
Figure 16-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 632
Figure 16-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 633
Figure 16-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 633
Figure 16-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 634
Figure 16-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 635
Figure 16-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 635
Figure 16-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 636
Figure 16-10. MICROWIRE Frame Format (Single Frame) ........................................................ 637
Figure 16-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 638
Figure 16-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 638
Figure 17-1. I2C Block Diagram ............................................................................................. 670
Figure 17-2. I2C Bus Configuration ........................................................................................ 671
Figure 17-3. START and STOP Conditions ............................................................................. 672
Figure 17-4. Complete Data Transfer with a 7-Bit Address ....................................................... 672
Figure 17-5. R/S Bit in First Byte ............................................................................................ 672
Figure 17-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 673
Figure 17-7. Master Single TRANSMIT .................................................................................. 676
Figure 17-8. Master Single RECEIVE ..................................................................................... 677
Figure 17-9. Master TRANSMIT with Repeated START ........................................................... 678
Figure 17-10. Master RECEIVE with Repeated START ............................................................. 679
IN_ODD
IN_ODD
IN_ODD
= 1.5 V ...................................................... 499
= 0.75 V .................................................... 500
= 2.25 V .................................................... 500
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Figure 17-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 680
Figure 17-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 681
Figure 17-13. Slave Command Sequence ................................................................................ 682
Figure 18-1. Analog Comparator Module Block Diagram ......................................................... 706
Figure 18-2. Structure of Comparator Unit .............................................................................. 708
Figure 18-3. Comparator Internal Reference Structure ............................................................ 709
Figure 19-1. 100-Pin LQFP Package Pin Diagram .................................................................. 718
Figure 19-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 719
Figure 22-1. Load Conditions ................................................................................................ 771
Figure 22-2. JTAG Test Clock Input Timing ............................................................................. 774
Figure 22-3. JTAG Test Access Port (TAP) Timing .................................................................. 775
Figure 22-4. External Reset Timing (RST) .............................................................................. 775
Figure 22-5. Power-On Reset Timing ..................................................................................... 776
Figure 22-6. Brown-Out Reset Timing .................................................................................... 776
Figure 22-7. Software Reset Timing ....................................................................................... 776
Figure 22-8. Watchdog Reset Timing ..................................................................................... 776
Figure 22-9. MOSC Failure Reset Timing ............................................................................... 777
Figure 22-10. Hibernation Module Timing with Internal Oscillator Running in Hibernation ............ 778
Figure 22-11. Hibernation Module Timing with Internal Oscillator Stopped in Hibernation ............ 778
Figure 22-12. SDRAM Initialization and Load Mode Register Timing .......................................... 780
Figure 22-13. SDRAM Read Timing ......................................................................................... 780
Figure 22-14. SDRAM Write Timing ......................................................................................... 781
Figure 22-15. Host-Bus 8/16 Mode Read Timing ...................................................................... 782
Figure 22-16. Host-Bus 8/16 Mode Write Timing ....................................................................... 782
Figure 22-17. General-Purpose Mode Read and Write Timing ................................................... 783
Figure 22-18. General-Purpose Mode iRDY Timing .................................................................. 783
Figure 22-19. ADC Input Equivalency Diagram ......................................................................... 784
Figure 22-20. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 785
Figure 22-21. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 786
Figure 22-22. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 786
Figure 22-23. I2C Timing ......................................................................................................... 786
Figure 22-24. Station Management Write Timing ...................................................................... 787
Figure 22-25. Station Management Read Timing ...................................................................... 787
Figure 22-26. MII Receive Timing ............................................................................................ 788
Figure 22-27. MII Transmit Timing ........................................................................................... 788
Figure E-1. 100-Pin LQFP Package ...................................................................................... 852
Figure E-2. 108-Ball BGA Package ...................................................................................... 854
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Table of Contents
List of Tables
Table 1. Revision History .................................................................................................. 23
Table 2. Documentation Conventions ................................................................................ 27
Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary ............................................................ 52
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary ............................................................ 54
Table 3-1. Memory Map ....................................................................................................... 63
Table 4-1. Exception Types .................................................................................................. 66
Table 4-2. Interrupts ............................................................................................................ 67
Table 5-1. Signals for JTAG_SWD_SWO (100LQFP) ............................................................. 70
Table 5-2. Signals for JTAG_SWD_SWO (108BGA) .............................................................. 71
Table 5-3. JTAG Port Pins State after Power-On Reset or RST assertion ................................ 72
Table 5-4. JTAG Instruction Register Commands ................................................................... 77
Table 6-1. Signals for System Control & Clocks (100LQFP) ................................................... 81
Table 6-2. Signals for System Control & Clocks (108BGA) ..................................................... 81
Table 6-3. Reset Sources .................................................................................................... 82
Table 6-4. Clock Source Options .......................................................................................... 88
Table 6-5. Possible System Clock Frequencies Using the SYSDIV Field ................................. 90
Table 6-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field ............ 90
Table 6-7. Examples of Possible System Clock Frequencies with DIV400=1 ........................... 91
Table 6-8. System Control Register Map ............................................................................... 95
Table 6-9. RCC2 Fields that Override RCC fields ................................................................. 115
Table 7-1. Signals for Hibernate (100LQFP) ........................................................................ 173
Table 7-2. Signals for Hibernate (108BGA) .......................................................................... 174
Table 7-3. Hibernation Module Clock Operation ................................................................... 179
Table 7-4. Hibernation Module Register Map ....................................................................... 182
Table 8-1. Flash Memory Protection Policy Combinations .................................................... 201
Table 8-2. User-Programmable Flash Memory Resident Registers ....................................... 204
Table 8-3. Flash Register Map ............................................................................................ 205
Table 9-1. μDMA Channel Assignments .............................................................................. 235
Table 9-2. Request Type Support ....................................................................................... 236
Table 9-3. Control Structure Memory Map ........................................................................... 238
Table 9-4. Channel Control Structure .................................................................................. 238
Table 9-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 247
Table 9-6. μDMA Interrupt Assignments .............................................................................. 248
Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 249
Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 249
Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 250
Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 251
Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 252
Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 253
Table 9-13. μDMA Register Map .......................................................................................... 254
Table 10-1. GPIO Pins With Non-Zero Reset Values .............................................................. 292
Table 10-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 292
Table 10-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 294
Table 10-4. GPIO Pad Configuration Examples ..................................................................... 300
Table 10-5. GPIO Interrupt Configuration Example ................................................................ 301
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Stellaris® LM3S1R21 Microcontroller
Table 10-6. GPIO Pins With Non-Zero Reset Values .............................................................. 302
Table 10-7. GPIO Register Map ........................................................................................... 303
Table 10-8. GPIO Pins With Non-Zero Reset Values .............................................................. 315
Table 10-9. GPIO Pins With Non-Zero Reset Values .............................................................. 321
Table 10-10. GPIO Pins With Non-Zero Reset Values .............................................................. 323
Table 10-11. GPIO Pins With Non-Zero Reset Values .............................................................. 326
Table 10-12. GPIO Pins With Non-Zero Reset Values .............................................................. 333
Table 11-1. Signals for External Peripheral Interface (100LQFP) ............................................ 349
Table 11-2. Signals for External Peripheral Interface (108BGA) .............................................. 350
Table 11-3. EPI SDRAM Signal Connections ......................................................................... 355
Table 11-4. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 359
Table 11-5. EPI Host-Bus 8 Signal Connections .................................................................... 360
Table 11-6. EPI Host-Bus 16 Signal Connections .................................................................. 361
Table 11-7. EPI General Purpose Signal Connections ........................................................... 369
Table 11-8. External Peripheral Interface (EPI) Register Map ................................................. 375
Table 12-1. Available CCP Pins ............................................................................................ 420
Table 12-2. Signals for General-Purpose Timers (100LQFP) .................................................. 421
Table 12-3. Signals for General-Purpose Timers (108BGA) .................................................... 422
Table 12-4. 16-Bit Timer With Prescaler Configurations ......................................................... 426
Table 12-5. Timers Register Map .......................................................................................... 435
Table 13-1. Watchdog Timers Register Map .......................................................................... 469
Table 14-1. Signals for ADC (100LQFP) ............................................................................... 492
Table 14-2. Signals for ADC (108BGA) ................................................................................. 493
Table 14-3. Samples and FIFO Depth of Sequencers ............................................................ 494
Table 14-4. Differential Sampling Pairs ................................................................................. 498
Table 14-5. ADC Register Map ............................................................................................. 507
Table 15-1. Signals for UART (100LQFP) ............................................................................. 567
Table 15-2. Signals for UART (108BGA) ............................................................................... 567
Table 15-3. Flow Control Mode ............................................................................................. 572
Table 15-4. UART Register Map ........................................................................................... 577
Table 16-1. Signals for SSI (100LQFP) ................................................................................. 629
Table 16-2. Signals for SSI (108BGA) ................................................................................... 629
Table 16-3. SSI Register Map .............................................................................................. 640
Table 17-1. Signals for I2C (100LQFP) ................................................................................. 670
Table 17-2. Signals for I2C (108BGA) ................................................................................... 670
Table 17-3. Examples of I2C Master Timer Period versus Speed Mode ................................... 674
Table 17-4. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 683
Table 17-5. Write Field Decoding for I2CMCS[3:0] Field ......................................................... 689
Table 18-1. Signals for Analog Comparators (100LQFP) ........................................................ 707
Table 18-2. Signals for Analog Comparators (108BGA) .......................................................... 707
Table 18-3. Internal Reference Voltage and ACREFCTL Field Values ..................................... 709
Table 18-4. Analog Comparators Register Map ..................................................................... 710
Table 20-1. GPIO Pins With Default Alternate Functions ........................................................ 720
Table 20-2. Signals by Pin Number ....................................................................................... 720
Table 20-3. Signals by Signal Name ..................................................................................... 728
Table 20-4. Signals by Function, Except for GPIO ................................................................. 736
Table 20-5. GPIO Pins and Alternate Functions ..................................................................... 741
Table 20-6. Signals by Pin Number ....................................................................................... 743
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Table of Contents
Table 20-7. Signals by Signal Name ..................................................................................... 752
Table 20-8. Signals by Function, Except for GPIO ................................................................. 759
Table 20-9. GPIO Pins and Alternate Functions ..................................................................... 764
Table 21-1. Temperature Characteristics ............................................................................... 767
Table 21-2. Thermal Characteristics ..................................................................................... 767
Table 21-3. ESD Absolute Maximum Ratings ........................................................................ 767
Table 22-1. Maximum Ratings .............................................................................................. 768
Table 22-2. Recommended DC Operating Conditions ............................................................ 768
Table 22-3. LDO Regulator Characteristics ........................................................................... 769
Table 22-4. Hibernation Module DC Characteristics ............................................................... 769
Table 22-5. Flash Memory Characteristics ............................................................................ 769
Table 22-6. GPIO Module DC Characteristics ........................................................................ 770
Table 22-7. Preliminary Current Consumption ....................................................................... 770
Table 22-8. Phase Locked Loop (PLL) Characteristics ........................................................... 771
Table 22-9. Actual PLL Frequency ........................................................................................ 772
Table 22-10. PIOSC Clock Characteristics .............................................................................. 772
Table 22-11. 30-kHz Clock Characteristics .............................................................................. 772
Table 22-12. Hibernation Clock Characteristics ....................................................................... 772
Table 22-13. HIB Oscillator Input Characteristics ..................................................................... 773
Table 22-14. Main Oscillator Clock Characteristics .................................................................. 773
Table 22-15. MOSC Oscillator Input Characteristics ................................................................ 773
Table 22-16. System Clock Characteristics with ADC Operation ............................................... 773
Table 22-17. JTAG Characteristics ......................................................................................... 774
Table 22-18. Reset Characteristics ......................................................................................... 775
Table 22-19. Sleep Modes AC Characteristics ......................................................................... 777
Table 22-20. Hibernation Module AC Characteristics ............................................................... 777
Table 22-21. GPIO Characteristics ......................................................................................... 778
Table 22-22. EPI SDRAM Characteristics ............................................................................... 779
Table 22-23. EPI SDRAM Interface Characteristics ................................................................. 779
Table 22-24. EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics ................................... 781
Table 22-25. EPI General-Purpose Interface Characteristics .................................................... 782
Table 22-26. ADC Characteristics ........................................................................................... 783
Table 22-27. ADC Module External Reference Characteristics ................................................. 784
Table 22-28. ADC Module Internal Reference Characteristics .................................................. 785
Table 22-29. SSI Characteristics ............................................................................................ 785
Table 22-30. Ethernet Station Management ............................................................................ 787
Table 22-31. Ethernet MII ...................................................................................................... 787
Table 22-32. Analog Comparator Characteristics ..................................................................... 788
Table 22-33. Analog Comparator Voltage Reference Characteristics ........................................ 788
Table D-1. Part Ordering Information ................................................................................... 850
Texas Instruments-Advance Information
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Stellaris® LM3S1R21 Microcontroller
List of Registers
System Control .............................................................................................................................. 81
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 97
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 99
Register 3: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 100
Register 4: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 102
Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 104
Register 6: Reset Cause (RESC), offset 0x05C ................................................................................ 106
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 108
Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 112
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 113
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 115
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 118
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 119
Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 121
Register 14: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 123
Register 15: Device Identification 1 (DID1), offset 0x004 ..................................................................... 124
Register 16: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 126
Register 17: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 127
Register 18: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 129
Register 19: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 131
Register 20: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 133
Register 21: Device Capabilities 5 (DC5), offset 0x020 ........................................................................ 135
Register 22: Device Capabilities 6 (DC6), offset 0x024 ........................................................................ 136
Register 23: Device Capabilities 7 (DC7), offset 0x028 ........................................................................ 137
Register 24: Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................ 141
Register 25: Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 ................................. 142
Register 26: Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 ............................................. 143
Register 27: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 144
Register 28: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 146
Register 29: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 148
Register 30: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 150
Register 31: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 153
Register 32: Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 156
Register 33: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 159
Register 34: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 161
Register 35: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 163
Register 36: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 165
Register 37: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 167
Register 38: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 170
Hibernation Module ..................................................................................................................... 172
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 183
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 184
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 185
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 186
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 187
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Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 190
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 192
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 194
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 196
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 197
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 198
Internal Memory ........................................................................................................................... 199
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 207
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 208
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 209
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 211
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 212
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 213
Register 7: Flash Memory Control 2 (FMC2), offset 0x020 ................................................................. 214
Register 8: Flash Write Buffer Valid (FWBVAL), offset 0x030 ............................................................. 215
Register 9: Flash Write Buffer n (FWBn), offset 0x100 - 0x17C .......................................................... 216
Register 10: Flash Control (FCTL), offset 0x0F8 ................................................................................. 217
Register 11: ROM Control (RMCTL), offset 0x0F0 .............................................................................. 218
Register 12: ROM Version Register (RMVER), offset 0x0F4 ................................................................ 219
Register 13: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 220
Register 14: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 221
Register 15: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 222
Register 16: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 223
Register 17: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 224
Register 18: User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 225
Register 19: User Register 3 (USER_REG3), offset 0x1EC ................................................................. 226
Register 20: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 227
Register 21: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 228
Register 22: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 229
Register 23: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 230
Register 24: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 231
Register 25: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 232
Micro Direct Memory Access (μDMA) ........................................................................................ 233
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 256
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 257
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 258
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 263
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 265
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 266
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 267
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 268
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 269
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 270
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 271
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 272
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 273
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 274
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 275
Texas Instruments-Advance Information
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Stellaris® LM3S1R21 Microcontroller
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 276
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 277
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 278
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 279
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 280
Register 21: DMA Channel Alternate Select (DMACHALT), offset 0x500 .............................................. 281
Register 22: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 282
Register 23: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 283
Register 24: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 284
Register 25: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 285
Register 26: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 286
Register 27: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 287
Register 28: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 288
Register 29: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 289
Register 30: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 290
General-Purpose Input/Outputs (GPIOs) ................................................................................... 291
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 305
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 306
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 307
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 308
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 309
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 310
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 311
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 312
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 314
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 315
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 317
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 318
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 319
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 320
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 321
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 323
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 325
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 326
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 328
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 329
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 331
Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 333
Register 23: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 335
Register 24: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 336
Register 25: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 337
Register 26: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 338
Register 27: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 339
Register 28: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 340
Register 29: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 341
Register 30: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 342
Register 31: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 343
Register 32: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 344
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Table of Contents
Register 33: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 345
Register 34: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 346
External Peripheral Interface (EPI) ............................................................................................. 347
Register 1: EPI Configuration (EPICFG), offset 0x000 ....................................................................... 377
Register 2: EPI Main Baud Rate (EPIBAUD), offset 0x004 ................................................................. 379
Register 3: EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 .............................................. 381
Register 4: EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 ............................................... 383
Register 5: EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 ........................................... 387
Register 6: EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 ........................................ 391
Register 7: EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 .......................................... 395
Register 8: EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 ....................................... 397
Register 9: EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014 ................................... 399
Register 10: EPI Address Map (EPIADDRMAP), offset 0x01C ............................................................. 400
Register 11: EPI Read Size 0 (EPIRSIZE0), offset 0x020 .................................................................... 402
Register 12: EPI Read Size 1 (EPIRSIZE1), offset 0x030 .................................................................... 402
Register 13: EPI Read Address 0 (EPIRADDR0), offset 0x024 ............................................................ 403
Register 14: EPI Read Address 1 (EPIRADDR1), offset 0x034 ............................................................ 403
Register 15: EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 ............................................. 404
Register 16: EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 ............................................. 404
Register 17: EPI Status (EPISTAT), offset 0x060 ................................................................................ 406
Register 18: EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ...................................................... 408
Register 19: EPI Read FIFO (EPIREADFIFO), offset 0x070 ................................................................ 409
Register 20: EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 .................................................... 409
Register 21: EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 .................................................... 409
Register 22: EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ................................................... 409
Register 23: EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 .................................................... 409
Register 24: EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 .................................................... 409
Register 25: EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 .................................................... 409
Register 26: EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ................................................... 409
Register 27: EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................ 410
Register 28: EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ...................................................... 412
Register 29: EPI Interrupt Mask (EPIIM), offset 0x210 ......................................................................... 413
Register 30: EPI Raw Interrupt Status (EPIRIS), offset 0x214 .............................................................. 414
Register 31: EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................ 416
Register 32: EPI Error Interrupt Status and Clear (EPIEISC), offset 0x21C ........................................... 417
General-Purpose Timers ............................................................................................................. 419
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 436
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 437
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 439
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 441
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 444
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 446
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 449
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 452
Register 9: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 454
Register 10: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 455
Register 11: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 456
Register 12: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 457
Texas Instruments-Advance Information
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Stellaris® LM3S1R21 Microcontroller
Register 13: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 458
Register 14: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 459
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 460
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 461
Register 17: GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 462
Register 18: GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 463
Register 19: GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 464
Register 20: GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 465
Watchdog Timers ......................................................................................................................... 466
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 470
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 471
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 472
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 474
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 475
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 476
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 477
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 478
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 479
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 480
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 481
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 482
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 483
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 484
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 485
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 486
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 487
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 488
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 489
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 490
Analog-to-Digital Converter (ADC) ............................................................................................. 491
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 510
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 511
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 513
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 515
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 518
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 520
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 523
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 524
Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 526
Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 527
Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 529
Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 530
Register 13: ADC Control (ADCCTL), offset 0x038 ............................................................................. 532
Register 14: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 533
Register 15: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 535
Register 16: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 538
Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 538
Register 18: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 538
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Register 19: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 538
Register 20: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 539
Register 21: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 539
Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 539
Register 23: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 539
Register 24: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 541
Register 25: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 543
Register 26: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 545
Register 27: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 545
Register 28: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 546
Register 29: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 546
Register 30: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 548
Register 31: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 548
Register 32: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 549
Register 33: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 549
Register 34: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 551
Register 35: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 552
Register 36: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 553
Register 37: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 554
Register 38: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 555
Register 39: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 560
Register 40: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 560
Register 41: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 560
Register 42: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 560
Register 43: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 560
Register 44: ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 ....................................... 560
Register 45: ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 ....................................... 560
Register 46: ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ...................................... 560
Register 47: ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 ....................................... 564
Register 48: ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 ....................................... 564
Register 49: ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 ....................................... 564
Register 50: ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ...................................... 564
Register 51: ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 ....................................... 564
Register 52: ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 ....................................... 564
Register 53: ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 ....................................... 564
Register 54: ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ...................................... 564
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 565
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 579
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 581
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 584
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 587
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 588
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 589
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 590
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 592
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 596
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 598
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 602
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Stellaris® LM3S1R21 Microcontroller
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 606
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 609
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 611
Register 15: UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 612
Register 16: UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 613
Register 17: UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 614
Register 18: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 615
Register 19: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 616
Register 20: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 617
Register 21: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 618
Register 22: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 619
Register 23: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 620
Register 24: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 621
Register 25: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 622
Register 26: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 623
Register 27: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 624
Register 28: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 625
Register 29: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 626
Synchronous Serial Interface (SSI) ............................................................................................ 627
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 642
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 644
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 646
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 647
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 649
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 650
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 651
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 653
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 655
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 656
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 657
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 658
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 659
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 660
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 661
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 662
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 663
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 664
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 665
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 666
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 667
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 668
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 669
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 685
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 686
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 691
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 692
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 693
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 694
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Table of Contents
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 695
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 696
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 697
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 698
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 699
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 701
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 702
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 703
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 704
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 705
Analog Comparators ................................................................................................................... 706
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 711
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 712
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 713
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 714
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 715
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 715
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 716
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 716
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Revision History
The revision history table notes changes made between the indicated revisions of the LM3S1R21
data sheet.
Table 1. Revision History
DescriptionRevisionDate
Started tracking revision history.5285May 2009
5779June 2009
■ In System Control chapter, clarified power-on reset and external reset pin descriptions in "Reset
■ Added missing comparator output pin bits to DC3 register; reset value changed as well.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0
■ In Request Type Support table in DMA chapter, corrected general-purpose timer row.
■ In General-Purpose Timers chapter, clarified DMA operation.
Stellaris® LM3S1R21 Microcontroller
Sources" section.
registers.
■ Added table "Preliminary Current Consumption" to Characteristics chapter.
■ Corrected Nom and Max values in "Hibernation Detailed Current Specifications" table.
■ Corrected Nom and Max values in EPI Characteristics table.
■ Added "CSn to output invalid" parameter to EPI table "EPI Host-Bus 8 and Host-Bus 16 Interface
Characteristics" and figure "Host-Bus 8/16 Mode Read Timing".
■ Corrected INL, DNL, OFF and GAIN values in ADC Characteristics table.
■ Updated ROM DriverLib appendix with RevC0 functions.
■ Updated part ordering numbers.
■ Additional minor data sheet clarifications and corrections.
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23February 09, 2010
Revision History
Table 1. Revision History (continued)
DescriptionRevisionDate
5930July 2009
■ Added "Non-Blocking Read Cycle", "Normal Read Cycle", and "Write Cycle" sections to EPI chapter.
■ Corrected values for MAXADC0SPD and MAXADC1SPD bits in DC1, RCGC0, SCGC0, and DCGC0
registers.
■ Corrected figure "TI Synchronous Serial Frame Format (Single Transfer)".
■ Changed HIB pin from type TTL to type OD.
■ Made a number of corrections to the Electrical Characteristics chapter:
– Deleted V
BAT
and V
parameters from and added footnotes to Recommended DC Operating
REFA
Conditions table.
– Modified Hibernation Module DC Characteristics table.
– Deleted Nominal and Maximum Current Specifications section.
– Modified EPI SDRAM Characteristics table:
• Changed t
• Changed t
– Changed values for t
EPIR
EPIF
to t
to t
SDRAMR
SDRAMF
, t
COV
and deleted values for 2-mA and 4-mA drive.
and deleted values for 2-mA and 4-mA drive.
COI
, and t
parameters in EPI SDRAM Interface Characteristics
COT
table.
– Deleted SDRAM Read Command Timing, SDRAM Write Command Timing, SDRAM Write Burst
Timing, SDRAM Precharge Command Timing and SDRAM CAS Latency Timing figures and
replaced with SDRAM Read Timing and SDRAM Write Timing figures.
– Modified Host-Bus 8/16 Mode Write Timing figure.
– Modified General-Purpose Mode Read and Write Timing figure.
– Modified values for tDVand tDIparameters, and deleted tODparameter from EPI General-Purpose
Interface Characteristics figure.
– Major changes to ADC Characteristics tables, including adding additonal tables and diagram.
■ Corrected ordering part numbers.
■ Additional minor data sheet clarifications and corrections.
Texas Instruments-Advance Information
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Table 1. Revision History (continued)
DescriptionRevisionDate
6458October 2009
■ Released new 1000, 3000, 5000 and 9000 series Stellaris®devices.
■ The IDCODE value was corrected to be 0x4BA0.0477.
■ Clarified that the NMISET bit in the ICSR register in the NVIC is also a source for NMI.
■ Clarified the use of the LDO.
■ To clarify clock operation, reorganized clocking section, changed the USEFRACT bit to the DIV400
bit and the FRACT bit to the SYSDIV2LSB bit in the RCC2 register, added tables, and rewrote
descriptions.
■ Corrected bit description of the DSDIVORIDE field in the DSLPCLKCFG register.
■ Removed the DSFLASHCFG register at System Control offset 0x14C as it does not function correctly.
■ Removed the MAXADC1SPD and MAXADC0SPD fields from the DCGC0 as they have no function in
deep-sleep mode.
■ Corrected address offsets for the Flash Write Buffer (FWBn) registers.
■ Added Flash Control (FCTL) register at Internal memory offset 0x0F8 to help control frequent
power cycling when hibernation is not used.
Stellaris® LM3S1R21 Microcontroller
■ Changed the name of the EPI channels for clarification: EPI0_TX became EPI0_WFIFO and EPI0_RX
became EPI0_NBRFIFO. This change was also made in the DC7 bit descriptions.
■ Removed the DMACHIS register at DMA module offset 0x504 as it does not function correctly.
■ Corrected alternate channel assignments for the µDMA controller.
■ Major improvements to the EPI chapter.
■ EPISDRAMCFG2 register was deleted as its function is not needed.
■ Clarified PWM source for ADC triggering
■ Changed SSI set up and hold times to be expressed in system clocks, not ns.
■ Updated Electrical Characteristics chapter with latest data. Changes were made to Hibernation,
ADC and EPI content.
■ Additional minor data sheet clarifications and corrections.
Texas Instruments-Advance Information
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Revision History
Table 1. Revision History (continued)
DescriptionRevisionDate
6790February 2010
■ Added 108-ball BGA package.
■ In "System Control" chapter:
– Clarified functional description for external reset and brown-out reset.
– Clarified Debug Access Port operation after Sleep modes.
– Corrected the reset value of the Run-Mode Clock Configuration 2 (RCC2) register.
■ In "Internal Memory" chapter, clarified wording on Flash memory access errors and added a section
on interrupts to the Flash memory description.
■ In "External Peripheral Interface" chapter:
– Added clarification about byte selects and dual chip selects.
– Added timing diagrams for continuous-read mode (formerly SRAM mode).
– Corrected reset values of EPI Write FIFO Count (EPIWFIFOCNT) and EPI Raw Interrupt
Status (EPIRIS) registers.
■ Added clarification about timer operating modes and added register descriptions for the GPTM
Timer n Prescale Match (GPTMTnPMR) registers.
■ Clarified register descriptions for GPTM Timer A Value (GPTMTAV) and GPTM Timer B Value
(GPTMTBV) registers.
■ Corrected the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers.
■ Added ADC Sample Phase Control (ADCSPC) register at offset 0x24.
■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■ Added Session Disconnect (DISCON) bit to the USB General Interrupt Status (USBIS) and
USB Interrupt Enable (USBIE) registers.
■ Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■ Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
– Added table entry for VDD3ON power consumption to Table 22-7 on page 770.
■ Added additional DriverLib functions to appendix.
Texas Instruments-Advance Information
February 09, 201026
About This Document
This data sheet provides reference information for the LM3S1R21 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Stellaris®web site at www.ti.com/stellaris:
Stellaris® LM3S1R21 Microcontroller
■
ARM® Cortex™-M3 Technical Reference Manual
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
■
Stellaris® Peripheral Driver Library User's Guide
■
Stellaris® ROM User’s Guide
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 2 on page 27.
Table 2. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 63.
Texas Instruments-Advance Information
27February 09, 2010
About This Document
Table 2. Documentation Conventions (continued)
Register N
reserved
yy:xx
Register Bit/Field
Types
R/W1C
R/W1S
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
MeaningNotation
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNALand SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Texas Instruments-Advance Information
February 09, 201028
Table 2. Documentation Conventions (continued)
MeaningNotation
0x
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Stellaris® LM3S1R21 Microcontroller
Texas Instruments-Advance Information
29February 09, 2010
Architectural Overview
1 Architectural Overview
Texas Instruments is the industry leader in bringing 32-bit capabilities and the full benefits of ARM®
Cortex-M3™-based microcontrollers to the broadest reach of the microcontroller market. For current
users of 8- and 16-bit MCUs, Stellaris®with Cortex-M3 offers a direct path to the strongest ecosystem
of development tools, software and knowledge in the industry. Designers who migrate to Stellaris
benefit from great tools, small code footprint and outstanding performance. Even more important,
designers can enter the ARM ecosystem with full confidence in a compatible roadmap from $1 to
1 GHz. For users of current 32-bit MCUs, the Stellaris®family offers the industry’s first implementation
of Cortex-M3 and the Thumb-2 instruction set. With blazingly-fast responsiveness, Thumb-2
technology combines both 16-bit and 32-bit instructions to deliver the best balance of code density
and performance. Thumb-2 uses 26 percent less memory than pure 32-bit code to reduce system
cost while delivering 25 percent better performance. The Texas Instruments Stellaris®family of
microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit
computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver
customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package
with a small footprint.
The LM3S1R21 microcontroller has the following features:
®
■ ARM® Cortex™-M3 Processor Core
– 80-MHz operation; 100 DMIPS performance
– ARM Cortex SysTick Timer
– Nested Vectored Interrupt Controller (NVIC)
■ On-Chip Memory
– 256 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance
above 50 MHz
– 48 KB single-cycle SRAM
– Internal ROM loaded with StellarisWare®software:
• Stellaris®Peripheral Driver Library
• Stellaris®Boot Loader
■ External Peripheral Interface (EPI)
– 8/16/32-bit dedicated parallel bus for external peripherals
– Supports SDRAM, SRAM/Flash memory, FPGAs, CPLDs
■ Advanced Serial Integration
– Three UARTs with IrDA and ISO 7816 support (one UART with full modem controls)
– Two I2C modules
– Two Synchronous Serial Interface modules (SSI)
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Texas Instruments-Advance Information
Stellaris® LM3S1R21 Microcontroller
■ System Integration
– Direct Memory Access Controller (DMA)
– System control and clocks including on-chip precision 16-MHz oscillator
– Four 32-bit timers (up to eight 16-bit)
– Eight Capture Compare PWM pins (CCP)
– Lower-power battery-backed hibernation module
– Real-Time Clock
– Two Watchdog Timers
• One timer runs off the main oscillator
• One timer runs off the precision internal oscillator
– Up to 67 GPIOs, depending on configuration
• Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
• Independently configurable to 2, 4 or 8 mA drive capability
• Up to 4 GPIOs can have 18 mA drive capability
■ Analog
– 10-bit Analog-to-Digital Converter (ADC) with eight analog input channels and sample rate
of one million samples/second
– Two analog comparators
– Eight digital comparators
– On-chip voltage regulator
■ JTAG and ARM Serial Wire Debug (SWD)
■ 100-pin LQFP and 108-ball BGA package
■ Industrial (-40°C to 85°C) Temperature Range
The Stellaris®LM3S5000 series, designed for Controller Area Network (CAN) applications, extends
the Stellaris®family with Bosch CAN networking technology combined with USB 2.0 Full or Low
Speed On-The-Go (OTG) or Host/Device capabilities. The LM3S5000 microcontrollers are perfect
for cost-effective embedded control applications requiring industrial connectivity.
The LM3S1R21 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S1R21 microcontroller features
a battery-backed Hibernation module to efficiently power down the LM3S1R21 to a low-power state
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Architectural Overview
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S1R21 microcontroller perfectly for
battery applications.
In addition, the LM3S1R21 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S1R21 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact Information” on page
850 for ordering information for Stellaris®family devices.
1.1 Functional Overview
The following sections provide an overview of the features of the LM3S1R21 microcontroller. The
page number in parentheses indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 850.
1.1.1 ARM Cortex™-M3
The following sections provide an overview of the ARM Cortex™-M3 processor core and instruction
set, the integrated System Timer (SysTick) and the Nested Vectored Interrupt Controller.
1.1.1.1 Processor Core (see page 50)
All members of the Stellaris®product family, including the LM3S1R21 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
■ 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set, delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices; typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
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■ Hardware division and fast multiplier
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage
■ Ultra-low power consumption with integrated sleep modes
■ 80-MHz operation
■ 1.25 DMIPS/MHz
“ARM Cortex-M3 Processor Core” on page 50 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.1.1.2 System Timer (SysTick) (see page 60)
ARM Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit,
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine
■ A high-speed alarm timer using the system clock
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter
■ A simple counter used to measure time to completion and time used
■ An internal clock-source control based on missing/meeting durations. The COUNTFLAG field in
the SysTick Control and Status register can be used to determine if an action completed within
a set duration, as part of a dynamic clock management control loop
1.1.1.3 Nested Vectored Interrupt Controller (NVIC) (see page 66)
The LM3S1R21 controller includes the ARM Nested Vectored Interrupt Controller (NVIC). The NVIC
and Cortex-M3 prioritize and handle all exceptions in Handler Mode. The processor state is
automatically stored to the stack on an exception and automatically restored from the stack at the
end of the Interrupt Service Routine (ISR). The interrupt vector is fetched in parallel to the state
saving, enabling efficient interrupt entry. The processor supports tail-chaining, meaning that
back-to-back interrupts can be performed without the overhead of state saving and restoration.
Software can set eight priority levels on 7 exceptions (system handlers) and 37 interrupts.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
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■ External non-maskable interrupt signal (NMI) available for immediate execution of NMI handler
for safety critical applications
■ Dynamically reprioritizable interrupts
■ Exceptional interrupt handling via hardware implementation of required register manipulations
“Interrupts” on page 66 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.1.2 On-Chip Memory
The following sections describe the on-chip memory modules.
1.1.2.1 SRAM (see page 200)
The LM3S1R21 microcontroller provides 48 KB of single-cycle on-chip SRAM. The internal SRAM
of the Stellaris®devices is located at offset 0x2000.0000 of the device memory map.
Because read-modify-write (RMW) operations are very time consuming, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Data can be transferred to and from the SRAM using the Micro Direct Memory Access Controller
(µDMA).
1.1.2.2 Flash Memory (see page 200)
The LM3S1R21 microcontroller provides 256 KB of single-cycle on-chip Flash memory (above 50
MHz, the Flash memory can be accessed in a single cycle as long as the code is linear; branches
incur a one-cycle stall). The Flash memory is organized as a set of 2-KB blocks that can be
individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s.
These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can
be marked as read-only or execute-only, providing different levels of code protection. Read-only
blocks cannot be erased or programmed, protecting the contents of those blocks from being modified.
Execute-only blocks cannot be erased or programmed, and can only be read by the controller
instruction fetch mechanism, protecting the contents of those blocks from being read by either the
controller or by a debugger.
1.1.2.3 ROM (see page 794)
The LM3S1R21 ROM is preprogrammed with the following software and programs:
■ Stellaris®Peripheral Driver Library
■ Stellaris®Boot Loader
The Stellaris®Peripheral Driver Library is a royalty-free software library for controlling on-chip
peripherals with a boot-loader capability. The library performs both peripheral initialization and
control functions, with a choice of polled or interrupt-driven peripheral support. In addition, the library
is designed to take full advantage of the stellar interrupt performance of the ARM® Cortex™-M3
core. No special pragmas or custom assembly code prologue/epilogue functions are required. For
applications that require in-field programmability, the royalty-free Stellaris®Boot Loader can act as
an application loader and support in-field firmware updates.
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1.1.3 External Peripheral Interface (see page 347)
The External Peripheral Interface (EPI) provides access to external devices using a parallel path.
Unlike communications peripherals such as SSI, UART, and I2C, the EPI is designed to act like a
bus to external peripherals and memory.
The EPI has the following features:
■ 8/16/32-bit dedicated parallel bus for external peripherals and memory
■ Memory interface supports contiguous memory access independent of data bus width, thus
enabling code execution directly from SDRAM, SRAM and Flash memory
■ Blocking and non-blocking reads
■ Separates processor from timing details through use of an internal write FIFO
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for read and write
– Read channel request asserted by programmable levels on the internal non-blocking read
FIFO (NBRFIFO)
Stellaris® LM3S1R21 Microcontroller
– Write channel request asserted by empty on the internal write FIFO (WFIFO)
The EPI supports three primary functional modes: Synchronous Dynamic Random Access Memory
(SDRAM) mode, Traditional Host-Bus mode, and General-Purpose mode. The EPI module also
provides custom GPIOs; however, unlike regular GPIOs, the EPI module uses a FIFO in the same
way as a communication mechanism and is speed-controlled using clocking.
■ Synchronous Dynamic Random Access Memory (SDRAM)
– Supports x16 (single data rate) SDRAM at up to 50 MHz
– Supports low-cost SDRAMs up to 64 MB (512 megabits)
– Includes automatic refresh and access to all banks/rows
– Includes a Sleep/Standby mode to keep contents active with minimal power draw
– Multiplexed address/data interface for reduced pin count
■ Host-bus
– Traditional x8 and x16 MCU bus interface capabilities
– Similar device compatibility options as PIC, ATmega, 8051, and others
– Access to SRAM, NOR Flash memory, and other devices, with up to 1 MB of addressing in
unmultiplexed mode and 256 MB in multiplexed mode (512 MB in Host-Bus 16 mode with
no byte selects)
– Support of both muxed and de-muxed address and data
– Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant,
with support for external FIFO (XFIFO) EMPTY and FULL signals
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– Speed controlled, with read and write data wait-state counters
– Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn
– Manual chip-enable (or use extra address pins)
■ General Purpose
– Wide parallel interfaces for fast communications with CPLDs and FPGAs
– Data widths up to 32-bits
– Data rates up to 150 MB/second
– Optional “address” sizes from 4-bits to 16-bits
– Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable
input
■ General parallel GPIO
– 1 to 32 bits, FIFOed with speed control
– Useful for custom peripherals or for digital data acquisition and actuator controls
1.1.4 Serial Communications Peripherals
The LM3S1R21 controller supports both asynchronous and synchronous serial communications
with:
■ Three UARTs with IrDA and ISO 7816 support (one UART with full modem controls)
■ Two I2C modules
■ Two Synchronous Serial Interface Modules (SSI)
The following sections provide more detail on each of these communications functions.
1.1.4.1 UART (see page 565)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S1R21 controller includes three fully programmable 16C550-type UARTs. Although the
functionality is similar to a 16C550 UART, this UART design is not register compatible. The UART
can generate individually masked interrupts from the Rx, Tx, modem status, and error conditions.
The module generates a single combined interrupt when any of the interrupts are asserted and are
unmasked.
The three UARTs have the following features:
■ Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
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■ Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
■ Standard asynchronous communication bits for start, stop, and parity
■ False-start bit detection
■ Line-break generation and detection
■ Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation/detection
– 1 or 2 stop bit generation
■ IrDA serial-IR (SIR) encoder/decoder providing
– Programmable use of IrDA Serial Infrared (SIR) or UART input/output
– Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
– Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
– Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
■ Support for communication with ISO 7816 smart cards
■ Full modem handshake support (on UART1)
■ LIN protocol support
■ Standard FIFO-level and End-of-Transmission interrupts
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
1.1.4.2 I2C (see page 669)
The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices
such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
The I2C bus may also be used for system testing and diagnostic purposes in product development
and manufacture.
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Each device on the I2C bus can be designated as either a master or a slave. Each I2C module
supports both sending and receiving data as either a master or a slave and can operate
simultaneously as both a master and a slave. Both the I2C master and slave can generate interrupts.
The LM3S1R21 controller includes two I2C modules with the following features:
■ Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
■ Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
■ Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
■ Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due
to an error)
– Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
■ Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing
mode
1.1.4.3 SSI (see page 627)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface that converts
data between parallel and serial. The SSI module performs serial-to-parallel conversion on data
received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral
device. The SSI module can be configured as either a master or slave device. As a slave device,
the SSI module can also be configured to disable its output, which allows a master device to be
coupled with multiple slave devices. The TX and RX paths are buffered with separate internal FIFOs.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
The LM3S1R21 controller includes two SSI modules with the following features:
■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
■ Master or slave operation
■ Programmable clock bit rate and prescaler
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■ Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
■ Programmable data frame size from 4 to 16 bits
■ Internal loopback test mode for diagnostic/debug testing
■ Standard FIFO-based interrupts and End-of-Transmission interrupt
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
– Transmit single request asserted when there is space in the FIFO; burst request asserted
when FIFO contains 4 entries
1.1.5 System Integration
The LM3S1R21 controller provides a variety of standard system functions integrated into the device,
including:
Stellaris® LM3S1R21 Microcontroller
■ Micro Direct Memory Access Controller (µDMA)
■ System control and clocks including on-chip precision 16-MHz oscillator
■ ARM Cortex SysTick Timer
■ Four 32-bit timers (up to eight 16-bit)
■ Eight Capture Compare PWM pins (CCP)
■ Lower-power battery-backed hibernation module
■ Real-Time Clock
■ Two Watchdog Timers
■ Up to 67 GPIOs, depending on configuration
– Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
– Independently configurable to 2, 4 or 8 mA drive capability
– Up to 4 GPIOs can have 18 mA drive capability
The following sections provide more detail on each of these functions.
1.1.5.1 Direct Memory Access (see page 233)
The LM3S1R21 microcontroller includes a Direct Memory Access (DMA) controller, known as
micro-DMA (μDMA). The μDMA controller provides a way to offload data transfer tasks from the
Cortex-M3 processor, allowing for more efficient use of the processor and the available bus
bandwidth. The μDMA controller can perform transfers between memory and peripherals. It has
dedicated channels for each supported on-chip module and can be programmed to automatically
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Architectural Overview
perform transfers between peripherals and memory as the peripheral is ready to transfer more data.
The μDMA controller provides the following features:
■ ARM PrimeCell® 32-channel configurable µDMA controller
■ Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple
transfer modes
– Basic for simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
■ Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules: GP Timer, UART, ADC, EPI, SSI
– Alternate channel assignments
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable bus arbitration scheme
– Optional software-initiated requests for any channel
■ Two levels of priority
■ Design optimizations for improved bus access performance between µDMA controller and the
processor core
– µDMA controller access is subordinate to core access
– RAM striping
– Peripheral bus segmentation
■ Data sizes of 8, 16, and 32 bits
■ Transfer size is programmable in binary steps from 1 to 1024
■ Source and destination address increment size of byte, half-word, word, or no increment
■ Maskable peripheral requests
■ Interrupt on transfer completion, with a separate interrupt per channel
1.1.5.2 System Control and Clocks (see page 81)
System control determines the overall operation of the device. It provides information about the
device, controls power-saving features, controls the clocking of the device and individual peripherals,
and handles reset detection and reporting.
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Stellaris® LM3S1R21 Microcontroller
■ Device identification information: version, part number, SRAM size, Flash memory size, and so
on
■ Power control
– On-chip fixed Low Drop-Out (LDO) voltage regulator
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options for microcontroller: Sleep and Deep-sleep modes with clock gating
– Low-power options for on-chip modules: software controls shutdown of individual peripherals
and memory
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Multiple clock sources for microcontroller system clock
– Precision Oscillator (PIOSC): on-chip resource providing a 16 MHz ±1% frequency at room
temperature
• 16 MHz ±3% across temperature
• Can be recalibrated with 7-bit trim resolution
• Software power down control for low power modes
– Main Oscillator (MOSC): a frequency-accurate clock source by one of two means: an external
single-ended clock source is connected to the OSC0 input pin, or an external crystal is
connected across the OSC0 input and OSC1 output pins.
• External oscillator used with or without on-chip PLL: select supported frequencies from 1
MHz to 16.384 MHz.
• External crystal: from DC to maximum device speed
– Internal 30-kHz Oscillator: on chip resource providing a 30 kHz ± 50% frequency, used during
power-saving modes
– Hibernation Module clock source: eliminates need for additional crystal for main clock source
• 32.768-kHz external oscillator
• 4.194304-MHz external crystal
■ Flexible reset sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out reset (BOR) detector alerts to system power drops
– Software reset
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Architectural Overview
– Watchdog timer reset
– MOSC failure
1.1.5.3 Four Programmable Timers (see page 419)
Programmable timers can be used to count or time external events that drive the Timer input pins.
Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently
as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time
Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions.
The General-Purpose Timer Module (GPTM) contains four GPTM blocks with the following functional
options:
■ Count up or down
■ 16- or 32-bit programmable one-shot timer
■ 16- or 32-bit programmable periodic timer
■ 16-bit general-purpose timer with an 8-bit prescaler
■ 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
■ Eight Capture Compare PWM pins (CCP)
■ Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
■ ADC event trigger
■ User-enabled stalling when the controller asserts CPU Halt flag during debug (excluding RTC
mode)
■ 16-bit input-edge count- or time-capture modes
■ 16-bit PWM mode with software-programmable output inversion of the PWM signal
■ Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine.
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each timer
– Burst request generated on timer interrupt
1.1.5.4 CCP Pins (see page 426)
Capture Compare PWM pins (CCP) can be used by the General-Purpose Timer Module to time/count
external events using the CCP pin as an input. Alternatively, the GPTM can generate a simple PWM
output on the CCP pin.
The LM3S1R21 microcontroller includes eight Capture Compare PWM pins (CCP) that can be
programmed to operate in the following modes:
■ Capture: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer captures and stores the current timer value when a programmed event occurs.
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■ Compare: The GP Timer is incremented/decremented by programmed events on the CCP input.
The GP Timer compares the current value with a stored value and generates an interrupt when
a match occurs.
■ PWM: The GP Timer is incremented/decremented by the system clock. A PWM signal is generated
based on a match between the counter value and a value stored in a match register and is output
on the CCP pin.
1.1.5.5 Hibernation Module (see page 172)
The Hibernation module provides logic to switch power off to the main processor and peripherals
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic and has the following features:
■ Two mechanisms for power control
– System power control using discrete external regulator
– On-chip power control using internal switches under register control
■ Dedicated pin for waking using an external signal
Stellaris® LM3S1R21 Microcontroller
■ Low-battery detection, signaling, and interrupt generation
■ 32-bit real-time counter (RTC)
– Two 32-bit RTC match registers for timed wake-up and interrupt generation
– RTC predivider trim for making fine adjustments to the clock rate
■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal; source can be
used for main controller clock
■ 64 32-bit words of non-volatile memory to save state during hibernation
■ Programmable interrupts for RTC match, external wake, and low battery events
1.1.5.6 Watchdog Timers (see page 466)
A watchdog timer is used to regain control when a system has failed due to a software error or to
the failure of an external device to respond in the expected way. The Stellaris®Watchdog Timer
can generate an interrupt or a reset when a time-out value is reached. In addition, the Watchdog
Timer is ARM FiRM-compliant and can be configured to generate an interrupt to the controller on
its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer
has been configured, the lock register can be written to prevent the timer configuration from being
inadvertently altered.
The LM3S1R21 microcontroller has two Watchdog Timer modules: Watchdog Timer 0 uses the
system clock for its timer clock; Watchdog Timer 1 uses the PIOSC as its timer clock. The Stellaris
Watchdog Timer module has the following features:
®
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
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Architectural Overview
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
1.1.5.7 Programmable GPIOs (see page 291)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris
GPIO module is comprised of nine physical GPIO blocks, each corresponding to an individual GPIO
port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time
Microcontrollers specification) and supports 0-67 programmable input/output pins. The number of
GPIOs available depends on the peripherals being used (see “Signal Tables” on page 720 for the
signals available to each GPIO pin).
■ Up to 67 GPIOs, depending on configuration
■ Highly flexible pin muxing allows use as GPIO or one of several peripheral functions
■ 5-V-tolerant input/outputs
■ Fast toggle capable of a change every two clock cycles
®
■ Two means of port access: either Advanced High-Performance Bus (AHB) with better back-to-back
access performance, or the legacy Advanced Peripheral Bus (APB) for backwards-compatibility
with existing code
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Can be used to initiate an ADC sample sequence
■ Pins configured as digital inputs are Schmitt-triggered
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
1.1.6 Analog
The LM3S1R21 controller provides analog functions integrated into the device, including:
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■ 10-bit Analog-to-Digital Converter (ADC) with eight analog input channels and sample rate of
one million samples/second
■ Two analog comparators
■ Eight digital comparators
■ On-chip voltage regulator
The following provides more detail on these analog functions.
1.1.6.1 ADC (see page 491)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number. The Stellaris®ADC module features 10-bit conversion resolution and supports
eight input channels plus an internal temperature sensor. Four buffered sample sequencers allow
rapid sampling of up to eight analog input sources without controller intervention. Each sample
sequencer provides flexible programming with fully configurable input source, trigger events, interrupt
generation, and sequencer priority. A digital comparator function is included that allows the conversion
value to be diverted to a comparison unit that provides eight digital comparators.
with the following features:
Stellaris® LM3S1R21 Microcontroller
■ Eight analog input channels
■ Single-ended and differential-input configurations
■ On-chip internal temperature sensor
■ Sample rate of one million samples/second
■ Optional phase shift in sample time programmable from 22.5º to 337.5º
■ Four programmable sample conversion sequencers from one to eight entries long, with
corresponding conversion result FIFOs
■ Flexible trigger control
– Controller (software)
– Timers
– Analog Comparators
– GPIO
■ Hardware averaging of up to 64 samples for improved accuracy
■ Digital comparison unit providing eight digital comparators
■ Converter uses an internal 3-V reference or an external reference
■ Power and ground for the analog circuitry is separate from the digital power and ground
■ Efficient transfers using Micro Direct Memory Access Controller (µDMA)
– Dedicated channel for each sample sequencer
Texas Instruments-Advance Information
45February 09, 2010
Architectural Overview
– Burst request asserted when interrupt is triggered
1.1.6.2 Analog Comparators (see page 706)
An analog comparator is a peripheral that compares two analog voltages and provides a logical
output that signals the comparison result. The LM3S1R21 microcontroller provides two independent
integrated analog comparators that can be configured to drive an output or generate an interrupt or
ADC event.
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
The LM3S1R21 microcontroller provides two independent integrated analog comparators with the
following functions:
■ Compare external pin input to external pin input or to internal programmable voltage reference
■ Compare a test voltage against any one of the following voltages:
– An individual external reference voltage
– A shared single external reference voltage
– A shared internal reference voltage
1.1.7 JTAG and ARM Serial Wire Debug (see page 69)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial
Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG
debug ports into one module providing all the normal JTAG debug and test functionality plus real-time
access to system memory without halting the core or requiring any target resident code. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP. The SWJ-DP interface
has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
Texas Instruments-Advance Information
February 09, 201046
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
1.1.8 Packaging and Temperature
■ Industrial-range 100-pin RoHS-compliant LQFP package
■ Industrial-range 108-ball RoHS-compliant BGA package
1.2 Target Applications
The Stellaris®family is positioned for cost-conscious applications requiring significant control
processing and connectivity capabilities such as:
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
Stellaris® LM3S1R21 Microcontroller
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 depicts the features on the Stellaris®LM3S1R21 microcontroller. Note that there are two
on-chip buses that connect the core to the peripherals. The Advanced Peripheral Bus (APB) bus is
the legacy bus. The Advanced High-Performance Bus (AHB) bus provides better back-to-back
access performance than the APB bus.
Texas Instruments-Advance Information
47February 09, 2010
LM3S1R21
ARM®
Cortex™-M3
(80 MHz)
NVIC MPU
Flash
(256 KB)
Boot Loader
DriverLib
AES & CRC
ROM
DCode bus
ICode bus
JTAG/SWD
System
Control and
Clocks
(w/ Precis. Osc.)
Bus Matrix
System Bus
SRAM
(48 KB)
SYSTEM PERIPHERALS
Watchdog
Timers
(2)
DMA
Hibernation
Module
GeneralPurpose
Timers (4)
GPIOs
(67)
External
Peripheral
Interface
SERIAL PERIPHERALS
UARTs
(3)
I2C
(2)
SSI
(2)
ANALOG PERIPHERALS
ADC
Channels
(8)
Analog
Comparators
(2)
Advanced Peripheral Bus (APB)
Advanced High-Performance Bus (AHB)
Architectural Overview
Figure 1-1. Stellaris®LM3S1R21 Microcontroller High-Level Block Diagram
Texas Instruments-Advance Information
February 09, 201048
1.4 Additional Features
1.4.1 Memory Map (see page 63)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S1R21 controller can be found in “Memory Map” on page 63. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map. The
ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map.
1.4.2 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 718
■ “Signal Tables” on page 720
■ “Operating Characteristics” on page 767
■ “Electrical Characteristics” on page 768
■ “Package Information” on page 852
Stellaris® LM3S1R21 Microcontroller
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49February 09, 2010
ARM Cortex-M3 Processor Core
2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
■ 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications
■ Outstanding processing performance combined with fast interrupt handling
■ Thumb-2 mixed 16-/32-bit instruction set, delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices; typically in
the range of a few kilobytes of memory for microcontroller-class applications
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
– Unaligned data access, enabling data to be efficiently packed into memory
■ Fast code execution permits slower processor clock or increases sleep mode time
■ Harvard architecture characterized by separate buses for instruction and data
■ Efficient processor core, system and memories
■ Hardware division and fast multiplier
■ Deterministic, high-performance interrupt handling for time-critical applications
■ Memory protection unit (MPU) to provide a privileged mode for protected operating system
functionality
■ Enhanced system debug with extensive breakpoint and trace capabilities
■ Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging and
tracing
■ Migration from the ARM7™ processor family for better performance and power efficiency
■ Optimized for single-cycle Flash memory usage
■ Ultra-low power consumption with integrated sleep modes
■ 80-MHz operation
■ 1.25 DMIPS/MHz
The Stellaris®family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
February 09, 201050
Texas Instruments-Advance Information
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Debug
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
2.1 Block Diagram
Figure 2-1. CPU Block Diagram
Stellaris® LM3S1R21 Microcontroller
2.2 Functional Description
Important:
Texas Instruments implements the ARM Cortex-M3 core as shown in Figure 2-1 on page 51. The
Cortex-M3 uses the entire 16-bit Thumb instruction set and the base Thumb-2 32-bit instruction set.
In addition, as noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3
components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the
MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the
sections that follow.
2.2.1 Programming Model
This section provides a brief overview of the programming model for the Cortex-M3 core. More
detailed information can be found in the ARM® Cortex™-M3 Technical Reference Manual.
■ Privileged access and user access - Code can execute as privileged or unprivileged. Unprivileged
execution limits or excludes access to some resources. Privileged execution has access to all
resources. Handler mode is always privileged. Thread mode can be privileged or unprivileged.
The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris®implementation.
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51February 09, 2010
ARM Cortex-M3 Processor Core
Thread mode is privileged out of reset, but you can change it to user or unprivileged by setting
the CONTROL[0] bit using the MSR instruction. User access prevents:
– Use of some instructions such as CPS to set FAULTMASK and PRIMASK
– Access to most registers in System Control Space (SCS)
When Thread mode has been changed from privileged to user, it cannot change itself back to
privileged. Only a Handler can change the privilege of Thread mode. Handler mode is always
privileged.
■ Register set - The processor has the following 32-bit registers:
– 13 general-purpose registers, r0-r12
– Stack point alias of banked registers, SP_process and SP_main
– Link register, r14
– Program counter, r15
– One program status register, xPSR.
■ Data types - The processor supports the following data types:
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
■ Memory formats - The processor views memory as a linear collection of bytes numbered in
ascending order from 0. For example, bytes 0-3 hold the first stored word and bytes 4-7 hold the
second stored word. The processor accesses code and data in little-endian format, which means
that the byte with the lowest address in a word is the least-significant byte of the word. The byte
with the highest address in a word is the most significant. The byte at address 0 of the memory
system connects to data lines 7-0.
■ Instruction set - The Cortex-M3 instruction set contains both 16 and 32-bit instructions. These
instructions are summarized in Table 2-1 on page 52 and Table 2-2 on page 54, respectively.
Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary
AssemblerOperation
ADC <Rd>, <Rm>Add register value and C flag to register value
ADD <Rd>, <Rn>, #<immed_3>Add immediate 3-bit value to register
ADD <Rd>, #<immed_8>Add immediate 8-bit value to register
ADD <Rd>, <Rn>, <Rm>Add low register value to low register value
ADD <Rd>, <Rm>Add high register value to low or high register value
ADD <Rd>, PC, #<immed_8> * 4Add 4* (immediate 8-bit value) with PC to register
ADD <Rd>, SP, #<immed_8> * 4Add 4* (immediate 8-bit value) with SP to register
ADD SP, #<immed_7> * 4Add 4* (immediate 7-bit value) to SP
AND <Rd>, <Rm>Bitwise AND register values
ASR <Rd>, <Rm>, #<immed_5>Arithmetic shift right by immediate number
Texas Instruments-Advance Information
February 09, 201052
Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary (continued)
AssemblerOperation
ASR <Rd>, <Rs>Arithmetic shift right by number in register
B<cond> <target address>Branch conditional
B <target_address>Branch unconditional
BIC <Rd>, <Rm>Bit clear
BKPT <immed_8>Software breakpoint
BL <Rm>Branch with link
BLX <Rm>Branch with link and exchange
BX <Rm>Branch and exchange
CBNZ <Rn>,<label>Compare not zero and branch
CBZ <Rn>,<label>Compare zero and branch
CMN <Rn>, <Rm>Compare negation of register value with another register value
CMP <Rn>, #<immed_8>Compare immediate 8-bit value
CMP <Rn>, <Rm>Compare registers
CMP <Rn>, <Rm>Compare high register to low or high register
CPS <effect>, <iflags>Change processor state
CPY <Rd> <Rm>Copy high or low register value to another high or low register
EOR <Rd>, <Rm>Bitwise exclusive OR register values
IT <cond>Condition the following instruction
IT<x> <cond>Condition the following two instructions
IT<x><y> <cond>Condition the following three instructions
IT<x><y><z> <cond>Condition the following four instructions
LDMIA <Rn>!, <registers>Multiple sequential memory word loads
LDR <Rd>, [<Rn>, #<immed_5> * 4]Load memory word from base register address + 5-bit immediate offset
LDR <Rd>, [<Rn>, <Rm>]Load memory word from base register address + register offset
LDR <Rd>, [PC, #<immed_8> * 4]Load memory word from PC address + 8-bit immediate offset
LDR, <Rd>, [SP, #<immed_8> * 4]Load memory word from SP address + 8-bit immediate offset
LDRB <Rd>, [<Rn>, #<immed_5>]Load memory byte [7:0] from register address + 5-bit immediate offset
LDRB <Rd>, [<Rn>, <Rm>]Load memory byte [7:0] from register address + register offset
LDRH <Rd>, [<Rn>, #<immed_5> * 2]Load memory halfword [15:0] from register address + 5-bit immediate offset
LDRH <Rd>, [<Rn>, <Rm>]Load halfword [15:0] from register address + register offset
LDRSB <Rd>, [<Rn>, <Rm>]Load signed byte [7:0] from register address + register offset
LDRSH <Rd>, [<Rn>, <Rm>]Load signed halfword [15:0] from register address + register offset
LSL <Rd>, <Rm>, #<immed_5>Logical shift left by immediate number
LSL <Rd>, <Rs>Logical shift left by number in register
LSR <Rd>, <Rm>, #<immed_5>Logical shift right by immediate number
LSR <Rd>, <Rs>Logical shift right by number in register
MOV <Rd>, #<immed_8>Move immediate 8-bit value to register
MOV <Rd>, <Rn>Move low register value to low register
MOV <Rd>, <Rm>Move high or low register value to high or low register
MUL <Rd>, <Rm>Multiply register values
MVN <Rd>, <Rm>Move complement of register value to register
NEG <Rd>, <Rm>Negate register value and store in register
Stellaris® LM3S1R21 Microcontroller
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53February 09, 2010
ARM Cortex-M3 Processor Core
Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary (continued)
AssemblerOperation
NOP <c>No operation
ORR <Rd>, <Rm>Bitwise logical OR register values
POP <registers>Pop registers from stack
POP <registers, PC>Pop registers and PC from stack
PUSH <registers>Push registers onto stack
PUSH <registers, LR>Push LR and registers onto stack
REV <Rd>, <Rn>Reverse bytes in word and copy to register
REV16 <Rd>, <Rn>Reverse bytes in two halfwords and copy to register
REVSH <Rd>, <Rn>Reverse bytes in low halfword [15:0], sign-extend, and copy to register
ROR <Rd>, <Rs>Rotate right by amount in register
SBC <Rd>, <Rm>Subtract register value and C flag from register value
SEV <c>Send event
STMIA <Rn>!, <registers>Store multiple register words to sequential memory locations
STR <Rd>, [<Rn>, #<immed_5> * 4]Store register word to register address + 5-bit immediate offset
STR <Rd>, [<Rn>, <Rm>]Store register word to register address
STR <Rd>, [SP, #<immed_8> * 4]Store register word to SP address + 8-bit immediate offset
STRB <Rd>, [<Rn>, #<immed_5>]Store register byte [7:0] to register address + 5-bit immediate offset
STRB <Rd>, [<Rn>, <Rm>]Store register byte [7:0] to register address
STRH <Rd>, [<Rn>, #<immed_5> * 2]Store register halfword [15:0] to register address + 5-bit immediate offset
STRH <Rd>, [<Rn>, <Rm>]Store register halfword [15:0] to register address + register offset
SUB <Rd>, <Rn>, #<immed_3>Subtract immediate 3-bit value from register
SUB <Rd>, #<immed_8>Subtract immediate 8-bit value from register value
SUB <Rd>, <Rn>, <Rm>Subtract register values
SUB SP, #<immed_7> * 4Subtract 4 (immediate 7-bit value) from SP
SVC <immed_8>Operating system service call with 8-bit immediate call code
SXTB <Rd>, <Rm>Extract byte [7:0] from register, move to register, and sign-extend to 32 bits
SXTH <Rd>, <Rm>Extract halfword [15:0] from register, move to register, and sign-extend to 32 bits
TST <Rn>, <Rm>Test register value for set bits by ANDing it with another register value
UXTB <Rd>, <Rm>10Extract byte [7:0] from register, move to register, and zero-extend to 32 bits
UXTH <Rd>, <Rm>Extract halfword [15:0] from register, move to register, and zero-extend to 32
bits
WFE <c>Wait for event
WFI <c>Wait for interrupt
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary
Texas Instruments-Advance Information
AssemblerOperation
ADC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12>Add register value, immediate 12-bit value, and C bit
ADC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}Add register value, shifted register value, and C bit
ADD{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>Add register value and immediate 12-bit value
ADD{S}.W <Rd>, <Rm>{, <shift>}Add register value and shifted register value
ADDW.W <Rd>, <Rn>, #<immed_12>Add register value and immediate 12-bit value
AND{S}.W <Rd>, <Rn>, #<modify_constant(immed_12>Bitwise AND register value with immediate 12-bit value
February 09, 201054
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
AssemblerOperation
AND{S}.W <Rd>, <Rn>, Rm>{, <shift>}Bitwise AND register value with shifted register value
ASR{S}.W <Rd>, <Rn>, <Rm>Arithmetic shift right by number in register
B{cond}.W <label>Conditional branch
BFC.W <Rd>, #<lsb>, #<width>Clear bit field
BFI.W <Rd>, <Rn>, #<lsb>, #<width>Insert bit field from one register value into another
BIC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>Bitwise AND register value with complement of immediate 12-bit value
BIC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}Bitwise AND register value with complement of shifted register value
BL <label>Branch with link
BL<c> <label>Branch with link (immediate)
B.W <label>Unconditional branch
CLREX <c>Clear exclusive clears the local record of the executing processor that an
address has had a request for an exclusive access.
CLZ.W <Rd>, <Rn>Return number of leading zeros in register value
CMN.W <Rn>, #<modify_constant(immed_12)>Compare register value with two’s complement of immediate 12-bit value
CMN.W <Rn>, <Rm>{, <shift>}Compare register value with two’s complement of shifted register value
CMP.W <Rn>, #<modify_constant(immed_12)>Compare register value with immediate 12-bit value
CMP.W <Rn>, <Rm>{, <shift>}Compare register value with shifted register value
DMB <c>Data memory barrier
DSB <c>Data synchronization barrier
EOR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>Exclusive OR register value with immediate 12-bit value
EOR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}Exclusive OR register value with shifted register value
ISB <c>Instruction synchronization barrier
LDM{IA|DB}.W <Rn>{!}, <registers>Load multiple memory registers, increment after or decrement before
LDR.W <Rxf>, [<Rn>, #<offset_12>]Memory word from base register address + immediate 12-bit offset
LDR.W PC, [<Rn>, #<offset_12>]Memory word to PC from register address + immediate 12-bit offset
LDR.W PC, [Rn], #<+/-<offset_8>Memory word to PC from base register address immediate 8-bit offset,
postindexed
LDR.W <Rxf>, [<Rn>], #+/–<offset_8>Memory word from base register address immediate 8-bit offset, postindexed
Memory word from base register address immediate 8-bit offset, preindexed
preindexed
postindexed
preindexed
LDR.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
LDRT.W <Rxf>, [<Rn>, #<offset_8>]
LDR.W PC, [<Rn>, #+/–<offset_8>]!Memory word to PC from base register address immediate 8-bit offset,
LDR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]Memory word from register address shifted left by 0, 1, 2, or 3 places
LDR.W PC, [<Rn>, <Rm>{, LSL #<shift>}]Memory word to PC from register address shifted left by 0, 1, 2, or 3 places
LDR.W <Rxf>, [PC, #+/–<offset_12>]Memory word from PC address immediate 12-bit offset
LDR.W PC, [PC, #+/–<offset_12>]Memory word to PC from PC address immediate 12-bit offset
LDRB.W <Rxf>, [<Rn>, #<offset_12>]Memory byte [7:0] from base register address + immediate 12-bit offset
LDRB.W <Rxf>. [<Rn>], #+/-<offset_8>Memory byte [7:0] from base register address immediate 8-bit offset,
LDRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]Memory byte [7:0] from register address shifted left by 0, 1, 2, or 3 places
LDRB.W <Rxf>, [<Rn>, #<+/–<offset_8>]!Memory byte [7:0] from base register address immediate 8-bit offset,
LDRB.W <Rxf>, [PC, #+/–<offset_12>]Memory byte from PC address immediate 12-bit offset
LDRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}Memory doubleword from register address 8-bit offset 4, preindexed
Stellaris® LM3S1R21 Microcontroller
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55February 09, 2010
ARM Cortex-M3 Processor Core
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
AssemblerOperation
LDRD.W <Rxf>, <Rxf2>, [<Rn>], #+/–<offset_8> * 4Memory doubleword from register address 8-bit offset 4, postindexed
LDREX<c> <Rt>,[<Rn>{,#<imm>}]Load register exclusive calculates an address from a base register value and
an immediate offset, loads a word from memory, writes it to a register
LDREXH<c> <Rt>,[<Rn>{,#<imm>}]Load register exclusive halfword calculates an address from a base register
value and an immediate offset, loads a halfword from memory, writes it to a
register
LDREXB<c> <Rt>,[<Rn>{,#<imm>}]Load register exclusive byte calculates an address from a base register value
and an immediate offset, loads a byte from memory, writes it to a register
LDRH.W <Rxf>, [<Rn>, #<offset_12>]Memory halfword [15:0] from base register address + immediate 12-bit offset
LDRH.W <Rxf>, [<Rn>, #<+/–<offset_8>]!Memory halfword [15:0] from base register address immediate 8-bit offset,
preindexed
LDRH.W <Rxf>. [<Rn>], #+/-<offset_8>Memory halfword [15:0] from base register address immediate 8-bit offset,
postindexed
LDRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]Memory halfword [15:0] from register address shifted left by 0, 1, 2, or 3 places
LDRH.W <Rxf>, [PC, #+/–<offset_12>]Memory halfword from PC address immediate 12-bit offset
LDRSB.W <Rxf>, [<Rn>, #<offset_12>]Memory signed byte [7:0] from base register address + immediate 12-bit offset
LDRSB.W <Rxf>. [<Rn>], #+/-<offset_8>Memory signed byte [7:0] from base register address immediate 8-bit offset,
postindexed
LDRSB.W <Rxf>, [<Rn>, #<+/–<offset_8>]!Memory signed byte [7:0] from base register address immediate 8-bit offset,
preindexed
LDRSB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]Memory signed byte [7:0] from register address shifted left by 0, 1, 2, or 3
places
LDRSB.W <Rxf>, [PC, #+/–<offset_12>]Memory signed byte from PC address immediate 12-bit offset
LDRSH.W <Rxf>, [<Rn>, #<offset_12>]Memory signed halfword [15:0] from base register address + immediate 12-bit
offset
LDRSH.W <Rxf>. [<Rn>], #+/-<offset_8>Memory signed halfword [15:0] from base register address immediate 8-bit
offset, postindexed
LDRSH.W <Rxf>, [<Rn>, #<+/–<offset_8>]!Memory signed halfword [15:0] from base register address immediate 8-bit
offset, preindexed
LDRSH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]Memory signed halfword [15:0] from register address shifted left by 0, 1, 2,
or 3 places
LDRSH.W <Rxf>, [PC, #+/–<offset_12>]Memory signed halfword from PC address immediate 12-bit offset
LSL{S}.W <Rd>, <Rn>, <Rm>Logical shift left register value by number in register
LSR{S}.W <Rd>, <Rn>, <Rm>Logical shift right register value by number in register
MLA.W <Rd>, <Rn>, <Rm>, <Racc>Multiply two signed or unsigned register values and add the low 32 bits to a
register value
MLS.W <Rd>, <Rn>, <Rm>, <Racc>Multiply two signed or unsigned register values and subtract the low 32 bits
from a register value
MOV{S}.W <Rd>, #<modify_constant(immed_12)>Move immediate 12-bit value to register
MOV{S}.W <Rd>, <Rm>{, <shift>}Move shifted register value to register
MOVT.W <Rd>, #<immed_16>Move immediate 16-bit value to top halfword [31:16] of register
MOVW.W <Rd>, #<immed_16>Move immediate 16-bit value to bottom halfword [15:0] of register and clear
top halfword [31:16]
MRS<c> <Rd>, <psr>Move to register from status
MSR<c> <psr>_<fields>,<Rn>Move to status register
MUL.W <Rd>, <Rn>, <Rm>Multiply two signed or unsigned register values
NOP.WNo operation
Texas Instruments-Advance Information
February 09, 201056
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
AssemblerOperation
ORN{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>Logical OR NOT register value with immediate 12-bit value
ORN[S}.W <Rd>, <Rn>, <Rm>{, <shift>}Logical OR NOT register value with shifted register value
ORR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>Logical OR register value with immediate 12-bit value
ORR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}Logical OR register value with shifted register value
RBIT.W <Rd>, <Rm>Reverse bit order
REV.W <Rd>, <Rm>Reverse bytes in word
REV16.W <Rd>, <Rn>Reverse bytes in each halfword
REVSH.W <Rd>, <Rn>Reverse bytes in bottom halfword and sign-extend
ROR{S}.W <Rd>, <Rn>, <Rm>Rotate right by number in register
RRX{S}.W <Rd>, <Rm>Rotate right with extend
RSB{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>Subtract a register value from an immediate 12-bit value
RSB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}Subtract a register value from a shifted register value
SBC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>Subtract immediate 12-bit value and C bit from register value
SBC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}Subtract shifted register value and C bit from register value
SBFX.W <Rd>, <Rn>, #<lsb>, #<width>Copy selected bits to register and sign-extend
SDIV<c> <Rd>,<Rn>,<Rm>Signed divide
SEV<c>Send event
SMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>Multiply signed words and add signed-extended value to 2-register value
SMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>Multiply two signed register values
SSAT.W <c> <Rd>, #<imm>, <Rn>{, <shift>}Signed saturate
STM{IA|DB}.W <Rn>{!}, <registers>Multiple register words to consecutive memory locations
STR.W <Rxf>, [<Rn>, #<offset_12>]Register word to register address + immediate 12-bit offset
STR.W <Rxf>, [<Rn>], #+/–<offset_8>Register word to register address immediate 8-bit offset, postindexed
STR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]Register word to register address shifted by 0, 1, 2, or 3 places
Register word to register address immediate 8-bit offset, preindexed Store,
preindexed
an immediate offset, and stores a word from a register to memory if the
executing processor has exclusive access to the memory addressed.
and stores a byte from a register to memory if the executing processor has
exclusive access to the memory addressed
value, and stores a halfword from a register to memory if the executing
processor has exclusive access to the memory addressed.
STR.W <Rxf>, [<Rn>, #+/-<offset_8>]{!}
STRT.W <Rxf>, [<Rn>, #<offset_8>]
STRB{T}.W <Rxf>, [<Rn>, #+/–<offset_8>]{!}Register byte [7:0] to register address immediate 8-bit offset, preindexed
STRB.W <Rxf>, [<Rn>, #<offset_12>]Register byte [7:0] to register address + immediate 12-bit offset
STRB.W <Rxf>, [<Rn>], #+/–<offset_8>Register byte [7:0] to register address immediate 8-bit offset, postindexed
STRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]Register byte [7:0] to register address shifted by 0, 1, 2, or 3 places
STRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}Store doubleword, preindexed
STRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]Store doubleword, postindexed
STREX <c> <Rd>,<Rt>,[<Rn>{,#<imm>}]Store register exclusive calculates an address from a base register value and
STREXB <c> <Rd>,<Rt>,[<Rn>]Store register exclusive byte derives an address from a base register value,
STREXH <c> <Rd>,<Rt>,[<Rn>]Store register exclusive halfword derives an address from a base register
STRH.W <Rxf>, [<Rn>, #<offset_12>]Register halfword [15:0] to register address + immediate 12-bit offset
STRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]Register halfword [15:0] to register address shifted by 0, 1, 2, or 3 places
STRH{T}.W <Rxf>, [<Rn>, #+/–<offset_8>]{!}Register halfword [15:0] to register address immediate 8-bit offset, preindexed
Stellaris® LM3S1R21 Microcontroller
Texas Instruments-Advance Information
57February 09, 2010
ARM Cortex-M3 Processor Core
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
AssemblerOperation
STRH.W <Rxf>, [<Rn>], #+/–<offset_8>Register halfword [15:0] to register address immediate 8-bit offset, postindexed
SUB{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>Subtract immediate 12-bit value from register value
SUB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}Subtract shifted register value from register value
SUBW.W <Rd>, <Rn>, #<immed_12>Subtract immediate 12-bit value from register value
SXTB.W <Rd>, <Rm>{, <rotation>}Sign extend byte to 32 bits
SXTH.W <Rd>, <Rm>{, <rotation>}Sign extend halfword to 32 bits
TBB [<Rn>, <Rm>]Table branch byte
TBH [<Rn>, <Rm>, LSL #1]Table branch halfword
TEQ.W <Rn>, #<modify_constant(immed_12)>Exclusive OR register value with immediate 12-bit value
TEQ.W <Rn>, <Rm>{, <shift}Exclusive OR register value with shifted register value
TST.W <Rn>, #<modify_constant(immed_12)>Logical AND register value with 12-bit immediate value
TST.W <Rn>, <Rm>{, <shift>}Logical AND register value with shifted register value
UBFX.W <Rd>, <Rn>, #<lsb>, #<width>Copy bit field from register value to register and zero-extend to 32 bits
UDIV<c> <Rd>,<Rn>,<Rm>Unsigned divide
UMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>Multiply two unsigned register values and add to a 2-register value
UMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>Multiply two unsigned register values
USAT <c> <Rd>, #<imm>, <Rn>{, <shift>}Unsigned saturate
UXTB.W <Rd>, <Rm>{, <rotation>}Copy unsigned byte to register and zero-extend to 32 bits
UXTH.W <Rd>, <Rm>{, <rotation>}Copy unsigned halfword to register and zero-extend to 32 bits
WFE.WWait for event
WFI.WWait for interrupt
2.2.2 Serial Wire and JTAG Debug
Texas Instruments replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. As a result, Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris®devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
2.2.3 Embedded Trace Macrocell (ETM)
ETM is not implemented in the Stellaris®devices. As a result, Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
2.2.4 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. Stellaris®devices implement the TPIU as shown in Figure 2-2. This implementation
is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual,
however, SWJ-DP only provides the Serial Wire Viewer (SWV) output format for the TPIU.
Texas Instruments-Advance Information
February 09, 201058
Figure 2-2. TPIU Block Diagram
ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
Stellaris® LM3S1R21 Microcontroller
2.2.5 ROM Table
The default ROM table is implemented as described in the ARM® Cortex™-M3 Technical Reference
Manual.
2.2.6 Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S1R21 controller and supports the
standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full
support for protection regions, overlapping protection regions, access permissions, and exporting
memory attributes to the system.
2.2.7 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC):
■ Facilitates low-latency exception and interrupt handling
■ Controls power management
■ Implements system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency interrupt
processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of
the stacked (nested) interrupts to enable tail-chaining of interrupts.
You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode
by enabling the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference
Manual). Any other user-mode access causes a bus fault.
All NVIC registers are accessible using byte, halfword, and word unless otherwise stated.
59February 09, 2010
Texas Instruments-Advance Information
ARM Cortex-M3 Processor Core
2.2.7.1 Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts
and interrupt priorities. The LM3S1R21 microcontroller supports 37 interrupts with eight priority
levels.
In addition to the peripheral interrupts, the system also provides for a non-maskable interrupt (NMI).
The NMI is generally used in safety critical applications where the immediate execution of an interrupt
handler is required. The NMI signal is available as an external signal so that it may be generated
by external circuitry. The NMI is also used internally as part of the main oscillator verification circuitry.
More information on the non-maskable interrupt is located in “Non-Maskable Interrupt” on page 86.
2.2.8 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine
■ A high-speed alarm timer using the system clock
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
2.2.8.1 Functional Description
The timer consists of three registers:
■ SysTick Control and Status Register - a control and status counter to configure its clock, enable
the counter, enable the SysTick interrupt, and determine counter status
■ SysTick Reload Value Register - the reload value for the counter, used to provide the counter's
wrap value
■ SysTick Current Value Register - the current value of the counter
A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris®devices.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the SysTick Reload Value register on the next clock edge, then decrements on
subsequent clocks. Clearing the SysTick Reload Value register disables the counter on the next
wrap. When the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit
clears on reads.
Writing to the SysTick Current Value register clears the register and the COUNTFLAG status bit.
The write does not trigger the SysTick exception logic. On a read, the current value is the value of
the register at the time the register is accessed.
February 09, 201060
Texas Instruments-Advance Information
If the core is in debug state (halted), the counter does not decrement. The timer is clocked with
respect to a reference clock, which can be either the core clock or an external clock source.
2.2.8.2 SysTick Control and Status Register
Use the SysTick Control and Status Register to enable the SysTick features. The reset is
0x0000.0000.
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
0x000ROreserved31:17
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Count Flag
0R/WCOUNTFLAG16
When set, this bit indicates that the timer has counted to 0 since the last time
this register was read.
This bit is cleared by a read of the register.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise, the
COUNTFLAG bit is not changed by the debugger read.
Software should not rely on the value of a reserved bit. To provide
0x000ROreserved15:3
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Clock Source
0R/WCLKSOURCE2
Stellaris® LM3S1R21 Microcontroller
0R/WTICKINT1
0R/WENABLE0
2.2.8.3 SysTick Reload Value Register
The SysTick Reload Value Register specifies the start value to load into the SysTick Current Value
Register when the counter reaches 0. The start value can be between 1 and 0x00FF.FFFF. A start
value of 0 is possible but has no effect because the SysTick interrupt and COUNTFLAG are activated
when counting from 1 to 0.
DescriptionValue
External reference clock. (Not implemented for Stellaris
0
microcontrollers.)
Core clock1
Because an external reference clock is not supported, this bit must be set
in order for SysTick to operate.
Tick Interrupt
When set, this bit causes an interrupt to be generated to the NVIC when
SysTick counts to 0.
When clear, interrupt generation is disabled. Software can use the
COUNTFLAG to determine if the counter has ever reached 0.
Enable
When set, this bit enables SysTick to operate in a multi-shot way. That is,
the counter loads the Reload value and begins counting down. On reaching
0, the COUNTFLAG bit is set and an interrupt is generated if enabled by
TICKINT. The counter then loads the Reload value again and begins counting.
When this bit is clear, the counter is disabled.
®
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
Texas Instruments-Advance Information
61February 09, 2010
ARM Cortex-M3 Processor Core
When configuring SysTick as a single-shot timer, a new value is written on each tick interrupt, and
the actual count down value must be written. For example, if a tick is next required after 400 clock
pulses, 400 must be written into the RELOAD field.
2.2.8.4 SysTick Current Value Register
The SysTick Current Value Register contains the current value of the counter.
0x00ROreserved31:24
DescriptionResetTypeNameBit/Field
0x00ROreserved31:24
-W1CCURRENT23:0
Software should not rely on the value of a reserved bit. To
provide compatibility with future products, the value of a
reserved bit should be preserved across a read-modify-write
operation.
Reload Value
-R/WRELOAD23:0
Value to load into the SysTick Current Value Register when
the counter reaches 0.
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Current Value
This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register
to 0. Clearing this register also clears the COUNTFLAG bit of the
SysTick Control and Status Register.
2.2.8.5 SysTick Calibration Value Register
The SysTick Calibration Value register is not implemented.
Texas Instruments-Advance Information
February 09, 201062
3 Memory Map
The memory map for the LM3S1R21 controller is provided in Table 3-1.
In this manual, register addresses are given as a hexadecimal increment, relative to the module’s
base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM®
Cortex™-M3 Technical Reference Manual.
Note that within the memory map, all reserved space returns a bus fault when read or written.
Table 3-1. Memory Map
Stellaris® LM3S1R21 Microcontroller
Memory
FiRM Peripherals
Peripherals
DescriptionEndStart
Reserved0x3FFF.FFFF0x0000.0001
Reserved0x4001.FFFF0x4000.F000
For details,
see page ...
200On-chip Flash0x0003.FFFF0x0000.0000
-Reserved0x00FF.FFFF0x0004.0000
200Reserved for ROM0x1FFF.FFFF0x0100.0000
200Bit-banded on-chip SRAM0x2000.0000
-Reserved0x21FF.FFFF0x0000.0001
200Bit-band alias of 0x2000.0000 through 0x200F.FFFF0x2200.0000
-
469Watchdog timer 00x4000.0FFF0x4000.0000
469Watchdog timer 10x4000.1FFF0x4000.1000
-Reserved0x4000.3FFF0x4000.2000
304GPIO Port A0x4000.4FFF0x4000.4000
304GPIO Port B0x4000.5FFF0x4000.5000
304GPIO Port C0x4000.6FFF0x4000.6000
304GPIO Port D0x4000.7FFF0x4000.7000
641SSI00x4000.8FFF0x4000.8000
641SSI10x4000.9FFF0x4000.9000
-Reserved0x4000.BFFF0x4000.A000
578UART00x4000.CFFF0x4000.C000
578UART10x4000.DFFF0x4000.D000
578UART20x4000.EFFF0x4000.E000
-
684I2C Master 00x4002.07FF0x4002.0000
697I2C Slave 00x4002.0FFF0x4002.0800
684I2C Master 10x4002.17FF0x4002.1000
697I2C Slave 10x4002.1FFF0x4002.1800
-Reserved0x4002.3FFF0x4002.2000
304GPIO Port E0x4002.4FFF0x4002.4000
304GPIO Port F0x4002.5FFF0x4002.5000
304GPIO Port G0x4002.6FFF0x4002.6000
304GPIO Port H0x4002.7FFF0x4002.7000
Texas Instruments-Advance Information
63February 09, 2010
Memory Map
Table 3-1. Memory Map (continued)
Private Peripheral Bus
DescriptionEndStart
Reserved0xDFFF.FFFF0xD000.0000
Instrumentation Trace Macrocell (ITM)0xE000.0FFF0xE000.0000
Data Watchpoint and Trace (DWT)0xE000.1FFF0xE000.1000
For details,
see page ...
-Reserved0x4002.FFFF0x4002.8000
435Timer 00x4003.0FFF0x4003.0000
435Timer 10x4003.1FFF0x4003.1000
435Timer 20x4003.2FFF0x4003.2000
435Timer 30x4003.3FFF0x4003.3000
-Reserved0x4003.7FFF0x4003.4000
509ADC00x4003.8FFF0x4003.8000
-Reserved0x4003.BFFF0x4003.9000
706Analog Comparators0x4003.CFFF0x4003.C000
304GPIO Port J0x4003.DFFF0x4003.D000
-Reserved0x4005.7FFF0x4003.E000
304GPIO Port A (AHB aperture)0x4005.8FFF0x4005.8000
304GPIO Port B (AHB aperture)0x4005.9FFF0x4005.9000
304GPIO Port C (AHB aperture)0x4005.AFFF0x4005.A000
304GPIO Port D (AHB aperture)0x4005.BFFF0x4005.B000
304GPIO Port E (AHB aperture)0x4005.CFFF0x4005.C000
304GPIO Port F (AHB aperture)0x4005.DFFF0x4005.D000
304GPIO Port G (AHB aperture)0x4005.EFFF0x4005.E000
304GPIO Port H (AHB aperture)0x4005.FFFF0x4005.F000
304GPIO Port J (AHB aperture)0x4006.0FFF0x4006.0000
-Reserved0x400C.FFFF0x4006.1000
376EPI00x400D.0FFF0x400D.0000
-Reserved0x400F.BFFF0x400D.1000
182Hibernation Module0x400F.CFFF0x400F.C000
206Flash memory control0x400F.DFFF0x400F.D000
96System control0x400F.EFFF0x400F.E000
254µDMA0x400F.FFFF0x400F.F000
-Reserved0x41FF.FFFF0x4010.0000
-Bit-banded alias of 0x4000.0000 through 0x400F.FFFF0x43FF.FFFF0x4200.0000
-Reserved0x5FFF.FFFF0x4400.0000
-EPI0 mapped peripheral and RAM0xCFFF.FFFF0x6000.0000
-
ARM®
Cortex™-M3
Technical
Reference
Manual
ARM®
Cortex™-M3
Technical
Reference
Manual
Texas Instruments-Advance Information
February 09, 201064
Table 3-1. Memory Map (continued)
Stellaris® LM3S1R21 Microcontroller
DescriptionEndStart
Flash Patch and Breakpoint (FPB)0xE000.2FFF0xE000.2000
Nested Vectored Interrupt Controller (NVIC)0xE000.EFFF0xE000.E000
Trace Port Interface Unit (TPIU)0xE004.0FFF0xE004.0000
Reserved0xFFFF.FFFF0xE004.1000
For details,
see page ...
ARM®
Cortex™-M3
Technical
Reference
Manual
-Reserved0xE000.DFFF0xE000.3000
ARM®
Cortex™-M3
Technical
Reference
Manual
-Reserved0xE003.FFFF0xE000.F000
ARM®
Cortex™-M3
Technical
Reference
Manual
-
Texas Instruments-Advance Information
65February 09, 2010
Interrupts
4 Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 4-1 on page 66 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 37 interrupts (listed in Table 4-2 on page 67).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. Priorities can be grouped by splitting priority levels into pre-emption priorities and
subpriorities. All of the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
Important: It may take several processor cycles after a write to clear an interrupt source for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Table 4-1. Exception Types
a
Exception Type
Interrupt (NMI)
Management
Vector
Number
-3 (highest)1Reset
-22Non-Maskable
-13Hard Fault
programmable4Memory
DescriptionPriority
Stack top is loaded from the first entry of the vector table on reset.-0-
This exception is invoked on power up and warm reset. On the first
instruction, Reset drops to the lowest priority (and then is called the
base level of activation). This exception is asynchronous.
This exception is caused by the assertion of the NMI signal or by using
the NVIC Interrupt Control State register and cannot be stopped or
preempted by any exception but Reset. This exception is asynchronous.
This exception is caused by all classes of Fault, when the fault cannot
activate due to priority or the configurable fault handler has been
disabled. This exception is synchronous.
This exception is caused by an MPU mismatch, including access
violation and no match. This exception is synchronous.
Texas Instruments-Advance Information
February 09, 201066
Table 4-1. Exception Types (continued)
a
Exception Type
Interrupts
a. 0 is the default priority for all the programmable priorities.
Vector
Number
programmable5Bus Fault
programmable6Usage Fault
programmable11SVCall
programmable12Debug Monitor
programmable14PendSV
programmable15SysTick
programmable16 and
above
DescriptionPriority
This exception is caused by a pre-fetch fault, memory access fault, and
other address/memory related faults. This exception is synchronous
when precise and asynchronous when imprecise.
This fault can be enabled or disabled.
This exception is caused by a usage fault, such as undefined instruction
executed or illegal state transition attempt. This exception is
synchronous.
Reserved.-7-10-
This exception is caused by a system service call with an SVC
instruction. This exception is synchronous.
This exception is caused by the debug monitor (when not halting). This
exception is synchronous, but only active when enabled. This exception
does not activate if it is a lower priority than the current activation.
Reserved.-13-
This exception is caused by a pendable request for system service. This
exception is asynchronous and only pended by software.
This exception is caused by the SysTick timer reaching 0, when it is
enabled to generate an interrupt. This exception is asynchronous.
This exception is caused by interrupts asserted from outside the ARM
Cortex-M3 core and fed through the NVIC (prioritized). These exceptions
are all asynchronous. Table 4-2 on page 67 lists the interrupts on the
LM3S1R21 controller.
Stellaris® LM3S1R21 Microcontroller
Table 4-2. Interrupts
Vector Number
DescriptionInterrupt Number (Bit in
Interrupt Registers)
Processor exceptions-0-15
GPIO Port A016
GPIO Port B117
GPIO Port C218
GPIO Port D319
GPIO Port E420
UART0521
UART1622
SSI0723
I2C0824
Reserved9-1325-29
ADC0 Sequence 01430
ADC0 Sequence 11531
ADC0 Sequence 21632
ADC0 Sequence 31733
Watchdog Timers 0 and 11834
Timer 0A1935
Timer 0B2036
Texas Instruments-Advance Information
67February 09, 2010
Interrupts
Table 4-2. Interrupts (continued)
Vector Number
DescriptionInterrupt Number (Bit in
Interrupt Registers)
Timer 1A2137
Timer 1B2238
Timer 2A2339
Timer 2B2440
Analog Comparator 02541
Analog Comparator 12642
Reserved2743
System Control2844
Flash Memory Control2945
GPIO Port F3046
GPIO Port G3147
GPIO Port H3248
UART23349
SSI13450
Timer 3A3551
Timer 3B3652
I2C13753
Reserved38-4254-58
Hibernation Module4359
Reserved44-4560-61
µDMA Software4662
µDMA Error4763
Reserved48-5264-68
EPI5369
GPIO Port J5470
Reserved5571
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5 JTAG Interface
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is comprised of four pins: TCK, TMS, TDI, and TDO. Data is transmitted serially into
the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent
on the current state of the TAP controller. For detailed information on the operation of the JTAG
port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The Stellaris®JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core
by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM
TDO output while Stellaris®JTAG instructions select the Stellaris®TDO output. The multiplexer is
controlled by the Stellaris®JTAG controller, which has comprehensive programming for the ARM,
Stellaris®, and unimplemented JTAG instructions.
Stellaris® LM3S1R21 Microcontroller
The Stellaris®JTAG module has the following features:
■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
■ Four-bit Instruction Register (IR) chain for storing JTAG instructions
■ IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
■ ARM additional instructions: APACC, DPACC and ABORT
■ Integrated ARM Serial Wire Debug (SWD)
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG
controller.
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69February 09, 2010
Instruction Register (IR)
TAP Controller
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TCK
TMS
TDI
TDO
Cortex-M3
Debug
Port
JTAG Interface
5.1 Block Diagram
Figure 5-1. JTAG Module Block Diagram
5.2 Signal Description
Table 5-1 on page 70 and Table 5-2 on page 71 list the external signals of the JTAG/SWD controller
and describe the function of each. The JTAG/SWD controller signals are alternate functions for
some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function.
The JTAG/SWD controller signals are under commit protection and require a special process to be
configured as GPIOs, see “Commit Control” on page 299. The column in the table below titled "Pin
Mux/Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL
bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 315) is set to choose the
JTAG/SWD function.The number in parentheses is the encoding that must be programmed into the
PMCn field in the GPIO Port Control (GPIOPCTL) register (page 333) to assign the JTAG/SWD
controller signals to the specified GPIO port pin. For more information on configuring GPIOs, see
“General-Purpose Input/Outputs (GPIOs)” on page 291.
Table 5-1. Signals for JTAG_SWD_SWO (100LQFP)
Pin NumberPin Name
Assignment
Pin TypePin Mux / Pin
a
DescriptionBuffer Type
JTAG/SWD CLK.TTLIPC0 (3)80SWCLK
JTAG TMS and SWDIO.TTLI/OPC1 (3)79SWDIO
JTAG TDO and SWO.TTLOPC3 (3)77SWO
JTAG/SWD CLK.TTLIPC0 (3)80TCK
JTAG TDI.TTLIPC2 (3)78TDI
JTAG TDO and SWO.TTLOPC3 (3)77TDO
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Table 5-1. Signals for JTAG_SWD_SWO (100LQFP) (continued)
Pin NumberPin Name
Assignment
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Pin TypePin Mux / Pin
Table 5-2. Signals for JTAG_SWD_SWO (108BGA)
Pin NumberPin Name
Assignment
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Pin TypePin Mux / Pin
Stellaris® LM3S1R21 Microcontroller
a
DescriptionBuffer Type
JTAG TMS and SWDIO.TTLIPC1 (3)79TMS
a
DescriptionBuffer Type
JTAG/SWD CLK.TTLIPC0 (3)A9SWCLK
JTAG TMS and SWDIO.TTLI/OPC1 (3)B9SWDIO
JTAG TDO and SWO.TTLOPC3 (3)A10SWO
JTAG/SWD CLK.TTLIPC0 (3)A9TCK
JTAG TDI.TTLIPC2 (3)B8TDI
JTAG TDO and SWO.TTLOPC3 (3)A10TDO
JTAG TMS and SWDIO.TTLIPC1 (3)B9TMS
5.3 Functional Description
A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 70. The JTAG
module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel
update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs.
The current state of the TAP controller depends on the sequence of values captured on TMS at the
rising edge of TCK. The TAP controller determines when the serial shift chains capture new data,
shift data from TDI towards TDO, and update the parallel load registers. The current state of the
TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register
(DR) chains is being accessed.
The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR)
chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load
register determines which DR chain is captured, shifted, or updated during the sequencing of the
TAP controller.
Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not
capture, shift, or update any of the chains. Instructions that are not implemented decode to the
BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see
Table 5-4 on page 77 for a list of implemented instructions).
See “JTAG and Boundary Scan” on page 774 for JTAG timing diagrams.
Note: Of all the possible reset sources, only Power-On reset (POR) and the assertion of the RST
input have any effect on the JTAG module. The pin configurations are reset by both the
RST input and POR, whereas the internal JTAG logic is only reset with POR. See “Reset
Sources” on page 82 for more information on reset.
5.3.1 JTAG Interface Pins
The JTAG interface consists of four standard pins: TCK, TMS, TDI, and TDO. These pins and their
associated state after a power-on reset or reset caused by the RST input are given in Table 5-3.
Detailed information on each pin follows. Refer to “General-Purpose Input/Outputs (GPIOs)” on page
291 for information on how to reprogram the configuration of these pins.
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JTAG Interface
Table 5-3. JTAG Port Pins State after Power-On Reset or RST assertion
5.3.1.1 Test Clock Input (TCK)
The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate
independently of any other system clocks and to ensure that multiple JTAG TAP controllers that
are daisy-chained together can synchronously communicate serial test data between components.
During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When
necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0
or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data
Registers is not lost.
By default, the internal pull-up resistor on the TCK pin is enabled after reset, assuring that no clocking
occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors
can be turned off to save internal power as long as the TCK pin is constantly being driven by an
external source (see page 321 and page 323).
Drive ValueDrive StrengthInternal Pull-DownInternal Pull-UpData DirectionPin Name
N/AN/ADisabledEnabledInputTCK
N/AN/ADisabledEnabledInputTMS
N/AN/ADisabledEnabledInputTDI
High-Z2-mA driverDisabledEnabledOutputTDO
5.3.1.2 Test Mode Select (TMS)
The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge
of TCK. Depending on the current TAP state and the sampled value of TMS, the next state may be
entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1
expects the value on TMS to change on the falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the
Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG
module and associated registers are reset to their default values. This procedure should be performed
to initialize the JTAG controller. The JTAG Test Access Port state machine can be seen in its entirety
in Figure 5-2 on page 73.
By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC1/TMS; otherwise JTAG communication could be lost (see page 321).
5.3.1.3 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is
sampled on the rising edge of TCK and, depending on the current TAP state and the current
instruction, may present this data to the proper shift register chain. Because the TDI pin is sampled
on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the
falling edge of TCK.
By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up
resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled
on PC2/TDI; otherwise JTAG communication could be lost (see page 321).
5.3.1.4 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR chains.
The value of TDO depends on the current TAP state, the current instruction, and the data in the
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February 09, 201072
chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin
Test Logic Reset
Run Test Idle Select DR Scan Select IR Scan
Capture DR Capture IR
Shift DR Shift IR
Exit 1 DR Exit 1 IR
Exit 2 DR Exit 2 IR
Pause DR Pause IR
Update DR Update IR
1 11
1 1
1
1 1
1 1
1 1
1 1
1 10 0
00
00
0 0
0 0
0 0
00
0
0
is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected
to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects
the value on TDO to change on the falling edge of TCK.
By default, the internal pull-up resistor on the TDO pin is enabled after reset, assuring that the pin
remains at a constant logic level when the JTAG port is not being used. The internal pull-up and
pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable
during certain TAP controller states (see page 321 and page 323).
5.3.2 JTAG TAP Controller
The JTAG TAP controller state machine is shown in Figure 5-2. The TAP controller state machine
is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR). In order to reset
the JTAG module after the microcontroller has been powered on, the TMS input must be held HIGH
for five TCK clock cycles, resetting the TAP controller and all associated JTAG chains. Asserting
the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in
data, or idle during extended testing sequences. For detailed information on the function of the TAP
controller and the operations that occur in each state, please refer to IEEE Standard 1149.1.
Figure 5-2. Test Access Port State Machine
Stellaris® LM3S1R21 Microcontroller
5.3.3 Shift Registers
The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift
register chain samples specific information during the TAP controller’s CAPTURE states and allows
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JTAG Interface
this information to be shifted out on TDOduring the TAP controller’s SHIFT states. While the sampled
data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register
on TDI. This new data is stored in the parallel load register during the TAP controller’s UPDATE
states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 77.
5.3.4 Operational Considerations
Certain operational parameters must be considered when using the JTAG module. Because the
JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these
pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire
Debug, the method for switching between these two operational modes is described below.
5.3.4.1 GPIO Functionality
When the microcontroller is reset with either a POR or RST, the JTAG/SWD port pins default to their
JTAG/SWD configurations. The default configuration includes enabling digital functionality (DEN[3:0]
set in the Port C GPIO Digital Enable (GPIODEN) register), enabling the pull-up resistors (PUE[3:0]
set in the Port C GPIO Pull-Up Select (GPIOPUR) register), disabling the pull-down resistors
(PDE[3:0] cleared in the Port C GPIO Pull-Down Select (GPIOPDR) register) and enabling the
alternate hardware function (AFSEL[3:0] set in the Port C GPIO Alternate Function Select
(GPIOAFSEL) register) on the JTAG/SWD pins. See page 315, page 321, page 323, and page 326.
It is possible for software to configure these pins as GPIOs after reset by clearing AFSEL[3:0] in
the Port C GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or
board-level testing, this provides four more GPIOs for use in the design.
Caution – It is possible to create a software sequence that prevents the debugger from connecting to
the Stellaris®microcontroller. If the program code loaded into ash immediately changes the JTAG
pins to their GPIO functionality, the debugger may not have enough time to connect and halt the
controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of
the part. This issue can be avoided with a software routine that restores JTAG functionality based on
an external or software trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of
critical hardware peripherals. Protection is currently provided for the NMI pin (PB7) and the four
JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO Alternate Function Select
(GPIOAFSEL) register (see page 315), GPIO Pull Up Select (GPIOPUR) register (see page 321),
GPIO Pull-Down Select (GPIOPDR) register (see page 323), and GPIO Digital Enable (GPIODEN)
register (see page 326) are not committed to storage unless the GPIO Lock (GPIOLOCK) register
(see page 328) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register
(see page 329) have been set.
5.3.4.2 Communication with JTAG/SWD
Because the debug clock and the system clock can be running at different frequencies, care must
be taken to maintain reliable communication with the JTAG/SWD interface. In the Capture-DR state,
the result of the previous transaction, if any, is returned, together with a 3-bit ACK response. Software
should check the ACK response to see if the previous operation has completed before initiating a
new transaction. Alternatively, if the system clock is at least 8 times faster than the debug clock
(TCK or SWCLK), the previous operation has enough time to complete and the ACK bits do not have
to be checked.
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5.3.4.3 Recovering a "Locked" Microcontroller
Note: Performing the sequence below restores the nonvolatile registers discussed in “Nonvolatile
Register Programming” on page 204 to their factory default values. The mass erase of the
Flash memory caused by the sequence below occurs prior to the nonvolatile registers being
restored.
If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate
with the debugger, there is a debug sequence that can be used to recover the microcontroller.
Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the
microcontroller in reset mass erases the Flash memory. The sequence to recover the microcontroller
is:
1. Assert and hold the RST signal.
2. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence on the section called “JTAG-to-SWD
Switching” on page 76.
3. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence on the section called “SWD-to-JTAG
Switching” on page 76.
4. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
Stellaris® LM3S1R21 Microcontroller
5. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
6. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
7. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
8. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
9. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
10. Perform steps 1 and 2 of the JTAG-to-SWD switch sequence.
11. Perform steps 1 and 2 of the SWD-to-JTAG switch sequence.
12. Release the RST signal.
13. Wait 400 ms.
14. Power-cycle the microcontroller.
5.3.4.4 ARM Serial Wire Debug (SWD)
In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire
debugger must be able to connect to the Cortex-M3 core without having to perform, or have any
knowledge of, JTAG cycles. This integration is accomplished with a SWD preamble that is issued
before the SWD session begins.
The switching preamble used to enable the SWD interface of the SWJ-DP module starts with the
TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller
through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic
Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run
Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states.
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Stepping through this sequence of the TAP state machine enables the SWD interface and disables
the JTAG interface. For more information on this operation and the SWD interface, see the ARM®
Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual.
Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG
TAP controller is not fully compliant to the IEEE Standard 1149.1. This instance is the only one
where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to
the low probability of this sequence occurring during normal operation of the TAP controller, it should
not affect normal performance of the JTAG interface.
JTAG-to-SWD Switching
To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the
external debug hardware must send the switching preamble to the microcontroller. The 16-bit TMS
command for switching to SWD mode is defined as b1110.0111.1001.1110, transmitted LSB first.
This command can also be represented as 0xE79E when transmitted LSB first. The complete switch
sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
2. Send the 16-bit JTAG-to-SWD switch command, 0xE79E, on TMS.
are in their reset/idle states.
3. Send at least 50 TCK/SWCLKcycles with TMS/SWDIOHigh to ensure that if SWJ-DP was already
in SWD mode, the SWD goes into the line reset state before sending the switch sequence.
SWD-to-JTAG Switching
To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the
external debug hardware must send a switch command to the microcontroller. The 16-bit TMS
command for switching to JTAG mode is defined as b1110.0111.0011.1100, transmitted LSB first.
This command can also be represented as 0xE73C when transmitted LSB first. The complete switch
sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals:
1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO High to ensure that both JTAG and SWD
are in their reset/idle states.
2. Send the 16-bit SWD-to-JTAG switch command, 0xE73C, on TMS.
3. Send at least 50 TCK/SWCLKcycles with TMS/SWDIOHigh to ensure that if SWJ-DP was already
in JTAG mode, the JTAG goes into the Test Logic Reset state before sending the switch
sequence.
5.4 Initialization and Configuration
After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for
JTAG communication. No user-defined initialization or configuration is needed. However, if the user
application changes these pins to their GPIO function, they must be configured back to their JTAG
functionality before JTAG communication can be restored. To return the pins to their JTAG functions,
enable the four JTAG pins (PC[3:0]) for their alternate function using the GPIOAFSEL register.
In addition to enabling the alternate functions, any other changes to the GPIO pad configurations
on the four JTAG pins (PC[3:0]) should be returned to their default settings.
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5.5 Register Descriptions
The registers in the JTAG TAP Controller or Shift Register chains are not memory mapped and are
not accessible through the on-chip Advanced Peripheral Bus (APB). Instead, the registers within
the JTAG controller are all accessed serially through the TAP Controller. These registers include
the Instruction Register and the six Data Registers.
5.5.1 Instruction Register (IR)
The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain connected between the JTAG
TDI and TDO pins with a parallel load register. When the TAP Controller is placed in the correct
states, bits can be shifted into the IR. Once these bits have been shifted into the chain and updated,
they are interpreted as the current instruction. The decode of the IR bits is shown in Table 5-4. A
detailed explanation of each instruction, along with its associated Data Register, follows.
Table 5-4. JTAG Instruction Register Commands
EXTEST0x0
INTEST0x1
SAMPLE / PRELOAD0x2
IDCODE0xE
ReservedAll Others
Stellaris® LM3S1R21 Microcontroller
DescriptionInstructionIR[3:0]
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction onto the pads.
Drives the values preloaded into the Boundary Scan Chain by the
SAMPLE/PRELOAD instruction into the controller.
Captures the current I/O values and shifts the sampled values out of the
Boundary Scan Chain while new preload data is shifted in.
Shifts data into the ARM Debug Port Abort Register.ABORT0x8
Shifts data into and out of the ARM DP Access Register.DPACC0xA
Shifts data into and out of the ARM AC Access Register.APACC0xB
Loads manufacturing information defined by the IEEE Standard 1149.1 into
the IDCODE chain and shifts it out.
Connects TDI to TDO through a single Shift Register chain.BYPASS0xF
Defaults to the BYPASS instruction to ensure that TDI is always connected
to TDO.
5.5.1.1 EXTEST Instruction
The EXTEST instruction is not associated with its own Data Register chain. Instead, the EXTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the outputs and output
enables are used to drive the GPIO pads rather than the signals coming from the core. With tests
that drive known values out of the controller, this instruction can be used to verify connectivity. While
the EXTEST instruction is present in the Instruction Register, the Boundary Scan Data Register can
be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
5.5.1.2 INTEST Instruction
The INTEST instruction is not associated with its own Data Register chain. Instead, the INTEST
instruction uses the data that has been preloaded into the Boundary Scan Data Register using the
SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register,
the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive
the signals going into the core rather than the signals coming from the GPIO pads. With tests that
drive known values into the controller, this instruction can be used for testing. It is important to note
that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable.
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While the INTEST instruction is present in the Instruction Register, the Boundary Scan Data Register
can be accessed to sample and shift out the current data and load new data into the Boundary Scan
Data Register.
5.5.1.3 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between
TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads
new test data. Each GPIO pad has an associated input, output, and output enable signal. When the
TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable
signals to each of the GPIO pads are captured. These samples are serially shifted out on TDO while
the TAP controller is in the Shift DR state and can be used for observation or comparison in various
tests.
While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary
Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI.
Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the
parallel load registers when the TAP controller enters the Update DR state. This update of the
parallel load register preloads data into the Boundary Scan Data Register that is associated with
each input, output, and output enable. This preloaded data can be used with the EXTEST and
INTEST instructions to drive data into or out of the controller. See “Boundary Scan Data
Register” on page 79 for more information.
5.5.1.4 ABORT Instruction
The ABORT instruction connects the associated ABORT Data Register chain between TDI and
TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates
a DAP abort of a previous request. See the “ABORT Data Register” on page 80 for more information.
5.5.1.5 DPACC Instruction
The DPACC instruction connects the associated DPACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to the ARM debug and status registers. See “DPACC Data
Register” on page 80 for more information.
5.5.1.6 APACC Instruction
The APACC instruction connects the associated APACC Data Register chain between TDI and
TDO. This instruction provides read and write access to the APACC Register of the ARM Debug
Access Port (DAP). Shifting the proper data into this register and reading the data output from this
register allows read and write access to internal components and buses through the Debug Port.
See “APACC Data Register” on page 80 for more information.
5.5.1.7 IDCODE Instruction
The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and
TDO. This instruction provides information on the manufacturer, part number, and version of the
ARM core. This information can be used by testing equipment and debuggers to automatically
configure input and output data streams. IDCODE is the default instruction loaded into the JTAG
Instruction Register when a Power-On-Reset (POR) is asserted, or the Test-Logic-Reset state is
entered. See “IDCODE Data Register” on page 79 for more information.
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5.5.1.8 BYPASS Instruction
Version Part Number Manufacturer ID 1
31 28 27 12 11 1 0
TDOTDI
0
TDO
TDI
0
The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and
TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports.
The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by
allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain
by loading them with the BYPASS instruction. See “BYPASS Data Register” on page 79 for more
information.
5.5.2 Data Registers
The JTAG module contains six Data Registers. These serial Data Register chains include: IDCODE,
BYPASS, Boundary Scan, APACC, DPACC, and ABORT and are discussed in the following sections.
5.5.2.1 IDCODE Data Register
The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-3. The standard requires that every JTAG-compliant microcontroller implement either the
IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE
Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB
of 0. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.
Stellaris® LM3S1R21 Microcontroller
The major uses of the JTAG port are for manufacturer testing of component assembly and program
development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE
instruction outputs a value of 0x4BA0.0477. This value allows the debuggers to automatically
configure themselves to work correctly with the Cortex-M3 during debug.
Figure 5-3. IDCODE Register Format
5.5.2.2 BYPASS Data Register
The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in
Figure 5-4. The standard requires that every JTAG-compliant microcontroller implement either the
BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS
Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB
of 1. This definition allows auto-configuration test tools to determine which instruction is the default
instruction.
Figure 5-4. BYPASS Register Format
5.5.2.3 Boundary Scan Data Register
The format of the Boundary Scan Data Register is shown in Figure 5-5. Each GPIO pin, starting
with a GPIO pin next to the JTAG port pins, is included in the Boundary Scan Data Register. Each
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79February 09, 2010
I
N
TDI
1
st
GPIO
TDO
...
O
U
T
O
E
I
N
m
th
GPIO
O
U
T
O
E
I
N
(m+1)
th
GPIO
O
U
T
O
E
...
I
N
GPIO n
th
O
U
T
O
E
JTAG Interface
GPIO pin has three associated digital signals that are included in the chain. These signals are input,
output, and output enable, and are arranged in that order as shown in the figure.
When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the
input, output, and output enable from each digital pad are sampled and then shifted out of the chain
to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR
state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain
in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with
the EXTEST and INTEST instructions. The EXTEST instruction forces data out of the controller,
and the INTEST instruction forces data into the controller.
Figure 5-5. Boundary Scan Register Format
5.5.2.4 APACC Data Register
The format for the 35-bit APACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.5.2.5 DPACC Data Register
The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
5.5.2.6 ABORT Data Register
The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM®
Cortex™-M3 Technical Reference Manual.
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February 09, 201080
6 System Control
System control configures the overall operation of the device and provides information about the
device. Configurable features include reset control, NMI operation, power control, clock control, and
low-power modes.
6.1 Signal Description
Table 6-1 on page 81 and Table 6-2 on page 81 list the external signals of the System Control
module and describe the function of each. The NMI signal is the alternate function for the GPIO PB7
signal and functions as a GPIO after reset. PB7 is under commit protection and requires a special
process to be configured as the NMI signal or to subsequently return to the GPIO function, see
“Commit Control” on page 299. The column in the table below titled "Pin Mux/Pin Assignment" lists
the GPIO pin placement for the NMI signal. The AFSEL bit in the GPIO Alternate Function Select
(GPIOAFSEL) register (page 315) should be set to choose the NMI function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 333) to assign the NMI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 291. The
remaining signals (with the word "fixed" in the Pin Mux/Pin Assignment column) have a fixed pin
assignment and function.
Stellaris® LM3S1R21 Microcontroller
Table 6-1. Signals for System Control & Clocks (100LQFP)
Pin NumberPin Name
Assignment
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Pin TypePin Mux / Pin
Table 6-2. Signals for System Control & Clocks (108BGA)
Pin NumberPin Name
Assignment
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Pin TypePin Mux / Pin
6.2 Functional Description
The System Control module provides the following capabilities:
a
DescriptionBuffer Type
Non-maskable interrupt.TTLIPB7 (4)89NMI
AnalogIfixed48OSC0
AnalogIfixedL11OSC0
Main oscillator crystal input or an external clock
reference input.
Main oscillator crystal output.AnalogOfixed49OSC1
System reset input.TTLIfixed64RST
a
DescriptionBuffer Type
Non-maskable interrupt.TTLIPB7 (4)A8NMI
Main oscillator crystal input or an external clock
reference input.
Main oscillator crystal output.AnalogOfixedM11OSC1
System reset input.TTLIfixedH11RST
■ Device identification, see “Device Identification” on page 82
■ Local control, such as reset (see “Reset Control” on page 82), power (see “Power
Control” on page 86) and clock control (see “Clock Control” on page 87)
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System Control
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 93
6.2.1 Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, Flash memory size, and other features. See the DID0 (page 97), DID1
(page 124), DC0-DC9 (page 126) and NVMSTAT (page 143) registers.
6.2.2 Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
6.2.2.1 Reset Sources
The LM3S1R21 microcontroller has six sources of reset:
1. Power-on reset (POR) (see page 82).
2. External reset input pin (RST) assertion (see page 83).
3. Internal brown-out (BOR) detector (see page 84).
4. Software-initiated reset (with the software reset registers) (see page 85).
5. A watchdog timer reset condition violation (see page 85).
6. MOSC failure (see page 86).
Table 6-3 provides a summary of results of the various reset operations.
Table 6-3. Reset Sources
On-Chip Peripherals Reset?JTAG Reset?Core Reset?Reset Source
YesYesYesPower-On Reset
YesPin Config OnlyYesRST
YesNoYesBrown-Out Reset
Software System Request
Reset
a. By using the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register
b. Programmable on a module-by-module basis using the Software Reset Control Registers.
a
NoNoSoftware Peripheral Reset
YesNoYes
Yes
YesNoYesWatchdog Reset
YesNoYesMOSC Failure Reset
b
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, in which case, all the bits in the RESC register are cleared except for the POR indicator.
A bit in the RESC register can be cleared by writing a 0.
6.2.2.2 Power-On Reset (POR)
Note: The power-on reset also resets the JTAG controller. An external reset does not.
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February 09, 201082
The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates
PU
RST
Stellaris®
R
VDD
a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a
threshold value (VTH). The microcontroller must be operating within the specified operating parameters
when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the microcontroller
must reach 3.0 V within 10 msec of VDDcrossing 2.0 V to guarantee proper operation. For applications
that require the use of an external reset signal to hold the microcontroller in reset longer than the
internal POR, the RST input may be used as discussed in “External RST Pin” on page 83.
The Power-On Reset sequence is as follows:
1. The microcontroller waits for internal POR to go inactive.
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
The internal POR is only active on the initial power-up of the microcontroller. The Power-On Reset
timing is shown in Figure 22-5 on page 776.
6.2.2.3 External RST Pin
Note: It is recommended that the trace for the RST signal must be kept as short as possible. Be
sure to place any components connected to the RST signal as close to the microcontroller
as possible.
Stellaris® LM3S1R21 Microcontroller
If the application only uses the internal POR circuit, the RST input must be connected to the power
supply (VDD) through an optional pull-up resistor (0 to 100K Ω) as shown in Figure 6-1 on page 83.
Figure 6-1. Basic RST Configuration
RPU= 0 to 100 kΩ
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 69). The external reset
sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by T
and then de-asserted
MIN
(see “Reset” on page 775).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 6-2 on page 84.
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PU
C
1
RST
Stellaris®
R
VDD
PU
C
1
R
S
RST
Stellaris®
R
VDD
System Control
Figure 6-2. External Circuitry to Extend Power-On Reset
RPU= 1 kΩ to 100 kΩ
C1= 1 nF to 10 µF
If the application requires the use of an external reset switch, Figure 6-3 on page 84 shows the
proper circuitry to use.
Figure 6-3. Reset Circuit Controlled by Switch
Typical RPU= 10 kΩ
Typical RS= 470 Ω
C1= 10 nF
The RPUand C1components define the power-on delay.
The external reset timing is shown in Figure 22-4 on page 775.
6.2.2.4 Brown-Out Reset (BOR)
The microcontroller provides a brown-out detection circuit that triggers if the power supply (VDD)
drops below a brown-out threshold voltage (V
may generate an interrupt or a system reset. The default condition is to generate an interrupt, so
BOR must be enabled. Brown-out resets are controlled with the Power-On and Brown-Out Reset
Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out
condition to trigger a reset; if BORIOR is clear, an interrupt is generated. When a Brown-out condition
occurs during a Flash PROGRAM or ERASE operation, a full system reset is always triggered
without regard to the setting in the PBORCTL register.
The brown-out reset sequence is as follows:
1. When VDDdrops below V
Texas Instruments-Advance Information
). If a brown-out condition is detected, the system
BTH
, an internal BOR condition is set.
BTH
February 09, 201084
2. If the BOR condition exists, an internal reset is asserted.
3. The internal reset is released and the microcontroller fetches and loads the initial stack pointer,
the initial program counter, the first instruction designated by the program counter, and begins
execution.
4. The internal BOR condition is reset after 500 µs to prevent another BOR condition from being
set before software has a chance to investigate the original cause.
The result of a brown-out reset is equivalent to that of an assertion of the external RST input, and
the reset is held active until the proper VDDlevel is restored. The RESC register can be examined
in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus
allowing software to determine what actions are required to recover.
The internal Brown-Out Reset timing is shown in Figure 22-6 on page 776.
6.2.2.5 Software Reset
Software can reset a specific peripheral or generate a reset to the entire microcontroller.
Peripherals can be individually reset by software via three registers that control reset signals to each
on-chip peripheral (see the SRCRn registers, page 165). If the bit position corresponding to a
peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers
is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see
“System Control” on page 93).
Stellaris® LM3S1R21 Microcontroller
The entire microcontroller including the core can be reset by software by setting the SYSRESETREQ
bit in the Cortex-M3 Application Interrupt and Reset Control register. The software-initiated system
reset sequence is as follows:
1. A software microcontroller reset is initiated by setting the SYSRESETREQ bit in the ARM
Cortex-M3 Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is deasserted and the microcontroller loads from memory the initial stack
pointer, the initial program counter, and the first instruction designated by the program counter,
and then begins execution.
The software-initiated system reset timing is shown in Figure 22-7 on page 776.
6.2.2.6 Watchdog Timer Reset
The Watchdog Timer module's function is to prevent system hangs. The LM3S1R21 microcontroller
has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run
off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module
operates in the same manner except that because the PIOSC watchdog timer module is in a different
clock domain, register accesses must have a time delay between them. The watchdog timer can
be configured to generate an interrupt to the microcontroller on its first time-out and to generate a
reset on its second time-out.
After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of
the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If
the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal
has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog
timer reset sequence is as follows:
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System Control
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the microcontroller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
For more information on the Watchdog Timer module, see “Watchdog Timers” on page 466.
The watchdog reset timing is shown in Figure 22-8 on page 776.
6.2.3 Non-Maskable Interrupt
The microcontroller has three sources of non-maskable interrupt (NMI):
■ The assertion of the NMI signal
■ A main oscillator verification error
■ The NMISET bit in the Interrupt Control and Status (ICSR) register in the Cortex-M3.
Software must check the cause of the interrupt in order to distinguish among the sources.
6.2.3.1 NMI Pin
The alternate function to GPIO port pin B7 is an NMI signal. The alternate function must be enabled
in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs
(GPIOs)” on page 291. Note that enabling the NMI alternate function requires the use of the GPIO
lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality, see
page 329. The active sense of the NMI signal is High; asserting the enabled NMI signal above V
initiates the NMI interrupt sequence.
6.2.3.2 Main Oscillator Verification Failure
The LM3S1R21 microcontroller provides a main oscillator verification circuit that generates an error
condition if the oscillator is running too fast or two slow. The main oscillator verification circuit can
be programmed to generate a reset event, at which time a Power-on Reset is generated and control
is transferred to the NMI handler. The NMI handler is used to address the main oscillator verification
failure because the necessary code can be removed from the general reset handler, speeding up
reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator
Control (MOSCCTL) register. The main oscillator verification error is indicated in the main oscillator
fail status (MOSCFAIL) bit in the Reset Cause (RESC) register. The main oscillator verification circuit
action is described in more detail in “Main Oscillator Verification Circuit” on page 93.
6.2.4 Power Control
The Stellaris®microcontroller provides an integrated LDO regulator that is used to provide power
to the majority of the microcontroller's internal logic. For power reduction, a non-programmable LDO
may be used to scale the microcontroller’s 3.3 V input voltage to 1.2V. The voltage output has a
minimum voltage of 1.08 V and a maximum of 1.35 V. The LDO delivers up to 60 ma.
IH
Figure 6-4 shows the power architecture.
Note: On the printed circuit board, use the LDO output as the source of VDDC input. In addition,
the LDO requires decoupling capacitors. See “On-Chip Low Drop-Out (LDO) Regulator
Characteristics” on page 769.
February 09, 201086
Texas Instruments-Advance Information
Figure 6-4. Power Architecture
Analog Circuits
(ADC, Analog
Comparators)
I/O Buffers
Low-Noise
LDO
Internal
Logic and PLL
GND
GNDA
GNDA
VDDA
VDDA
VDDC
VDDC
LDO
+3.3V
GND
GND
GND
VDD
VDD
Stellaris® LM3S1R21 Microcontroller
6.2.5 Clock Control
System control determines the control of clocks in this part.
6.2.5.1 Fundamental Clock Sources
There are multiple clock sources for use in the microcontroller:
■ Precision Internal Oscillator (PIOSC). The precision internal oscillator is an on-chip clock
source that is the clock source the microcontroller uses during and following POR. It does not
require the use of any external components and provides a clock that is 16 MHz ±1% at room
temperature and ±3% across temperature. The PIOSC allows for a reduced system cost in
applications that require an accurate clock source. If the main oscillator is required, software
must enable the main oscillator following reset and allow the main oscillator to stabilize before
changing the clock reference. If the Hibernation Module clock source is a 32.768-kHz oscillator,
the precision internal oscillator can be trimmed by software based on a reference clock for
increased accuracy.
■ Main Oscillator (MOSC). The main oscillator provides a frequency-accurate clock source by
one of two means: an external single-ended clock source is connected to the OSC0 input pin, or
an external crystal is connected across the OSC0 input and OSC1 output pins. If the PLL is being
used, the crystal value must be one of the supported frequencies between 3.579545 MHz through
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System Control
■ Internal 30-kHz Oscillator. The internal 30-kHz oscillator provides an operational frequency of
■ Hibernation Module Clock Source. The Hibernation module can be clocked in one of two ways.
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL and the precision internal oscillator divided by four (4 MHz ± 1%).
The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 16.384 MHz
(inclusive). Table 6-4 on page 88 shows how the various clock sources can be used in a system.
16.384 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported
frequencies between 1 MHz and 16.384 MHz. The single-ended clock source range is from DC
through the specified speed of the microcontroller. The supported crystals are listed in the XTAL
bit field in the RCC register (see page 108).
30 kHz ± 50%. It is intended for use during Deep-Sleep power-saving modes. This power-savings
mode benefits from reduced internal switching and also allows the MOSC and PIOSC to be
powered down.
The first way is a 4.194304-MHz crystal connected to the XOSC0 and XOSC1 pins. This clock
signal is divided by 128 internally to produce the 32.768-kHz clock reference. The second way
is a 32.768-kHz oscillator connected to the XOSC0 pin. The clock source for the Hibernation
module can be used for the system clock, thus eliminating the need for an additional crystal or
oscillator. In addition, a 4.194304-MHz crystal can also be a source for the PLL. The Hibernation
module clock source is intended to provide the system with a real-time clock source and may
also provide an accurate source of Deep-Sleep or Hibernate mode power savings.
Table 6-4. Clock Source Options
by 4 (4 MHz ± 1%)
Crystal
Oscillator
6.2.5.2 Clock Configuration
The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2)
registers provide control for the system clock. The RCC2 register is provided to extend fields that
offer additional encodings over the RCC register. When used, the RCC2 register field values are
used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for
a larger assortment of clock configuration options. These registers control the following clock
functionality:
■ Source of clocks in sleep and deep-sleep modes
Used as SysClk?Drive PLL?Clock Source
YesPrecision Internal Oscillator
0x1
YesMain Oscillator
0x0
YesHibernation Module 4.194304-MHz
0x7
BYPASS = 1, OSCSRC = 0x1YesBYPASS = 0, OSCSRC =
BYPASS = 1, OSCSRC = 0x2YesBYPASS = 1NoPrecision Internal Oscillator divide
BYPASS = 1, OSCSRC = 0x0YesBYPASS = 0, OSCSRC =
BYPASS = 1, OSCSRC = 0x3YesBYPASS = 1NoInternal 30-kHz Oscillator
BYPASS = 1, OSCSRC2 = 0x6YesBYPASS = 0, OSCSRC2 =
BYPASS = 1, OSCSRC2 = 0x7YesBYPASS = 1NoHibernation Module 32.768-kHz
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
Texas Instruments-Advance Information
February 09, 201088
■ Clock divisors
Main OSC
Precision
Internal OSC
(16 MHz)
Internal OSC
(30 kHz)
÷ 4
÷ 25
PWRDN
ADC Clock
System Clock
MOSCDIS
a
IOSCDIS
a
SYSDIV
e
USESYSDIV
a,d
PWMDW
a
USEPWMDIV
a
PWM Clock
Hibernation
OSC
OSCSRC
b,d
BYPASS
b,d
XTAL
a
PWRDN
b
÷ 2
f
USB PLL
(240 MHz)
÷ 4
USB Clock
XTAL
a
USBPWRDN
c
RXINT
RXFRAC
I
2
S Receive MCLK
I
2
S Transmit MCLK
PLL
(400 MHz)
TXINT
TXFRAC
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2 bit, or
[SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set.
f. Only a 4.194304-Mhz crystal can be used to drive the PLL.
DIV400
c
■ Crystal input selection
Figure 6-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled. The ADC clock signal is automatically divided
down to 16 MHz for proper ADC operation.
Note: When the ADC module is in operation, the system clock must be at least 16 MHz.
Figure 6-5. Main Clock Tree
Stellaris® LM3S1R21 Microcontroller
Note: The figure above shows all features available on all Stellaris® Tempest-class microcontrollers.
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System Control
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 6-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 6-4 on page 88.
Table 6-5. Possible System Clock Frequencies Using the SYSDIV Field
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
Frequency (BYPASS=1)Frequency (BYPASS=0)DivisorSYSDIV
StellarisWare Parameter
SYSCTL_SYSDIV_1Clock source frequencyreserved/10x0
SYSCTL_SYSDIV_2Clock source frequency/2reserved/20x1
SYSCTL_SYSDIV_3Clock source frequency/366.67 MHz/30x2
SYSCTL_SYSDIV_4Clock source frequency/450 MHz/40x3
SYSCTL_SYSDIV_5Clock source frequency/540 MHz/50x4
SYSCTL_SYSDIV_6Clock source frequency/633.33 MHz/60x5
SYSCTL_SYSDIV_7Clock source frequency/728.57 MHz/70x6
SYSCTL_SYSDIV_8Clock source frequency/825 MHz/80x7
SYSCTL_SYSDIV_9Clock source frequency/922.22 MHz/90x8
SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x9
SYSCTL_SYSDIV_11Clock source frequency/1118.18 MHz/110xA
SYSCTL_SYSDIV_12Clock source frequency/1216.67 MHz/120xB
SYSCTL_SYSDIV_13Clock source frequency/1315.38 MHz/130xC
SYSCTL_SYSDIV_14Clock source frequency/1414.29 MHz/140xD
SYSCTL_SYSDIV_15Clock source frequency/1513.33 MHz/150xE
SYSCTL_SYSDIV_16Clock source frequency/1612.5 MHz (default)/160xF
a
The SYSDIV2 field in the RCC2 register is 2 bits wider than the SYSDIV field in the RCC register
so that additional larger divisors up to /64 are possible, allowing a lower system clock frequency for
improved Deep Sleep power consumption. When using the PLL, the VCO frequency of 400 MHz is
predivided by 2 before the divisor is applied. The divisor is equivalent to the SYSDIV2 encoding
plus 1. Table 6-6 shows how the SYSDIV2 encoding affects the system clock frequency, depending
on whether the PLL is used (BYPASS2=0) or another clock source is used (BYPASS2=1). For a list
of possible clock sources, see Table 6-4 on page 88.
Table 6-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
DivisorSYSDIV2
(BYPASS2=0)
Frequency (BYPASS2=1)Frequency
StellarisWare Parameter
SYSCTL_SYSDIV_1Clock source frequencyreserved/10x00
SYSCTL_SYSDIV_2Clock source frequency/2reserved/20x01
SYSCTL_SYSDIV_3Clock source frequency/366.67 MHz/30x02
SYSCTL_SYSDIV_4Clock source frequency/450 MHz/40x03
...............
SYSCTL_SYSDIV_10Clock source frequency/1020 MHz/100x09
...............
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Texas Instruments-Advance Information
a
Stellaris® LM3S1R21 Microcontroller
Table 6-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field
(continued)
DivisorSYSDIV2
(BYPASS2=0)
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
Frequency (BYPASS2=1)Frequency
StellarisWare Parameter
SYSCTL_SYSDIV_64Clock source frequency/643.125 MHz/640x3F
a
To allow for additional frequency choices when using the PLL, the DIV400 bit is provided along
with the SYSDIV2LSB bit. When the DIV400 bit is set, bit 22 becomes the LSB for SYSDIV2. In
this situation, the divisor is equivalent to the (SYSDIV2 encoding with SYSDIV2LSB appended) plus
one. When the DIV400 bit is clear, SYSDIV2LSB is ignored, and the system clock frequency is
determined as shown in Table 6-6 on page 90. Care must be taken when using these frequency
choices with StellarisWare DriverLib API functions. see Table 6-7.
Table 6-7. Examples of Possible System Clock Frequencies with DIV400=1
a
DivisorSYSDIV2LSBSYSDIV2
a. Note that DIV400 and SYSDIV2LSB are only valid when BYPASS2=0.
b. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
Frequency (BYPASS2=0)
StellarisWare Parameter
-reserved/2reserved0x00
-reserved/300x01
-reserved/41
SYSCTL_SYSDIV_2_580 MHz/500x02
SYSCTL_SYSDIV_366.67 MHz/61
-reserved/700x03
SYSCTL_SYSDIV_450 MHz/81
SYSCTL_SYSDIV_4_544.44 MHz/900x04
SYSCTL_SYSDIV_540 MHz/101
...............
SYSCTL_SYSDIV_63_53.15 MHz/12700x3F
SYSCTL_SYSDIV_643.125 MHz/1281
b
6.2.5.3 Precision Internal Oscillator Operation (PIOSC)
The microcontroller powers up with the PIOSC running. If another clock source is desired, the PIOSC
can be powered down by setting the IOSCDIS bit in the RCC register.
The PIOSC generates a 16 MHz clock with a ±1% accuracy at room temperatures. Across the
extended temperature range, the accuracy is ±3%. At the factory, the PIOSC is set to 16 MHz at
room temperature, however, the frequency can be trimmed for other voltage or temperature conditions
using software in one of three ways:
■ Default calibration: clear the UTENbit and set the UPDATE bit in the Precision Internal Oscillator
Calibration (PIOSCCAL) register.
■ User-defined calibration: The user can program the UT value to adjust the PIOSC frequency. As
the UT value increases, the generated period increases. To commit a new UT value, first set the
UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within
a few clock periods and is glitch free.
Texas Instruments-Advance Information
91February 09, 2010
System Control
■ Automatic calibration using the enable 32.768-kHz oscillator from the Hibernation module: set
the CAL bit; the results of the calibration are shown in the RESULT field in the Precision Internal
Oscillator Statistic (PIOSCSTAT) register. After calibration is complete, the PIOSC is trimmed
using trimmed value returned in the CT field.
6.2.5.4 Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 16.384 MHz, otherwise,
the range of supported crystals is 1 to 16.384 MHz.
The XTALbit in the RCC register (see page 108) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
6.2.5.5 Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor.
To configure the PIOSC to be the clock source for the main PLL, program the OSCRC2 field in the
Run-Mode Clock Configuration 2 (RCC2) register to be 0x1.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 112). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency. Table 22-9 on page 772 shows the actual PLL frequency and error for
a given crystal choice.
To configure the Hibernation module 4.194304-MHz crystal as the PLL input reference, program
the OSCSRC2 field in the Run-Mode Clock Configuration 2 (RCC2) register to be 0x6.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 108)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
6.2.5.6 PLL Modes
two modes of operation: Normal and Power-Down
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 108 and page 115).
6.2.5.7 PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is T
READY
(see Table
22-8 on page 771). During the relock time, the affected PLL is not usable as a clock reference.
PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
February 09, 201092
Texas Instruments-Advance Information
■ Change in the PLL from Power-Down to Normal mode.
Stellaris® LM3S1R21 Microcontroller
A counter is defined to measure the T
READY
oscillator. The range of the main oscillator has been taken into account and the down counter is set
to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). When the XTAL value is
greater than 0x0F, the down counter is set to 0x2400 to maintain the required lock time on higher
frequency crystal inputs. Hardware is provided to keep the PLL from being used as a system clock
until the T
condition is met after one of the two changes above. It is the user's responsibility
READY
to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched
to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the microcontroller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (T
READY
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
6.2.5.8 Main Oscillator Verification Circuit
The clock control includes circuitry to ensure that the main oscillator is running at the appropriate
frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside
of the allowable band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, the following sequence is performed by the
hardware:
requirement. The counter is clocked by the main
time met), after which it changes to the PLL. Software
1. The MOSCFAIL bit in the Reset Cause (RESC) register is set.
2. If the internal oscillator (PIOSC) is disabled, it is enabled.
3. The system clock is switched from the main oscillator to the PIOSC.
4. An internal power-on reset is initiated that lasts for 32 PIOSC periods.
5. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence.
6.2.6 System Control
For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the microcontroller is in Run, Sleep, and
Deep-Sleep mode, respectively. The DC1 , DC2 and DC4 registers act as a write mask for the
RCGCn , SCGCn, and DCGCn registers.
There are four levels of operation for the microcontroller defined as:
■ Run Mode. In Run mode, the microcontroller actively executes code. Run mode provides normal
operation of the processor and all of the peripherals that are currently enabled by the RCGCn
registers. The system clock can be any of the available clock sources including the PLL.
■ Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the
processor and the memory subsystem are not clocked and therefore no longer execute code.
Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction.
Any properly configured interrupt event in the system brings the processor back into Run mode.
Texas Instruments-Advance Information
93February 09, 2010
System Control
■ Deep-Sleep Mode. In Deep-Sleep mode, the clock frequency of the active peripherals may
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled
(see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system
clock has the same source and frequency as that during Run mode.
change (depending on the Run mode clock configuration) in addition to the processor clock being
stopped. An interrupt returns the microcontroller to Run mode from one of the sleep modes; the
sleep modes are entered on request from the code. Deep-Sleep mode is entered by first writing
the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing
a WFI instruction. Any properly configured interrupt event in the system brings the processor
back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical
Reference Manual for more details.
The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are
clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC
register) or the RCGCn register when auto-clock gating is disabled. The system clock source is
specified in the DSLPCLKCFG register. When the DSLPCLKCFG register is used, the internal
oscillator source is powered up, if necessary, and other clocks are powered down. If the PLL is
running at the time of the WFI instruction, hardware powers the PLL down and overrides the
SYSDIV field of the active RCC/RCC2 register, to be determined by the DSDIVORIDE setting in
the DSLPCLKCFG register, up to /16 or /64 respectively. When the Deep-Sleep exit event
occurs, hardware brings the system clock back to the source and frequency it had at the onset
of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep
duration. If the PIOSC or the 4.194304-MHz Hibernation module clock source is used as the
PLL reference clock source, it may continue to provide the clock during Deep-Sleep. See page 119.
■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the
microcontroller and only the Hibernation module's circuitry is active. An external wake event or
RTC event is required to bring the microcontroller back to Run mode. The Cortex-M3 processor
and peripherals outside of the Hibernation module see a normal "power on" sequence and the
processor starts running code. Software can determine if the microcontroller has been restarted
from Hibernate mode by inspecting the Hibernation module registers.
Caution – If the Cortex-M3 Debug Access Port (DAP) has been enabled, and the device wakes from a
low power sleep or deep-sleep mode, the core may start executing code before all clocks to peripherals
have been restored to their run mode conguration. The DAP is usually enabled by software tools
accessing the JTAG or SWD interface when debugging or ash programming. If this condition occurs,
a Hard Fault is triggered when software accesses a peripheral with an invalid clock.
A software delay loop can be used at the beginning of the interrupt routine that is used to wake up a
system from a WFI (Wait For Interrupt) instruction. This stalls the execution of any code that accesses
a peripheral register that might cause a fault. This loop can be removed for production software as the
DAP is most likely not enabled during normal execution.
Because the DAP is disabled by default (power on reset), the user can also power cycle the device. The
DAP is not enabled unless it is enabled through the JTAG or SWD interface.
Texas Instruments-Advance Information
February 09, 201094
6.3 Initialization and Configuration
The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register
is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps
required to successfully change the PLL-based system clock are:
1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS
bit in the RCC register, thereby configuring the microcontroller to run off a “raw” clock source
and allowing for the new PLL configuration to be validated before switching the system clock
to the PLL.
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in
RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output.
3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The
SYSDIV field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
Stellaris® LM3S1R21 Microcontroller
6.4 Register Map
Table 6-8 on page 95 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use. Software should not modify any reserved memory address.
Additional Flash and ROM registers defined in the System Control register space are
described in the “Internal Memory” on page 199.
Table 6-8. System Control Register Map
DescriptionResetTypeNameOffset
See
page
97Device Identification 0-RODID00x000
124Device Identification 1-RODID10x004
126Device Capabilities 00x00BF.007FRODC00x008
127Device Capabilities 1-RODC10x010
129Device Capabilities 20x430F.5037RODC20x014
131Device Capabilities 30xBFFF.0FC0RODC30x018
133Device Capabilities 40x0004.F1FFRODC40x01C
Texas Instruments-Advance Information
135Device Capabilities 50x0000.0000RODC50x020
136Device Capabilities 60x0000.0000RODC60x024
137Device Capabilities 70xFFFF.FFFFRODC70x028
141Device Capabilities 8 ADC Channels0x0000.00FFRODC80x02C
95February 09, 2010
System Control
Table 6-8. System Control Register Map (continued)
DescriptionResetTypeNameOffset
See
page
99Brown-Out Reset Control0x0000.7FFDR/WPBORCTL0x030
165Software Reset Control 00x00000000R/WSRCR00x040
167Software Reset Control 10x00000000R/WSRCR10x044
170Software Reset Control 20x00000000R/WSRCR20x048
100Raw Interrupt Status0x0000.0000RORIS0x050
102Interrupt Mask Control0x0000.0000R/WIMC0x054
104Masked Interrupt Status and Clear0x0000.0000R/W1CMISC0x058
106Reset Cause-R/WRESC0x05C
108Run-Mode Clock Configuration0x0780.3AD1R/WRCC0x060
112XTAL to PLL Translation-ROPLLCFG0x064
113GPIO High-Performance Bus Control0x0000.0000R/WGPIOHBCTL0x06C
115Run-Mode Clock Configuration 20x07C0.6810R/WRCC20x070
118Main Oscillator Control0x0000.0000R/WMOSCCTL0x07C
144Run Mode Clock Gating Control Register 00x00000040R/WRCGC00x100
150Run Mode Clock Gating Control Register 10x00000000R/WRCGC10x104
6.5 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
159Run Mode Clock Gating Control Register 20x00000000R/WRCGC20x108
146Sleep Mode Clock Gating Control Register 00x00000040R/WSCGC00x110
153Sleep Mode Clock Gating Control Register 10x00000000R/WSCGC10x114
161Sleep Mode Clock Gating Control Register 20x00000000R/WSCGC20x118
148Deep Sleep Mode Clock Gating Control Register 00x00000040R/WDCGC00x120
156Deep-Sleep Mode Clock Gating Control Register 10x00000000R/WDCGC10x124
163Deep Sleep Mode Clock Gating Control Register 20x00000000R/WDCGC20x128
119Deep Sleep Clock Configuration0x0780.0000R/WDSLPCLKCFG0x144
121Precision Internal Oscillator Calibration0x0000.0000R/WPIOSCCAL0x150
123Precision Internal Oscillator Statistics0x0000.0040ROPIOSCSTAT0x154
142Device Capabilities 9 ADC Digital Comparators0x0000.00FFRODC90x190
143Non-Volatile Memory Information0x0000.0001RONVMSTAT0x1A0
Texas Instruments-Advance Information
February 09, 201096
Register 1: Device Identification 0 (DID0), offset 0x000
This register identifies the version of the microcontroller.
Device Identification 0 (DID0)
Base 0x400F.E000
Offset 0x000
Type RO, reset -
reserved
Stellaris® LM3S1R21 Microcontroller
16171819202122232425262728293031
CLASSreservedVER
ROROROROROROROROROROROROROROROROType
0010000000001000Reset
0123456789101112131415
MINORMAJOR
ROROROROROROROROROROROROROROROROType
----------------Reset
DescriptionResetTypeNameBit/Field
0ROreserved31
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x1ROVER30:28
DID0 Version
This field defines the DID0 register format version. The version number
is numeric. The value of the VER field is encoded as follows (all other
encodings are reserved):
DescriptionValue
Second version of the DID0 register format.0x1
0x0ROreserved27:24
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x04ROCLASS23:16
Device Class
The CLASS field value identifies the internal design from which all mask
sets are generated for all microcontrollers in a particular product line.
The CLASS field value is changed for new product lines, for changes in
fab process (for example, a remap or shrink), or any case where the
MAJOR or MINORfields require differentiation from prior microcontrollers.
The value of the CLASS field is encoded as follows (all other encodings
are reserved):
DescriptionValue
Stellaris® Tempest-class microcontrollers0x04
Texas Instruments-Advance Information
97February 09, 2010
System Control
DescriptionResetTypeNameBit/Field
-ROMAJOR15:8
-ROMINOR7:0
Major Revision
This field specifies the major revision number of the microcontroller.
The major revision reflects changes to base layers of the design. The
major revision number is indicated in the part number as a letter (A for
first revision, B for second, and so on). This field is encoded as follows:
DescriptionValue
Revision A (initial device)0x0
Revision B (first base layer revision)0x1
Revision C (second base layer revision)0x2
and so on.
Minor Revision
This field specifies the minor revision number of the microcontroller.
The minor revision reflects changes to the metal layers of the design.
The MINOR field value is reset when the MAJOR field is changed. This
field is numeric and is encoded as follows:
DescriptionValue
Initial device, or a major revision update.0x0
First metal layer change.0x1
Second metal layer change.0x2
and so on.
Texas Instruments-Advance Information
February 09, 201098
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030
This register is responsible for controlling reset conditions after initial power-on reset.
Brown-Out Reset Control (PBORCTL)
Base 0x400F.E000
Offset 0x030
Type R/W, reset 0x0000.7FFD
reserved
DescriptionResetTypeNameBit/Field
Stellaris® LM3S1R21 Microcontroller
16171819202122232425262728293031
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
BORIORreserved
reserved
ROR/WROROROROROROROROROROROROROROType
0000000000000000Reset
0x0000.000ROreserved31:2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0R/WBORIOR1
BOR Interrupt or Reset
DescriptionValue
A Brown Out Event causes an interrupt to be generated to the
0
interrupt controller.
A Brown Out Event causes a reset of the microcontroller.1
0ROreserved0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Texas Instruments-Advance Information
99February 09, 2010
System Control
Register 3: Raw Interrupt Status (RIS), offset 0x050
This register indicates the status for system control raw interrupts. An interrupt is sent to the interrupt
controller if the corresponding bit in the Interrupt Mask Control (IMC) register is set. Writing a 1
to the corresponding bit in the Masked Interrupt Status and Clear (MISC) register clears an interrupt
status bit.
Raw Interrupt Status (RIS)
Base 0x400F.E000
Offset 0x050
Type RO, reset 0x0000.0000
reserved
reserved
MOSCPUPRIS
DescriptionResetTypeNameBit/Field
reserved
16171819202122232425262728293031
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
BORRISreservedPLLLRIS
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0x0000.00ROreserved31:9
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROMOSCPUPRIS8
MOSC Power Up Raw Interrupt Status
DescriptionValue
Sufficient time has passed for the MOSC to reach the expected
1
frequency. The value for this power-up time is indicated by
T
MOSC_SETTLE
Sufficient time has not passed for the MOSC to reach the
0
.
expected frequency.
This bit is cleared by writing a 1 to the MOSCPUPMIS bit in the MISC
register.
0ROreserved7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROPLLLRIS6
PLL Lock Raw Interrupt Status
DescriptionValue
The PLL timer has reached T
1
indicating that sufficient time
READY
has passed for the PLL to lock.
The PLL timer has not reached T
READY
.0
This bit is cleared by writing a 1 to the PLLLMIS bit in the MISC register.
0x0ROreserved5:2
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Texas Instruments-Advance Information
February 09, 2010100
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