Texas instruments STELLARIS LM3S1R21 DATA SHEET

TEXAS INSTRUMENTS-ADVANCE INFORMATION

Stellaris® LM3S1R21 Microcontroller

DATA SHEET

DS-LM3S1R21-6790	Copyright © 2007-2010 Texas Instruments
	Incorporated

Copyright

Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.

ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated

108 Wild Basin, Suite 350 Austin, TX 78746

http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

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		Stellaris® LM3S1R21 Microcontroller
Table of Contents
Revision History .............................................................................................................................		23
About This Document ....................................................................................................................		27
Audience ..............................................................................................................................................		27
About This Manual ................................................................................................................................		27
Related Documents ...............................................................................................................................		27
Documentation Conventions ..................................................................................................................		27
1	Architectural Overview ..........................................................................................	30
1.1	Functional Overview ......................................................................................................	32
1.1.1	ARM Cortex™-M3 .........................................................................................................	32
1.1.2	On-Chip Memory ...........................................................................................................	34
1.1.3	External Peripheral Interface .........................................................................................	35
1.1.4	Serial Communications Peripherals ................................................................................	36
1.1.5	System Integration ........................................................................................................	39
1.1.6	Analog ..........................................................................................................................	44
1.1.7	JTAG and ARM Serial Wire Debug ................................................................................	46
1.1.8	Packaging and Temperature ..........................................................................................	47
1.2	Target Applications ........................................................................................................	47
1.3	High-Level Block Diagram .............................................................................................	47
1.4	Additional Features .......................................................................................................	49
1.4.1	Memory Map ................................................................................................................	49
1.4.2	Hardware Details ..........................................................................................................	49
2	ARM Cortex-M3 Processor Core ...........................................................................	50
2.1	Block Diagram ..............................................................................................................	51
2.2	Functional Description ...................................................................................................	51
2.2.1	Programming Model ......................................................................................................	51
2.2.2	Serial Wire and JTAG Debug .........................................................................................	58
2.2.3	Embedded Trace Macrocell (ETM) .................................................................................	58
2.2.4	Trace Port Interface Unit (TPIU) .....................................................................................	58
2.2.5	ROM Table ...................................................................................................................	59
2.2.6	Memory Protection Unit (MPU) .......................................................................................	59
2.2.7	Nested Vectored Interrupt Controller (NVIC) ....................................................................	59
2.2.8	System Timer (SysTick) .................................................................................................	60
3	Memory Map ...........................................................................................................	63
4	Interrupts .................................................................................................................	66
5	JTAG Interface ........................................................................................................	69
5.1	Block Diagram ..............................................................................................................	70
5.2	Signal Description .........................................................................................................	70
5.3	Functional Description ...................................................................................................	71
5.3.1	JTAG Interface Pins ......................................................................................................	71
5.3.2	JTAG TAP Controller .....................................................................................................	73
5.3.3	Shift Registers ..............................................................................................................	73
5.3.4	Operational Considerations ............................................................................................	74
5.4	Initialization and Configuration .......................................................................................	76
5.5	Register Descriptions ....................................................................................................	77
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5.5.1	Instruction Register (IR) .................................................................................................	77
5.5.2	Data Registers ..............................................................................................................	79

6	System Control .......................................................................................................	81
6.1	Signal Description .........................................................................................................	81
6.2	Functional Description ...................................................................................................	81
6.2.1	Device Identification ......................................................................................................	82
6.2.2	Reset Control ................................................................................................................	82
6.2.3	Non-Maskable Interrupt .................................................................................................	86
6.2.4	Power Control ...............................................................................................................	86
6.2.5	Clock Control ................................................................................................................	87
6.2.6	System Control .............................................................................................................	93
6.3	Initialization and Configuration .......................................................................................	95
6.4	Register Map ................................................................................................................	95
6.5	Register Descriptions ....................................................................................................	96

7	Hibernation Module ..............................................................................................			172
7.1	Block Diagram ............................................................................................................			173
7.2	Signal Description .......................................................................................................			173
7.3	Functional Description .................................................................................................			174
7.3.1	Register Access Timing ...............................................................................................			175
7.3.2	Clock Source ..............................................................................................................			175
7.3.3	Battery Management ...................................................................................................			176
7.3.4	Real-Time Clock ..........................................................................................................			177
7.3.5	Non-Volatile Memory ...................................................................................................			177
7.3.6	Power Control Using			177
		HIB
7.3.7	Power Control Using VDD3ON Mode ...........................................................................			178
7.3.8	Initiating Hibernate ......................................................................................................			178
7.3.9	Interrupts and Status ...................................................................................................			178
7.4	Initialization and Configuration .....................................................................................			179
7.4.1	Initialization .................................................................................................................			179
7.4.2	RTC Match Functionality (No Hibernation) ....................................................................			180
7.4.3	RTC Match/Wake-Up from Hibernation .........................................................................			180
7.4.4	External Wake-Up from Hibernation ..............................................................................			180
7.4.5	RTC or External Wake-Up from Hibernation ..................................................................			180
7.4.6	Register Reset ............................................................................................................			181
7.5	Register Map ..............................................................................................................			181
7.6	Register Descriptions ..................................................................................................			182

8	Internal Memory ...................................................................................................	199
8.1	Block Diagram ............................................................................................................	199
8.2	Functional Description .................................................................................................	199
8.2.1	SRAM ........................................................................................................................	200
8.2.2	ROM ..........................................................................................................................	200
8.2.3	Flash Memory .............................................................................................................	200
8.3	Flash Memory Initialization and Configuration ...............................................................	202
8.3.1	Flash Memory Programming ........................................................................................	202
8.3.2	32-Word Flash Memory Write Buffer .............................................................................	203
8.3.3	Nonvolatile Register Programming ...............................................................................	204
8.4	Register Map ..............................................................................................................	205
8.5	Flash Memory Register Descriptions (Flash Control Offset) ............................................	206
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8.6	Memory Register Descriptions (System Control Offset) ..................................................	217
9	Micro Direct Memory Access (μDMA) ................................................................	233
9.1	Block Diagram ............................................................................................................	234
9.2	Functional Description .................................................................................................	234
9.2.1	Channel Assignments ..................................................................................................	235
9.2.2	Priority ........................................................................................................................	236
9.2.3	Arbitration Size ............................................................................................................	236
9.2.4	Request Types ............................................................................................................	236
9.2.5	Channel Configuration .................................................................................................	237
9.2.6	Transfer Modes ...........................................................................................................	239
9.2.7	Transfer Size and Increment ........................................................................................	247
9.2.8	Peripheral Interface .....................................................................................................	247
9.2.9	Software Request ........................................................................................................	247
9.2.10	Interrupts and Errors ....................................................................................................	248
9.3	Initialization and Configuration .....................................................................................	248
9.3.1	Module Initialization .....................................................................................................	248
9.3.2	Configuring a Memory-to-Memory Transfer ...................................................................	248
9.3.3	Configuring a Peripheral for Simple Transmit ................................................................	250
9.3.4	Configuring a Peripheral for Ping-Pong Receive ............................................................	251
9.3.5	Configuring Alternate Channels ....................................................................................	254
9.4	Register Map ..............................................................................................................	254
9.5	μDMA Channel Control Structure .................................................................................	255
9.6	μDMA Register Descriptions ........................................................................................	262
10	General-Purpose Input/Outputs (GPIOs) ...........................................................	291
10.1	Signal Description .......................................................................................................	291
10.2	Functional Description .................................................................................................	296
10.2.1	Data Control ...............................................................................................................	297
10.2.2	Interrupt Control ..........................................................................................................	298
10.2.3	Mode Control ..............................................................................................................	299
10.2.4	Commit Control ...........................................................................................................	299
10.2.5	Pad Control .................................................................................................................	300
10.2.6	Identification ...............................................................................................................	300
10.3	Initialization and Configuration .....................................................................................	300
10.4	Register Map ..............................................................................................................	301
10.5	Register Descriptions ..................................................................................................	304
11	External Peripheral Interface (EPI) .....................................................................	347
11.1	EPI Block Diagram ......................................................................................................	348
11.2	Signal Description .......................................................................................................	349
11.3	Functional Description .................................................................................................	351
11.3.1	Non-Blocking Reads ....................................................................................................	352
11.3.2	DMA Operation ...........................................................................................................	353
11.4	Initialization and Configuration .....................................................................................	353
11.4.1	SDRAM Mode .............................................................................................................	354
11.4.2	Host Bus Mode ...........................................................................................................	358
11.4.3	General-Purpose Mode ...............................................................................................	367
11.5	Register Map ..............................................................................................................	375
11.6	Register Descriptions ..................................................................................................	376

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12	General-Purpose Timers ......................................................................................	419
12.1	Block Diagram ............................................................................................................	420
12.2	Signal Description .......................................................................................................	420
12.3	Functional Description .................................................................................................	423
12.3.1	GPTM Reset Conditions ..............................................................................................	423
12.3.2	32-Bit Timer Operating Modes ......................................................................................	424
12.3.3	16-Bit Timer Operating Modes ......................................................................................	425
12.3.4	DMA Operation ...........................................................................................................	431
12.4	Initialization and Configuration .....................................................................................	431
12.4.1	32-Bit One-Shot/Periodic Timer Mode ...........................................................................	431
12.4.2	32-Bit Real-Time Clock (RTC) Mode .............................................................................	432
12.4.3	16-Bit One-Shot/Periodic Timer Mode ...........................................................................	432
12.4.4	16-Bit Input Edge-Count Mode .....................................................................................	433
12.4.5	16-Bit Input Edge Timing Mode ....................................................................................	433
12.4.6	16-Bit PWM Mode .......................................................................................................	434
12.5	Register Map ..............................................................................................................	434
12.6	Register Descriptions ..................................................................................................	435

13	Watchdog Timers .................................................................................................	466
13.1	Block Diagram ............................................................................................................	467
13.2	Functional Description .................................................................................................	467
13.2.1	Register Access Timing ...............................................................................................	468
13.3	Initialization and Configuration .....................................................................................	468
13.4	Register Map ..............................................................................................................	468
13.5	Register Descriptions ..................................................................................................	469

14	Analog-to-Digital Converter (ADC) .....................................................................	491
14.1	Block Diagram ............................................................................................................	492
14.2	Signal Description .......................................................................................................	492
14.3	Functional Description .................................................................................................	493
14.3.1	Sample Sequencers ....................................................................................................	493
14.3.2	Module Control ............................................................................................................	494
14.3.3	Hardware Sample Averaging Circuit .............................................................................	496
14.3.4	Analog-to-Digital Converter ..........................................................................................	496
14.3.5	Differential Sampling ...................................................................................................	498
14.3.6	Internal Temperature Sensor ........................................................................................	501
14.3.7	Digital Comparator Unit ...............................................................................................	501
14.4	Initialization and Configuration .....................................................................................	506
14.4.1	Module Initialization .....................................................................................................	506
14.4.2	Sample Sequencer Configuration .................................................................................	507
14.5	Register Map ..............................................................................................................	507
14.6	Register Descriptions ..................................................................................................	509

15	Universal Asynchronous Receivers/Transmitters (UARTs)	............................. 565
15.1	Block Diagram ............................................................................................................	566
15.2	Signal Description .......................................................................................................	566
15.3	Functional Description .................................................................................................	568
15.3.1	Transmit/Receive Logic ...............................................................................................	569
15.3.2	Baud-Rate Generation .................................................................................................	569
15.3.3	Data Transmission ......................................................................................................	570
15.3.4	Serial IR (SIR) .............................................................................................................	570
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		Stellaris® LM3S1R21 Microcontroller
15.3.5	ISO 7816 Support .......................................................................................................	571
15.3.6	Modem Handshake Support .........................................................................................	571
15.3.7	LIN Support ................................................................................................................	573
15.3.8	FIFO Operation ...........................................................................................................	574
15.3.9	Interrupts ....................................................................................................................	574
15.3.10	Loopback Operation ....................................................................................................	575
15.3.11	DMA Operation ...........................................................................................................	575
15.4	Initialization and Configuration .....................................................................................	576
15.5	Register Map ..............................................................................................................	577
15.6	Register Descriptions ..................................................................................................	578
16	Synchronous Serial Interface (SSI) ....................................................................	627
16.1	Block Diagram ............................................................................................................	628
16.2	Signal Description .......................................................................................................	628
16.3	Functional Description .................................................................................................	629
16.3.1	Bit Rate Generation .....................................................................................................	630
16.3.2	FIFO Operation ...........................................................................................................	630
16.3.3	Interrupts ....................................................................................................................	630
16.3.4	Frame Formats ...........................................................................................................	631
16.3.5	DMA Operation ...........................................................................................................	638
16.4	Initialization and Configuration .....................................................................................	639
16.5	Register Map ..............................................................................................................	640
16.6	Register Descriptions ..................................................................................................	641
17	Inter-Integrated Circuit (I2C) Interface ................................................................	669
17.1	Block Diagram ............................................................................................................	670
17.2	Signal Description .......................................................................................................	670
17.3	Functional Description .................................................................................................	671
17.3.1	I2C Bus Functional Overview ........................................................................................	671
17.3.2	Available Speed Modes ...............................................................................................	673
17.3.3	Interrupts ....................................................................................................................	674
17.3.4	Loopback Operation ....................................................................................................	675
17.3.5	Command Sequence Flow Charts ................................................................................	675
17.4	Initialization and Configuration .....................................................................................	682
17.5	Register Map ..............................................................................................................	683
17.6	Register Descriptions (I2C Master) ...............................................................................	684
17.7	Register Descriptions (I2C Slave) .................................................................................	697
18	Analog Comparators ............................................................................................	706
18.1	Block Diagram ............................................................................................................	706
18.2	Signal Description .......................................................................................................	707
18.3	Functional Description .................................................................................................	708
18.3.1	Internal Reference Programming ..................................................................................	708
18.4	Initialization and Configuration .....................................................................................	710
18.5	Register Map ..............................................................................................................	710
18.6	Register Descriptions ..................................................................................................	710
19	Pin Diagram ..........................................................................................................	718
20	Signal Tables ........................................................................................................	720
20.1	100-Pin LQFP Package Pin Tables ...............................................................................	720
20.2	108-Pin BGA Package Pin Tables ................................................................................	743
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21	Operating Characteristics ...................................................................................	767
22	Electrical Characteristics ....................................................................................	768
22.1	DC Characteristics ......................................................................................................	768
22.1.1	Maximum Ratings .......................................................................................................	768
22.1.2	Recommended DC Operating Conditions ......................................................................	768
22.1.3	On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................	769
22.1.4	Hibernation Module Characteristics ..............................................................................	769
22.1.5	Flash Memory Characteristics ......................................................................................	769
22.1.6	GPIO Module Characteristics .......................................................................................	770
22.1.7	Current Specifications ..................................................................................................	770
22.2	AC Characteristics .......................................................................................................	771
22.2.1	Load Conditions ..........................................................................................................	771
22.2.2	Clocks ........................................................................................................................	771
22.2.3	JTAG and Boundary Scan ............................................................................................	774
22.2.4	Reset .........................................................................................................................	775
22.2.5	Sleep Modes ...............................................................................................................	777
22.2.6	Hibernation Module .....................................................................................................	777
22.2.7	General-Purpose I/O (GPIO) ........................................................................................	778
22.2.8	External Peripheral Interface (EPI) ...............................................................................	778
22.2.9	Analog-to-Digital Converter ..........................................................................................	783
22.2.10	Synchronous Serial Interface (SSI) ...............................................................................	785
22.2.11	Inter-Integrated Circuit (I2C) Interface ...........................................................................	786
22.2.12	Ethernet Controller ......................................................................................................	787
22.2.13	Analog Comparator .....................................................................................................	788
A	Boot Loader ..........................................................................................................	789
A.1	Boot Loader Overview .................................................................................................	789
A.2	Serial Interfaces ..........................................................................................................	789
A.2.1	Serial Configuration .....................................................................................................	789
A.2.2	Serial Packet Handling ................................................................................................	790
A.2.3	Serial Commands ........................................................................................................	791
B	ROM DriverLib Functions ....................................................................................	794
B.1	DriverLib Functions Included in the Integrated ROM ......................................................	794
C	Register Quick Reference ...................................................................................	828
D	Ordering and Contact Information .....................................................................	850
D.1	Ordering Information ....................................................................................................	850
D.2	Part Markings ..............................................................................................................	850
D.3	Kits .............................................................................................................................	851
D.4	Support Information .....................................................................................................	851
E	Package Information ............................................................................................	852

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Stellaris® LM3S1R21 Microcontroller

List of Figures
Figure 1-1.	Stellaris® LM3S1R21 Microcontroller High-Level Block Diagram ............................	48
Figure 2-1.	CPU Block Diagram .............................................................................................	51
Figure 2-2.	TPIU Block Diagram ............................................................................................	59
Figure 5-1.	JTAG Module Block Diagram ................................................................................	70
Figure 5-2.	Test Access Port State Machine ...........................................................................	73
Figure 5-3.	IDCODE Register Format .....................................................................................	79
Figure 5-4.	BYPASS Register Format ....................................................................................	79
Figure 5-5.	Boundary Scan Register Format ...........................................................................	80
Figure 6-1.	Basic RST Configuration ......................................................................................	83
Figure 6-2.	External Circuitry to Extend Power-On Reset ........................................................	84
Figure 6-3.	Reset Circuit Controlled by Switch ........................................................................	84
Figure 6-4.	Power Architecture ..............................................................................................	87
Figure 6-5.	Main Clock Tree ..................................................................................................	89
Figure 7-1.	Hibernation Module Block Diagram .....................................................................	173
Figure 7-2.	Clock Source Using Crystal ................................................................................	176
Figure 7-3.	Clock Source Using Dedicated Oscillator and VDD3ON Mode ..............................	176
Figure 8-1.	Internal Memory Block Diagram ..........................................................................	199
Figure 9-1.	μDMA Block Diagram .........................................................................................	234
Figure 9-2.	Example of Ping-Pong μDMA Transaction ...........................................................	240
Figure 9-3.	Memory Scatter-Gather, Setup and Configuration ................................................	242
Figure 9-4.	Memory Scatter-Gather, μDMA Copy Sequence ..................................................	243
Figure 9-5.	Peripheral Scatter-Gather, Setup and Configuration .............................................	245
Figure 9-6.	Peripheral Scatter-Gather, μDMA Copy Sequence ...............................................	246
Figure 10-1.	Digital I/O Pads .................................................................................................	296
Figure 10-2.	Analog/Digital I/O Pads ......................................................................................	297
Figure 10-3.	GPIODATA Write Example .................................................................................	298
Figure 10-4.	GPIODATA Read Example .................................................................................	298
Figure 11-1.	EPI Block Diagram .............................................................................................	349
Figure 11-2.	SDRAM Non-Blocking Read Cycle ......................................................................	356
Figure 11-3.	SDRAM Normal Read Cycle ...............................................................................	357
Figure 11-4.	SDRAM Write Cycle ...........................................................................................	358
Figure 11-5.	Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 ..........................	365
Figure 11-6.	Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 ..........................	365
Figure 11-7.	Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
	= 1, RDHIGH = 1 ...............................................................................................	366
Figure 11-8.	Continuous Read Mode Accesses ......................................................................	366
Figure 11-9.	Write Followed by Read to External FIFO ............................................................	367
Figure 11-10.	Two-Entry FIFO .................................................................................................	367
Figure 11-11.	Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ...........................	371
Figure 11-12.	Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,
	WRCYC=1 ........................................................................................................	371
Figure 11-13.	Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................	372
Figure 11-14.	FRAME Signal Operation, FRM50=0 and FRMCNT=0 .........................................	372
Figure 11-15.	FRAME Signal Operation, FRM50=0 and FRMCNT=1 .........................................	372
Figure 11-16.	FRAME Signal Operation, FRM50=0 and FRMCNT=2 .........................................	373
Figure 11-17.	FRAME Signal Operation, FRM50=1 and FRMCNT=0 .........................................	373
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Figure 11-18.	FRAME Signal Operation, FRM50=1 and FRMCNT=1 .........................................	373
Figure 11-19.	FRAME Signal Operation, FRM50=1 and FRMCNT=2 .........................................	373
Figure 11-20.	iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 .........................	374
Figure 11-21.	EPI Clock Operation, CLKGATE=1, WR2CYC=0 .................................................	374
Figure 11-22.	EPI Clock Operation, CLKGATE=1, WR2CYC=1 .................................................	375
Figure 12-1.	GPTM Module Block Diagram ............................................................................	420
Figure 12-2.	16-Bit Input Edge-Count Mode Example ..............................................................	427
Figure 12-3.	16-Bit Input Edge-Time Mode Example ...............................................................	429
Figure 12-4.	16-Bit PWM Mode Example ................................................................................	430
Figure 12-5.	Timer Daisy Chain .............................................................................................	430
Figure 13-1.	WDT Module Block Diagram ..............................................................................	467
Figure 14-1.	ADC Module Block Diagram ...............................................................................	492
Figure 14-2.	Internal Voltage Conversion Result .....................................................................	497
Figure 14-3.	External Voltage Conversion Result ....................................................................	498
Figure 14-4.	Differential Sampling Range, VIN_ODD = 1.5 V ......................................................	499
Figure 14-5.	Differential Sampling Range, VIN_ODD = 0.75 V ....................................................	500
Figure 14-6.	Differential Sampling Range, VIN_ODD = 2.25 V ....................................................	500
Figure 14-7.	Internal Temperature Sensor Characteristic .........................................................	501
Figure 14-8.	Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................	504
Figure 14-9.	Mid-Band Operation (CIC=0x1 and/or CTC=0x1) .................................................	505
Figure 14-10.	High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................	506
Figure 15-1.	UART Module Block Diagram .............................................................................	566
Figure 15-2.	UART Character Frame .....................................................................................	569
Figure 15-3.	IrDA Data Modulation .........................................................................................	571
Figure 15-4.	LIN Message .....................................................................................................	573
Figure 15-5.	LIN Synchronization Field ...................................................................................	574
Figure 16-1.	SSI Module Block Diagram .................................................................................	628
Figure 16-2.	TI Synchronous Serial Frame Format (Single Transfer) ........................................	632
Figure 16-3.	TI Synchronous Serial Frame Format (Continuous Transfer) ................................	632
Figure 16-4.	Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ..........................	633
Figure 16-5.	Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ..................	633
Figure 16-6.	Freescale SPI Frame Format with SPO=0 and SPH=1 .........................................	634
Figure 16-7.	Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ...............	635
Figure 16-8.	Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........	635
Figure 16-9.	Freescale SPI Frame Format with SPO=1 and SPH=1 .........................................	636
Figure 16-10.	MICROWIRE Frame Format (Single Frame) ........................................................	637
Figure 16-11.	MICROWIRE Frame Format (Continuous Transfer) .............................................	638
Figure 16-12.	MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............	638
Figure 17-1.	I2C Block Diagram .............................................................................................	670
Figure 17-2.	I2C Bus Configuration ........................................................................................	671
Figure 17-3.	START and STOP Conditions .............................................................................	672
Figure 17-4.	Complete Data Transfer with a 7-Bit Address .......................................................	672
Figure 17-5.	R/S Bit in First Byte ............................................................................................	672
Figure 17-6.	Data Validity During Bit Transfer on the I2C Bus ...................................................	673
Figure 17-7.	Master Single TRANSMIT ..................................................................................	676
Figure 17-8.	Master Single RECEIVE .....................................................................................	677
Figure 17-9.	Master TRANSMIT with Repeated START ...........................................................	678
Figure 17-10.	Master RECEIVE with Repeated START .............................................................	679
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Figure 17-11.	Master RECEIVE with Repeated START after TRANSMIT with Repeated
	START ..............................................................................................................	680
Figure 17-12.	Master TRANSMIT with Repeated START after RECEIVE with Repeated
	START ..............................................................................................................	681
Figure 17-13.	Slave Command Sequence ................................................................................	682
Figure 18-1.	Analog Comparator Module Block Diagram .........................................................	706
Figure 18-2.	Structure of Comparator Unit ..............................................................................	708
Figure 18-3.	Comparator Internal Reference Structure ............................................................	709
Figure 19-1.	100-Pin LQFP Package Pin Diagram ..................................................................	718
Figure 19-2.	108-Ball BGA Package Pin Diagram (Top View) ...................................................	719
Figure 22-1.	Load Conditions ................................................................................................	771
Figure 22-2.	JTAG Test Clock Input Timing .............................................................................	774
Figure 22-3.	JTAG Test Access Port (TAP) Timing ..................................................................	775
Figure 22-4.	External Reset Timing (RST) ..............................................................................	775
Figure 22-5.	Power-On Reset Timing .....................................................................................	776
Figure 22-6.	Brown-Out Reset Timing ....................................................................................	776
Figure 22-7.	Software Reset Timing .......................................................................................	776
Figure 22-8.	Watchdog Reset Timing .....................................................................................	776
Figure 22-9.	MOSC Failure Reset Timing ...............................................................................	777
Figure 22-10.	Hibernation Module Timing with Internal Oscillator Running in Hibernation ............	778
Figure 22-11.	Hibernation Module Timing with Internal Oscillator Stopped in Hibernation ............	778
Figure 22-12.	SDRAM Initialization and Load Mode Register Timing ..........................................	780
Figure 22-13.	SDRAM Read Timing .........................................................................................	780
Figure 22-14.	SDRAM Write Timing .........................................................................................	781
Figure 22-15.	Host-Bus 8/16 Mode Read Timing ......................................................................	782
Figure 22-16.	Host-Bus 8/16 Mode Write Timing .......................................................................	782
Figure 22-17.	General-Purpose Mode Read and Write Timing ...................................................	783
Figure 22-18.	General-Purpose Mode iRDY Timing ..................................................................	783
Figure 22-19.	ADC Input Equivalency Diagram .........................................................................	784
Figure 22-20.	SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
	Measurement ....................................................................................................	785
Figure 22-21.	SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer .................	786
Figure 22-22.	SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .....................................	786
Figure 22-23.	I2C Timing .........................................................................................................	786
Figure 22-24.	Station Management Write Timing ......................................................................	787
Figure 22-25.	Station Management Read Timing ......................................................................	787
Figure 22-26.	MII Receive Timing ............................................................................................	788
Figure 22-27.	MII Transmit Timing ...........................................................................................	788
Figure E-1.	100-Pin LQFP Package ......................................................................................	852
Figure E-2.	108-Ball BGA Package ......................................................................................	854

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Table of Contents
List of Tables
Table 1.	Revision History ..................................................................................................	23
Table 2.	Documentation Conventions ................................................................................	27
Table 2-1.	16-Bit Cortex-M3 Instruction Set Summary ............................................................	52
Table 2-2.	32-Bit Cortex-M3 Instruction Set Summary ............................................................	54
Table 3-1.	Memory Map .......................................................................................................	63
Table 4-1.	Exception Types ..................................................................................................	66
Table 4-2.	Interrupts ............................................................................................................	67
Table 5-1.	Signals for JTAG_SWD_SWO (100LQFP) .............................................................	70
Table 5-2.	Signals for JTAG_SWD_SWO (108BGA) ..............................................................	71
Table 5-3.	JTAG Port Pins State after Power-On Reset or RST assertion ................................	72
Table 5-4.	JTAG Instruction Register Commands ...................................................................	77
Table 6-1.	Signals for System Control & Clocks (100LQFP) ...................................................	81
Table 6-2.	Signals for System Control & Clocks (108BGA) .....................................................	81
Table 6-3.	Reset Sources ....................................................................................................	82
Table 6-4.	Clock Source Options ..........................................................................................	88
Table 6-5.	Possible System Clock Frequencies Using the SYSDIV Field .................................	90
Table 6-6.	Examples of Possible System Clock Frequencies Using the SYSDIV2 Field ............	90
Table 6-7.	Examples of Possible System Clock Frequencies with DIV400=1 ...........................	91
Table 6-8.	System Control Register Map ...............................................................................	95
Table 6-9.	RCC2 Fields that Override RCC fields .................................................................	115
Table 7-1.	Signals for Hibernate (100LQFP) ........................................................................	173
Table 7-2.	Signals for Hibernate (108BGA) ..........................................................................	174
Table 7-3.	Hibernation Module Clock Operation ...................................................................	179
Table 7-4.	Hibernation Module Register Map .......................................................................	182
Table 8-1.	Flash Memory Protection Policy Combinations ....................................................	201
Table 8-2.	User-Programmable Flash Memory Resident Registers .......................................	204
Table 8-3.	Flash Register Map ............................................................................................	205
Table 9-1.	μDMA Channel Assignments ..............................................................................	235
Table 9-2.	Request Type Support .......................................................................................	236
Table 9-3.	Control Structure Memory Map ...........................................................................	238
Table 9-4.	Channel Control Structure ..................................................................................	238
Table 9-5.	μDMA Read Example: 8-Bit Peripheral ................................................................	247
Table 9-6.	μDMA Interrupt Assignments ..............................................................................	248
Table 9-7.	Channel Control Structure Offsets for Channel 30 ................................................	249
Table 9-8.	Channel Control Word Configuration for Memory Transfer Example ......................	249
Table 9-9.	Channel Control Structure Offsets for Channel 7 ..................................................	250
Table 9-10.	Channel Control Word Configuration for Peripheral Transmit Example ..................	251
Table 9-11.	Primary and Alternate Channel Control Structure Offsets for Channel 8 .................	252
Table 9-12.	Channel Control Word Configuration for Peripheral Ping-Pong Receive
	Example ............................................................................................................	253
Table 9-13.	μDMA Register Map ..........................................................................................	254
Table 10-1.	GPIO Pins With Non-Zero Reset Values ..............................................................	292
Table 10-2.	GPIO Pins and Alternate Functions (100LQFP) ...................................................	292
Table 10-3.	GPIO Pins and Alternate Functions (108BGA) .....................................................	294
Table 10-4.	GPIO Pad Configuration Examples .....................................................................	300
Table 10-5.	GPIO Interrupt Configuration Example ................................................................	301
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Stellaris® LM3S1R21 Microcontroller

Table 10-6.	GPIO Pins With Non-Zero Reset Values ..............................................................	302
Table 10-7.	GPIO Register Map ...........................................................................................	303
Table 10-8.	GPIO Pins With Non-Zero Reset Values ..............................................................	315
Table 10-9.	GPIO Pins With Non-Zero Reset Values ..............................................................	321
Table 10-10.	GPIO Pins With Non-Zero Reset Values ..............................................................	323
Table 10-11.	GPIO Pins With Non-Zero Reset Values ..............................................................	326
Table 10-12.	GPIO Pins With Non-Zero Reset Values ..............................................................	333
Table 11-1.	Signals for External Peripheral Interface (100LQFP) ............................................	349
Table 11-2.	Signals for External Peripheral Interface (108BGA) ..............................................	350
Table 11-3.	EPI SDRAM Signal Connections .........................................................................	355
Table 11-4.	Capabilities of Host Bus 8 and Host Bus 16 Modes ..............................................	359
Table 11-5.	EPI Host-Bus 8 Signal Connections ....................................................................	360
Table 11-6.	EPI Host-Bus 16 Signal Connections ..................................................................	361
Table 11-7.	EPI General Purpose Signal Connections ...........................................................	369
Table 11-8.	External Peripheral Interface (EPI) Register Map .................................................	375
Table 12-1.	Available CCP Pins ............................................................................................	420
Table 12-2.	Signals for General-Purpose Timers (100LQFP) ..................................................	421
Table 12-3.	Signals for General-Purpose Timers (108BGA) ....................................................	422
Table 12-4.	16-Bit Timer With Prescaler Configurations .........................................................	426
Table 12-5.	Timers Register Map ..........................................................................................	435
Table 13-1.	Watchdog Timers Register Map ..........................................................................	469
Table 14-1.	Signals for ADC (100LQFP) ...............................................................................	492
Table 14-2.	Signals for ADC (108BGA) .................................................................................	493
Table 14-3.	Samples and FIFO Depth of Sequencers ............................................................	494
Table 14-4.	Differential Sampling Pairs .................................................................................	498
Table 14-5.	ADC Register Map .............................................................................................	507
Table 15-1.	Signals for UART (100LQFP) .............................................................................	567
Table 15-2.	Signals for UART (108BGA) ...............................................................................	567
Table 15-3.	Flow Control Mode .............................................................................................	572
Table 15-4.	UART Register Map ...........................................................................................	577
Table 16-1.	Signals for SSI (100LQFP) .................................................................................	629
Table 16-2.	Signals for SSI (108BGA) ...................................................................................	629
Table 16-3.	SSI Register Map ..............................................................................................	640
Table 17-1.	Signals for I2C (100LQFP) .................................................................................	670
Table 17-2.	Signals for I2C (108BGA) ...................................................................................	670
Table 17-3.	Examples of I2C Master Timer Period versus Speed Mode ...................................	674
Table 17-4.	Inter-Integrated Circuit (I2C) Interface Register Map .............................................	683
Table 17-5.	Write Field Decoding for I2CMCS[3:0] Field .........................................................	689
Table 18-1.	Signals for Analog Comparators (100LQFP) ........................................................	707
Table 18-2.	Signals for Analog Comparators (108BGA) ..........................................................	707
Table 18-3.	Internal Reference Voltage and ACREFCTL Field Values .....................................	709
Table 18-4.	Analog Comparators Register Map .....................................................................	710
Table 20-1.	GPIO Pins With Default Alternate Functions ........................................................	720
Table 20-2.	Signals by Pin Number .......................................................................................	720
Table 20-3.	Signals by Signal Name .....................................................................................	728
Table 20-4.	Signals by Function, Except for GPIO .................................................................	736
Table 20-5.	GPIO Pins and Alternate Functions .....................................................................	741
Table 20-6.	Signals by Pin Number .......................................................................................	743

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Table of Contents

Table 20-7.	Signals by Signal Name .....................................................................................	752
Table 20-8.	Signals by Function, Except for GPIO .................................................................	759
Table 20-9.	GPIO Pins and Alternate Functions .....................................................................	764
Table 21-1.	Temperature Characteristics ...............................................................................	767
Table 21-2.	Thermal Characteristics .....................................................................................	767
Table 21-3.	ESD Absolute Maximum Ratings ........................................................................	767
Table 22-1.	Maximum Ratings ..............................................................................................	768
Table 22-2.	Recommended DC Operating Conditions ............................................................	768
Table 22-3.	LDO Regulator Characteristics ...........................................................................	769
Table 22-4.	Hibernation Module DC Characteristics ...............................................................	769
Table 22-5.	Flash Memory Characteristics ............................................................................	769
Table 22-6.	GPIO Module DC Characteristics ........................................................................	770
Table 22-7.	Preliminary Current Consumption .......................................................................	770
Table 22-8.	Phase Locked Loop (PLL) Characteristics ...........................................................	771
Table 22-9.	Actual PLL Frequency ........................................................................................	772
Table 22-10.	PIOSC Clock Characteristics ..............................................................................	772
Table 22-11.	30-kHz Clock Characteristics ..............................................................................	772
Table 22-12.	Hibernation Clock Characteristics .......................................................................	772
Table 22-13.	HIB Oscillator Input Characteristics .....................................................................	773
Table 22-14.	Main Oscillator Clock Characteristics ..................................................................	773
Table 22-15.	MOSC Oscillator Input Characteristics ................................................................	773
Table 22-16.	System Clock Characteristics with ADC Operation ...............................................	773
Table 22-17.	JTAG Characteristics .........................................................................................	774
Table 22-18.	Reset Characteristics .........................................................................................	775
Table 22-19.	Sleep Modes AC Characteristics .........................................................................	777
Table 22-20.	Hibernation Module AC Characteristics ...............................................................	777
Table 22-21.	GPIO Characteristics .........................................................................................	778
Table 22-22.	EPI SDRAM Characteristics ...............................................................................	779
Table 22-23.	EPI SDRAM Interface Characteristics .................................................................	779
Table 22-24.	EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics ...................................	781
Table 22-25.	EPI General-Purpose Interface Characteristics ....................................................	782
Table 22-26.	ADC Characteristics ...........................................................................................	783
Table 22-27.	ADC Module External Reference Characteristics .................................................	784
Table 22-28.	ADC Module Internal Reference Characteristics ..................................................	785
Table 22-29.	SSI Characteristics ............................................................................................	785
Table 22-30.	Ethernet Station Management ............................................................................	787
Table 22-31.	Ethernet MII ......................................................................................................	787
Table 22-32.	Analog Comparator Characteristics .....................................................................	788
Table 22-33.	Analog Comparator Voltage Reference Characteristics ........................................	788
Table D-1.	Part Ordering Information ...................................................................................	850

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Stellaris® LM3S1R21 Microcontroller

List of Registers
System Control ..............................................................................................................................		81
Register 1:	Device Identification 0 (DID0), offset 0x000 .......................................................................	97
Register 2:	Brown-Out Reset Control (PBORCTL), offset 0x030 ..........................................................	99
Register 3:	Raw Interrupt Status (RIS), offset 0x050 ..........................................................................	100
Register 4:	Interrupt Mask Control (IMC), offset 0x054 ......................................................................	102
Register 5:	Masked Interrupt Status and Clear (MISC), offset 0x058 ..................................................	104
Register 6:	Reset Cause (RESC), offset 0x05C ................................................................................	106
Register 7:	Run-Mode Clock Configuration (RCC), offset 0x060 .........................................................	108
Register 8:	XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................	112
Register 9:	GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ...................................	113
Register 10:	Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ....................................................	115
Register 11:	Main Oscillator Control (MOSCCTL), offset 0x07C ...........................................................	118
Register 12:	Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................	119
Register 13:	Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ...................................	121
Register 14:	Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 ....................................	123
Register 15:	Device Identification 1 (DID1), offset 0x004 .....................................................................	124
Register 16:	Device Capabilities 0 (DC0), offset 0x008 ........................................................................	126
Register 17:	Device Capabilities 1 (DC1), offset 0x010 ........................................................................	127
Register 18:	Device Capabilities 2 (DC2), offset 0x014 ........................................................................	129
Register 19:	Device Capabilities 3 (DC3), offset 0x018 ........................................................................	131
Register 20:	Device Capabilities 4 (DC4), offset 0x01C .......................................................................	133
Register 21:	Device Capabilities 5 (DC5), offset 0x020 ........................................................................	135
Register 22:	Device Capabilities 6 (DC6), offset 0x024 ........................................................................	136
Register 23:	Device Capabilities 7 (DC7), offset 0x028 ........................................................................	137
Register 24:	Device Capabilities 8 ADC Channels (DC8), offset 0x02C ................................................	141
Register 25:	Device Capabilities 9 ADC Digital Comparators (DC9), offset 0x190 .................................	142
Register 26:	Non-Volatile Memory Information (NVMSTAT), offset 0x1A0 .............................................	143
Register 27:	Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ...................................	144
Register 28:	Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................	146
Register 29:	Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 .......................	148
Register 30:	Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ...................................	150
Register 31:	Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................	153
Register 32:	Deep-Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 .......................	156
Register 33:	Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ...................................	159
Register 34:	Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................	161
Register 35:	Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 .......................	163
Register 36:	Software Reset Control 0 (SRCR0), offset 0x040 .............................................................	165
Register 37:	Software Reset Control 1 (SRCR1), offset 0x044 .............................................................	167
Register 38:	Software Reset Control 2 (SRCR2), offset 0x048 .............................................................	170
Hibernation Module .....................................................................................................................		172
Register 1:	Hibernation RTC Counter (HIBRTCC), offset 0x000 .........................................................	183
Register 2:	Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 .......................................................	184
Register 3:	Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 .......................................................	185
Register 4:	Hibernation RTC Load (HIBRTCLD), offset 0x00C ...........................................................	186
Register 5:	Hibernation Control (HIBCTL), offset 0x010 .....................................................................	187

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Table of Contents

Register 6:	Hibernation Interrupt Mask (HIBIM), offset 0x014 .............................................................	190
Register 7:	Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 ..................................................	192
Register 8:	Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................	194
Register 9:	Hibernation Interrupt Clear (HIBIC), offset 0x020 .............................................................	196
Register 10:	Hibernation RTC Trim (HIBRTCT), offset 0x024 ...............................................................	197
Register 11:	Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................	198
Internal Memory ...........................................................................................................................		199
Register 1:	Flash Memory Address (FMA), offset 0x000 ....................................................................	207
Register 2:	Flash Memory Data (FMD), offset 0x004 .........................................................................	208
Register 3:	Flash Memory Control (FMC), offset 0x008 .....................................................................	209
Register 4:	Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................	211
Register 5:	Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................	212
Register 6:	Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 .....................	213
Register 7:	Flash Memory Control 2 (FMC2), offset 0x020 .................................................................	214
Register 8:	Flash Write Buffer Valid (FWBVAL), offset 0x030 .............................................................	215
Register 9:	Flash Write Buffer n (FWBn), offset 0x100 - 0x17C ..........................................................	216
Register 10:	Flash Control (FCTL), offset 0x0F8 .................................................................................	217
Register 11:	ROM Control (RMCTL), offset 0x0F0 ..............................................................................	218
Register 12:	ROM Version Register (RMVER), offset 0x0F4 ................................................................	219
Register 13:	Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ...................	220
Register 14:	Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ...............	221
Register 15:	User Debug (USER_DBG), offset 0x1D0 .........................................................................	222
Register 16:	User Register 0 (USER_REG0), offset 0x1E0 ..................................................................	223
Register 17:	User Register 1 (USER_REG1), offset 0x1E4 ..................................................................	224
Register 18:	User Register 2 (USER_REG2), offset 0x1E8 ..................................................................	225
Register 19:	User Register 3 (USER_REG3), offset 0x1EC .................................................................	226
Register 20:	Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 ....................................	227
Register 21:	Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 ....................................	228
Register 22:	Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ...................................	229
Register 23:	Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ...............................	230
Register 24:	Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ...............................	231
Register 25:	Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ...............................	232
Micro Direct Memory Access (μDMA) ........................................................................................		233
Register 1:	DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ......................	256
Register 2:	DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................	257
Register 3:	DMA Channel Control Word (DMACHCTL), offset 0x008 ..................................................	258
Register 4:	DMA Status (DMASTAT), offset 0x000 ............................................................................	263
Register 5:	DMA Configuration (DMACFG), offset 0x004 ...................................................................	265
Register 6:	DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 ..................................	266
Register 7:	DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C ....................	267
Register 8:	DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 .............................	268
Register 9:	DMA Channel Software Request (DMASWREQ), offset 0x014 .........................................	269
Register 10:	DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 ....................................	270
Register 11:	DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C .................................	271
Register 12:	DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 ..............................	272
Register 13:	DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ...........................	273
Register 14:	DMA Channel Enable Set (DMAENASET), offset 0x028 ...................................................	274
Register 15:	DMA Channel Enable Clear (DMAENACLR), offset 0x02C ...............................................	275
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Stellaris® LM3S1R21 Microcontroller

Register 16:	DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 ....................................	276
Register 17:	DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 .................................	277
Register 18:	DMA Channel Priority Set (DMAPRIOSET), offset 0x038 .................................................	278
Register 19:	DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C ..............................................	279
Register 20:	DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................	280
Register 21:	DMA Channel Alternate Select (DMACHALT), offset 0x500 ..............................................	281
Register 22:	DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 .........................................	282
Register 23:	DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 .........................................	283
Register 24:	DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 .........................................	284
Register 25:	DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................	285
Register 26:	DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 .........................................	286
Register 27:	DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ...........................................	287
Register 28:	DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ...........................................	288
Register 29:	DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ...........................................	289
Register 30:	DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ...........................................	290
General-Purpose Input/Outputs (GPIOs) ...................................................................................		291
Register 1:	GPIO Data (GPIODATA), offset 0x000 ............................................................................	305
Register 2:	GPIO Direction (GPIODIR), offset 0x400 .........................................................................	306
Register 3:	GPIO Interrupt Sense (GPIOIS), offset 0x404 ..................................................................	307
Register 4:	GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................	308
Register 5:	GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................	309
Register 6:	GPIO Interrupt Mask (GPIOIM), offset 0x410 ...................................................................	310
Register 7:	GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................	311
Register 8:	GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ...................................................	312
Register 9:	GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................	314
Register 10:	GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................	315
Register 11:	GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................	317
Register 12:	GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................	318
Register 13:	GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................	319
Register 14:	GPIO Open Drain Select (GPIOODR), offset 0x50C .........................................................	320
Register 15:	GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................	321
Register 16:	GPIO Pull-Down Select (GPIOPDR), offset 0x514 ...........................................................	323
Register 17:	GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................	325
Register 18:	GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................	326
Register 19:	GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................	328
Register 20:	GPIO Commit (GPIOCR), offset 0x524 ............................................................................	329
Register 21:	GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ...................................................	331
Register 22:	GPIO Port Control (GPIOPCTL), offset 0x52C .................................................................	333
Register 23:	GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 .......................................	335
Register 24:	GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 .......................................	336
Register 25:	GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 .......................................	337
Register 26:	GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ......................................	338
Register 27:	GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 .......................................	339
Register 28:	GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 .......................................	340
Register 29:	GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 .......................................	341
Register 30:	GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ......................................	342
Register 31:	GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 ..........................................	343
Register 32:	GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 ..........................................	344
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Table of Contents

Register 33:	GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 ..........................................	345
Register 34:	GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC .........................................	346

External Peripheral Interface (EPI) .............................................................................................		347
Register 1:	EPI Configuration (EPICFG), offset 0x000 .......................................................................	377
Register 2:	EPI Main Baud Rate (EPIBAUD), offset 0x004 .................................................................	379
Register 3:	EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 ..............................................	381
Register 4:	EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 ...............................................	383
Register 5:	EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 ...........................................	387
Register 6:	EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 ........................................	391
Register 7:	EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 ..........................................	395
Register 8:	EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 .......................................	397
Register 9:	EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014 ...................................	399
Register 10:	EPI Address Map (EPIADDRMAP), offset 0x01C .............................................................	400
Register 11:	EPI Read Size 0 (EPIRSIZE0), offset 0x020 ....................................................................	402
Register 12:	EPI Read Size 1 (EPIRSIZE1), offset 0x030 ....................................................................	402
Register 13:	EPI Read Address 0 (EPIRADDR0), offset 0x024 ............................................................	403
Register 14:	EPI Read Address 1 (EPIRADDR1), offset 0x034 ............................................................	403
Register 15:	EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 .............................................	404
Register 16:	EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 .............................................	404
Register 17:	EPI Status (EPISTAT), offset 0x060 ................................................................................	406
Register 18:	EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ......................................................	408
Register 19:	EPI Read FIFO (EPIREADFIFO), offset 0x070 ................................................................	409
Register 20:	EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 ....................................................	409
Register 21:	EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 ....................................................	409
Register 22:	EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ...................................................	409
Register 23:	EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 ....................................................	409
Register 24:	EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 ....................................................	409
Register 25:	EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 ....................................................	409
Register 26:	EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ...................................................	409
Register 27:	EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................	410
Register 28:	EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ......................................................	412
Register 29:	EPI Interrupt Mask (EPIIM), offset 0x210 .........................................................................	413
Register 30:	EPI Raw Interrupt Status (EPIRIS), offset 0x214 ..............................................................	414
Register 31:	EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................	416
Register 32:	EPI Error Interrupt Status and Clear (EPIEISC), offset 0x21C ...........................................	417

General-Purpose Timers .............................................................................................................		419
Register 1:	GPTM Configuration (GPTMCFG), offset 0x000 ..............................................................	436
Register 2:	GPTM Timer A Mode (GPTMTAMR), offset 0x004 ...........................................................	437
Register 3:	GPTM Timer B Mode (GPTMTBMR), offset 0x008 ...........................................................	439
Register 4:	GPTM Control (GPTMCTL), offset 0x00C ........................................................................	441
Register 5:	GPTM Interrupt Mask (GPTMIMR), offset 0x018 ..............................................................	444
Register 6:	GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .....................................................	446
Register 7:	GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................	449
Register 8:	GPTM Interrupt Clear (GPTMICR), offset 0x024 ..............................................................	452
Register 9:	GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................	454
Register 10:	GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................	455
Register 11:	GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 ..................................................	456
Register 12:	GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 .................................................	457
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Register 13:	GPTM Timer A Prescale (GPTMTAPR), offset 0x038 .......................................................	458
Register 14:	GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ......................................................	459
Register 15:	GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ...........................................	460
Register 16:	GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ...........................................	461
Register 17:	GPTM Timer A (GPTMTAR), offset 0x048 .......................................................................	462
Register 18:	GPTM Timer B (GPTMTBR), offset 0x04C .......................................................................	463
Register 19:	GPTM Timer A Value (GPTMTAV), offset 0x050 ...............................................................	464
Register 20:	GPTM Timer B Value (GPTMTBV), offset 0x054 ..............................................................	465
Watchdog Timers .........................................................................................................................		466
Register 1:	Watchdog Load (WDTLOAD), offset 0x000 ......................................................................	470
Register 2:	Watchdog Value (WDTVALUE), offset 0x004 ...................................................................	471
Register 3:	Watchdog Control (WDTCTL), offset 0x008 .....................................................................	472
Register 4:	Watchdog Interrupt Clear (WDTICR), offset 0x00C ..........................................................	474
Register 5:	Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ..................................................	475
Register 6:	Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 .............................................	476
Register 7:	Watchdog Test (WDTTEST), offset 0x418 .......................................................................	477
Register 8:	Watchdog Lock (WDTLOCK), offset 0xC00 .....................................................................	478
Register 9:	Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 .................................	479
Register 10:	Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 .................................	480
Register 11:	Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 .................................	481
Register 12:	Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................	482
Register 13:	Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 .................................	483
Register 14:	Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 .................................	484
Register 15:	Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 .................................	485
Register 16:	Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................	486
Register 17:	Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 ....................................	487
Register 18:	Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 ....................................	488
Register 19:	Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 ....................................	489
Register 20:	Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ..................................	490
Analog-to-Digital Converter (ADC) .............................................................................................		491
Register 1:	ADC Active Sample Sequencer (ADCACTSS), offset 0x000 .............................................	510
Register 2:	ADC Raw Interrupt Status (ADCRIS), offset 0x004 ...........................................................	511
Register 3:	ADC Interrupt Mask (ADCIM), offset 0x008 .....................................................................	513
Register 4:	ADC Interrupt Status and Clear (ADCISC), offset 0x00C ..................................................	515
Register 5:	ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................	518
Register 6:	ADC Event Multiplexer Select (ADCEMUX), offset 0x014 .................................................	520
Register 7:	ADC Underflow Status (ADCUSTAT), offset 0x018 ...........................................................	523
Register 8:	ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 .............................................	524
Register 9:	ADC Sample Phase Control (ADCSPC), offset 0x024 ......................................................	526
Register 10:	ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 .................................	527
Register 11:	ADC Sample Averaging Control (ADCSAC), offset 0x030 .................................................	529
Register 12:	ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 .................	530
Register 13:	ADC Control (ADCCTL), offset 0x038 .............................................................................	532
Register 14:	ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ...............	533
Register 15:	ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................	535
Register 16:	ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................	538
Register 17:	ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................	538
Register 18:	ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................	538
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Register 19:	ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ...............................	538
Register 20:	ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C .............................	539
Register 21:	ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C .............................	539
Register 22:	ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................	539
Register 23:	ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................	539
Register 24:	ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ......................................	541
Register 25:	ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 ..............	543
Register 26:	ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ...............	545
Register 27:	ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ...............	545
Register 28:	ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................	546
Register 29:	ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................	546
Register 30:	ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ......................................	548
Register 31:	ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 .....................................	548
Register 32:	ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 ..............	549
Register 33:	ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 ..............	549
Register 34:	ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ...............	551
Register 35:	ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................	552
Register 36:	ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 .....................................	553
Register 37:	ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 ..............	554
Register 38:	ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 .....................	555
Register 39:	ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 .......................................	560
Register 40:	ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 .......................................	560
Register 41:	ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 .......................................	560
Register 42:	ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ......................................	560
Register 43:	ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 .......................................	560
Register 44:	ADC Digital Comparator Control 5 (ADCDCCTL5), offset 0xE14 .......................................	560
Register 45:	ADC Digital Comparator Control 6 (ADCDCCTL6), offset 0xE18 .......................................	560
Register 46:	ADC Digital Comparator Control 7 (ADCDCCTL7), offset 0xE1C ......................................	560
Register 47:	ADC Digital Comparator Range 0 (ADCDCCMP0), offset 0xE40 .......................................	564
Register 48:	ADC Digital Comparator Range 1 (ADCDCCMP1), offset 0xE44 .......................................	564
Register 49:	ADC Digital Comparator Range 2 (ADCDCCMP2), offset 0xE48 .......................................	564
Register 50:	ADC Digital Comparator Range 3 (ADCDCCMP3), offset 0xE4C ......................................	564
Register 51:	ADC Digital Comparator Range 4 (ADCDCCMP4), offset 0xE50 .......................................	564
Register 52:	ADC Digital Comparator Range 5 (ADCDCCMP5), offset 0xE54 .......................................	564
Register 53:	ADC Digital Comparator Range 6 (ADCDCCMP6), offset 0xE58 .......................................	564
Register 54:	ADC Digital Comparator Range 7 (ADCDCCMP7), offset 0xE5C ......................................	564
Universal Asynchronous Receivers/Transmitters (UARTs) .....................................................		565
Register 1:	UART Data (UARTDR), offset 0x000 ...............................................................................	579
Register 2:	UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ...........................	581
Register 3:	UART Flag (UARTFR), offset 0x018 ................................................................................	584
Register 4:	UART IrDA Low-Power Register (UARTILPR), offset 0x020 .............................................	587
Register 5:	UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................	588
Register 6:	UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 .......................................	589
Register 7:	UART Line Control (UARTLCRH), offset 0x02C ...............................................................	590
Register 8:	UART Control (UARTCTL), offset 0x030 .........................................................................	592
Register 9:	UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ...........................................	596
Register 10:	UART Interrupt Mask (UARTIM), offset 0x038 .................................................................	598
Register 11:	UART Raw Interrupt Status (UARTRIS), offset 0x03C ......................................................	602
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Register 12:	UART Masked Interrupt Status (UARTMIS), offset 0x040 .................................................	606
Register 13:	UART Interrupt Clear (UARTICR), offset 0x044 ...............................................................	609
Register 14:	UART DMA Control (UARTDMACTL), offset 0x048 ..........................................................	611
Register 15:	UART LIN Control (UARTLCTL), offset 0x090 .................................................................	612
Register 16:	UART LIN Snap Shot (UARTLSS), offset 0x094 ...............................................................	613
Register 17:	UART LIN Timer (UARTLTIM), offset 0x098 .....................................................................	614
Register 18:	UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 .....................................	615
Register 19:	UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 .....................................	616
Register 20:	UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 .....................................	617
Register 21:	UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC .....................................	618
Register 22:	UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ......................................	619
Register 23:	UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ......................................	620
Register 24:	UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ......................................	621
Register 25:	UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC .....................................	622
Register 26:	UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................	623
Register 27:	UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................	624
Register 28:	UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................	625
Register 29:	UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................	626
Synchronous Serial Interface (SSI) ............................................................................................		627
Register 1:	SSI Control 0 (SSICR0), offset 0x000 ..............................................................................	642
Register 2:	SSI Control 1 (SSICR1), offset 0x004 ..............................................................................	644
Register 3:	SSI Data (SSIDR), offset 0x008 ......................................................................................	646
Register 4:	SSI Status (SSISR), offset 0x00C ...................................................................................	647
Register 5:	SSI Clock Prescale (SSICPSR), offset 0x010 ..................................................................	649
Register 6:	SSI Interrupt Mask (SSIIM), offset 0x014 .........................................................................	650
Register 7:	SSI Raw Interrupt Status (SSIRIS), offset 0x018 ..............................................................	651
Register 8:	SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................	653
Register 9:	SSI Interrupt Clear (SSIICR), offset 0x020 .......................................................................	655
Register 10:	SSI DMA Control (SSIDMACTL), offset 0x024 .................................................................	656
Register 11:	SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 .............................................	657
Register 12:	SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 .............................................	658
Register 13:	SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 .............................................	659
Register 14:	SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................	660
Register 15:	SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 .............................................	661
Register 16:	SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 .............................................	662
Register 17:	SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 .............................................	663
Register 18:	SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................	664
Register 19:	SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ...............................................	665
Register 20:	SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ...............................................	666
Register 21:	SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ...............................................	667
Register 22:	SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ...............................................	668
Inter-Integrated Circuit (I2C) Interface ........................................................................................		669
Register 1:	I2C Master Slave Address (I2CMSA), offset 0x000 ...........................................................	685
Register 2:	I2C Master Control/Status (I2CMCS), offset 0x004 ...........................................................	686
Register 3:	I2C Master Data (I2CMDR), offset 0x008 .........................................................................	691
Register 4:	I2C Master Timer Period (I2CMTPR), offset 0x00C ...........................................................	692
Register 5:	I2C Master Interrupt Mask (I2CMIMR), offset 0x010 .........................................................	693
Register 6:	I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 .................................................	694
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Register 7:	I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ...........................................	695
Register 8:	I2C Master Interrupt Clear (I2CMICR), offset 0x01C .........................................................	696
Register 9:	I2C Master Configuration (I2CMCR), offset 0x020 ............................................................	697
Register 10:	I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................	698
Register 11:	I2C Slave Control/Status (I2CSCSR), offset 0x004 ...........................................................	699
Register 12:	I2C Slave Data (I2CSDR), offset 0x008 ...........................................................................	701
Register 13:	I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ...........................................................	702
Register 14:	I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ...................................................	703
Register 15:	I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 ..............................................	704
Register 16:	I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................	705
Analog Comparators ...................................................................................................................		706
Register 1:	Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ..................................	711
Register 2:	Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 .......................................	712
Register 3:	Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 .........................................	713
Register 4:	Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 .......................	714
Register 5:	Analog Comparator Status 0 (ACSTAT0), offset 0x020 .....................................................	715
Register 6:	Analog Comparator Status 1 (ACSTAT1), offset 0x040 .....................................................	715
Register 7:	Analog Comparator Control 0 (ACCTL0), offset 0x024 .....................................................	716
Register 8:	Analog Comparator Control 1 (ACCTL1), offset 0x044 .....................................................	716

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Revision History

The revision history table notes changes made between the indicated revisions of the LM3S1R21 data sheet.

Table 1. Revision History

Date	Revision	Description
May 2009	5285	Started tracking revision history.
June 2009	5779	■ In System Control chapter, clarified power-on reset and external reset pin descriptions in "Reset

Sources" section.

■ Added missing comparator output pin bits to DC3 register; reset value changed as well. ■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.

■ Addedexplanationofresetvalueto FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG,and USER_REG0

registers.

■ In Request Type Support table in DMA chapter, corrected general-purpose timer row. ■ In General-Purpose Timers chapter, clarified DMA operation.

■ Added table "Preliminary Current Consumption" to Characteristics chapter.

■ Corrected Nom and Max values in "Hibernation Detailed Current Specifications" table. ■ Corrected Nom and Max values in EPI Characteristics table.

■ Added "CSn to output invalid" parameter to EPI table "EPI Host-Bus 8 and Host-Bus 16 Interface Characteristics" and figure "Host-Bus 8/16 Mode Read Timing".

■ Corrected INL, DNL, OFF and GAIN values in ADC Characteristics table. ■ Updated ROM DriverLib appendix with RevC0 functions.

■ Updated part ordering numbers.

■ Additional minor data sheet clarifications and corrections.

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Revision History

Table 1. Revision History (continued)

Date	Revision	Description
July 2009	5930	■ Added"Non-BlockingReadCycle","NormalReadCycle",and"WriteCycle"sectionstoEPIchapter.
		■ Corrected values for MAXADC0SPD and MAXADC1SPD bits in DC1, RCGC0, SCGC0, and DCGC0
		registers.
		■ Corrected figure "TI Synchronous Serial Frame Format (Single Transfer)".
		■ Changed HIB pin from type TTL to type OD.
		■ Made a number of corrections to the Electrical Characteristics chapter:
		–	DeletedVBAT andVREFA parametersfromandaddedfootnotestoRecommendedDCOperating
			Conditions table.
		– Modified Hibernation Module DC Characteristics table.
		– Deleted Nominal and Maximum Current Specifications section.
		– Modified EPI SDRAM Characteristics table:
			• Changed tEPIR to tSDRAMR and deleted values for 2-mA and 4-mA drive.
			• Changed tEPIF to tSDRAMF and deleted values for 2-mA and 4-mA drive.
		– Changed values for tCOV, tCOI, and tCOT parameters in EPI SDRAM Interface Characteristics
			table.
		–	DeletedSDRAMReadCommandTiming,SDRAMWriteCommandTiming,SDRAMWriteBurst
			Timing, SDRAM Precharge Command Timing and SDRAM CAS Latency Timing figures and
			replaced with SDRAM Read Timing and SDRAM Write Timing figures.
		– Modified Host-Bus 8/16 Mode Write Timing figure.
		– Modified General-Purpose Mode Read and Write Timing figure.
		–	ModifiedvaluesfortDV andtDI parameters,anddeletedtOD parameterfromEPIGeneral-Purpose

Interface Characteristics figure.

– Major changes to ADC Characteristics tables, including adding additonal tables and diagram. ■ Corrected ordering part numbers.

■ Additional minor data sheet clarifications and corrections.

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Table 1. Revision History (continued)

Date	Revision	Description
October 2009	6458	■ Released new 1000, 3000, 5000 and 9000 series Stellaris® devices.
		■ The IDCODE value was corrected to be 0x4BA0.0477.
		■ Clarified that the NMISET bit in the ICSR register in the NVIC is also a source for NMI.
		■ Clarified the use of the LDO.
		■ To clarify clock operation, reorganized clocking section, changed the USEFRACT bit to the DIV400
		bit and the FRACT bit to the SYSDIV2LSB bit in the RCC2 register, added tables, and rewrote
		descriptions.
		■ Corrected bit description of the DSDIVORIDE field in the DSLPCLKCFG register.
		■ RemovedtheDSFLASHCFGregisteratSystemControloffset0x14Casitdoesnotfunctioncorrectly.
		■ Removed the MAXADC1SPD and MAXADC0SPD fields from the DCGC0 as they have no function in
		deep-sleep mode.
		■ Corrected address offsets for the Flash Write Buffer (FWBn) registers.
		■ Added Flash Control (FCTL) register at Internal memory offset 0x0F8 to help control frequent
		power cycling when hibernation is not used.
		■ ChangedthenameoftheEPIchannelsforclarification:EPI0_TXbecameEPI0_WFIFOandEPI0_RX
		became EPI0_NBRFIFO. This change was also made in the DC7 bit descriptions.
		■ Removed the DMACHIS register at DMA module offset 0x504 as it does not function correctly.
		■ Corrected alternate channel assignments for the µDMA controller.
		■ Major improvements to the EPI chapter.
		■ EPISDRAMCFG2 register was deleted as its function is not needed.
		■ Clarified PWM source for ADC triggering
		■ Changed SSI set up and hold times to be expressed in system clocks, not ns.
		■ Updated Electrical Characteristics chapter with latest data. Changes were made to Hibernation,
		ADC and EPI content.
		■ Additional minor data sheet clarifications and corrections.

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25

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Revision History

Table 1. Revision History (continued)

Date	Revision	Description
February 2010	6790	■	Added 108-ball BGA package.
		■ In "System Control" chapter:
			– Clarified functional description for external reset and brown-out reset.
			– Clarified Debug Access Port operation after Sleep modes.
			– Corrected the reset value of the Run-Mode Clock Configuration 2 (RCC2) register.
		■	In"InternalMemory"chapter,clarifiedwordingonFlashmemoryaccesserrorsandaddedasection
			on interrupts to the Flash memory description.
		■ In "External Peripheral Interface" chapter:
			– Added clarification about byte selects and dual chip selects.
			– Added timing diagrams for continuous-read mode (formerly SRAM mode).
			– Corrected reset values of EPI Write FIFO Count (EPIWFIFOCNT) and EPI Raw Interrupt
			Status (EPIRIS) registers.
		■ Added clarification about timer operating modes and added register descriptions for the GPTM
			Timer n Prescale Match (GPTMTnPMR) registers.
		■ Clarified register descriptions for GPTM Timer A Value (GPTMTAV) and GPTM Timer B Value
			(GPTMTBV) registers.
		■ Corrected the reset value of the ADCSampleSequenceResultFIFOn(ADCSSFIFOn) registers.
		■ Added ADC Sample Phase Control (ADCSPC) register at offset 0x24.
		■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
			field width to 7 bits.
		■	Added Session Disconnect (DISCON) bit to the USB General Interrupt Status (USBIS) and
			USB Interrupt Enable (USBIE) registers.

■ Made these changes to the Operating Characteristics chapter:

– Added storage temperature ratings to "Temperature Characteristics" table

– Added "ESD Absolute Maximum Ratings" table

■ Made these changes to the Electrical Characteristics chapter:

– In "Flash Memory Characteristics" table, corrected Mass erase time

– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)

– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time

– Added table entry for VDD3ON power consumption to Table 22-7 on page 770. ■ Added additional DriverLib functions to appendix.

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About This Document

This data sheet provides reference information for the LM3S1R21 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core.

Audience

This manual is intended for system software developers, hardware designers, and application developers.

About This Manual

This document is organized into sections that correspond to each major feature.

Related Documents

The following documents are referenced by the data sheet, and available on the documentation CD or from the Stellaris® web site at www.ti.com/stellaris:

■ARM® Cortex™-M3 Technical Reference Manual

■ARM® CoreSight Technical Reference Manual

■ARM® v7-M Architecture Application Level Reference Manual

■Stellaris® Peripheral Driver Library User's Guide

■Stellaris® ROM User’s Guide

The following related documents are also referenced:

■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture

This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers.

Documentation Conventions

This document uses the conventions shown in Table 2 on page 27.

Table 2. Documentation Conventions

Notation Meaning

General Register Notation

REGISTER	APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
	Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
	thanoneregister. Forexample, SRCRn representsany(orall)ofthethreeSoftwareResetControl
	registers: SRCR0, SRCR1 , and SRCR2.
bit	A single bit in a register.
bit field	Two or more consecutive and related bits.
offset 0xnnn	Ahexadecimalincrementtoaregister'saddress,relativetothatmodule'sbaseaddressasspecified
	in “Memory Map” on page 63.

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About This Document

Table 2. Documentation Conventions (continued)

Notation		Meaning
Register N		Registers are numbered consecutively throughout the document to aid in referencing them. The
		register number has no meaning to software.
reserved		Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
		0; however, user software should not rely on the value of a reserved bit. To provide software
		compatibility with future products, the value of a reserved bit should be preserved across a
		read-modify-write operation.
yy:xx		The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
		that register.
Register Bit/Field		This value in the register bit diagram indicates whether software running on the controller can
Types		change the value of the bit field.
RC		Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO		Software can read this field. Always write the chip reset value.
R/W		Software can read or write this field.
R/W1C		Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
		register. Awriteofa1clearsthevalueofthebitintheregister;theremainingbitsremainunchanged.
		This register type is primarily used for clearing interrupt status bits where the read operation
		providestheinterruptstatusandthewriteofthereadvalueclearsonlytheinterruptsbeingreported
		at the time the register was read.
R/W1S		Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
		value in the register.
W1C		Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
		A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
		read of the register returns no meaningful data.
		This register is typically used to clear the corresponding bit in an interrupt register.
WO		Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field		This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0		Bit cleared to 0 on chip reset.
1		Bit set to 1 on chip reset.
-		Nondeterministic.
Pin/Signal Notation
[ ]		Pin alternate function; a pin defaults to the signal without the brackets.
pin		Refers to the physical connection on the package.
signal		Refers to the electrical signal encoding of a pin.
assert a signal		Change the value of the signal from the logically False state to the logically True state. For active
		Highsignals,theassertedsignalvalueis1(High);foractiveLowsignals,theassertedsignalvalue
		is0(Low). Theactivepolarity(HighorLow)isdefinedbythesignalname(see SIGNAL and
							SIGNAL
		below).
deassert a signal		Change the value of the signal from the logically True state to the logically False state.
		Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
SIGNAL
		it is active Low. To assert		is to drive it Low; to deassert		is to drive it High.
			SIGNAL		SIGNAL
SIGNAL		Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
		assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.

Numbers

XAn uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on.

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Stellaris® LM3S1R21 Microcontroller

Table 2. Documentation Conventions (continued)

Notation	Meaning
0x	Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
	All other numbers within register tables are assumed to be binary. Within conceptual information,
	binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
	without a prefix or suffix.

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Architectural Overview

1Architectural Overview

Texas Instruments is the industry leader in bringing 32-bit capabilities and the full benefits of ARM® Cortex-M3™-basedmicrocontrollerstothebroadestreachofthemicrocontrollermarket. Forcurrent usersof8- and16-bitMCUs,Stellaris® withCortex-M3offersadirectpathtothestrongestecosystem of development tools, software and knowledge in the industry. Designers who migrate to Stellaris® benefit from great tools, small code footprint and outstanding performance. Even more important, designers can enter the ARM ecosystem with full confidence in a compatible roadmap from $1 to 1GHz. Forusersofcurrent32-bitMCUs,theStellaris® familyofferstheindustry’sfirstimplementation of Cortex-M3 and the Thumb-2 instruction set. With blazingly-fast responsiveness, Thumb-2 technology combines both 16-bit and 32-bit instructions to deliver the best balance of code density and performance. Thumb-2 uses 26 percent less memory than pure 32-bit code to reduce system cost while delivering 25 percent better performance. The Texas Instruments Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.

The LM3S1R21 microcontroller has the following features:

■ARM® Cortex™-M3 Processor Core

–80-MHz operation; 100 DMIPS performance

–ARM Cortex SysTick Timer

–Nested Vectored Interrupt Controller (NVIC)

■On-Chip Memory

–256 KB single-cycle Flash memory up to 50 MHz; a prefetch buffer improves performance above 50 MHz

–48 KB single-cycle SRAM

–Internal ROM loaded with StellarisWare® software:

•Stellaris® Peripheral Driver Library

•Stellaris® Boot Loader

■External Peripheral Interface (EPI)

–8/16/32-bit dedicated parallel bus for external peripherals

–Supports SDRAM, SRAM/Flash memory, FPGAs, CPLDs

■Advanced Serial Integration

–Three UARTs with IrDA and ISO 7816 support (one UART with full modem controls)

–Two I2C modules

–Two Synchronous Serial Interface modules (SSI)

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