Texas instruments STELLARIS LM3S1439 DATA SHEET

TEXAS INSTRUMENTS-PRODUCTION DATA

Stellaris® LM3S1439 Microcontroller

DATA SHEET

DS-LM3S1439-7393	Copyright © 2007-2010 Texas Instruments
	Incorporated

Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Pleasebe awarethat an importantnoticeconcerningavailability, standardwarranty, and use in criticalapplicationsof Texas Instrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated

108 Wild Basin, Suite 350 Austin, TX 78746

http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

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		Stellaris® LM3S1439 Microcontroller
Table of Contents
Revision History .............................................................................................................................		20
About This Document ....................................................................................................................		24
Audience ..............................................................................................................................................		24
About This Manual ................................................................................................................................		24
Related Documents ...............................................................................................................................		24
Documentation Conventions ..................................................................................................................		25
1	Architectural Overview ..........................................................................................	27
1.1	Product Features ..........................................................................................................	27
1.2	Target Applications ........................................................................................................	35
1.3	High-Level Block Diagram .............................................................................................	36
1.4	Functional Overview ......................................................................................................	38
1.4.1	ARM Cortex™-M3 .........................................................................................................	38
1.4.2	Motor Control Peripherals ..............................................................................................	39
1.4.3	Analog Peripherals ........................................................................................................	39
1.4.4	Serial Communications Peripherals ................................................................................	40
1.4.5	System Peripherals .......................................................................................................	41
1.4.6	Memory Peripherals ......................................................................................................	42
1.4.7	Additional Features .......................................................................................................	43
1.4.8	Hardware Details ..........................................................................................................	43
2	ARM Cortex-M3 Processor Core ...........................................................................	45
2.1	Block Diagram ..............................................................................................................	46
2.2	Functional Description ...................................................................................................	46
2.2.1	Serial Wire and JTAG Debug .........................................................................................	46
2.2.2	Embedded Trace Macrocell (ETM) .................................................................................	47
2.2.3	Trace Port Interface Unit (TPIU) .....................................................................................	47
2.2.4	ROM Table ...................................................................................................................	47
2.2.5	Memory Protection Unit (MPU) .......................................................................................	47
2.2.6	Nested Vectored Interrupt Controller (NVIC) ....................................................................	47
3	Memory Map ...........................................................................................................	51
4	Interrupts .................................................................................................................	53
5	JTAG Interface ........................................................................................................	56
5.1	Block Diagram ..............................................................................................................	57
5.2	Functional Description ...................................................................................................	57
5.2.1	JTAG Interface Pins ......................................................................................................	57
5.2.2	JTAG TAP Controller .....................................................................................................	59
5.2.3	Shift Registers ..............................................................................................................	60
5.2.4	Operational Considerations ............................................................................................	60
5.3	Initialization and Configuration .......................................................................................	63
5.4	Register Descriptions ....................................................................................................	63
5.4.1	Instruction Register (IR) .................................................................................................	63
5.4.2	Data Registers ..............................................................................................................	65
6	System Control .......................................................................................................	68
6.1	Functional Description ...................................................................................................	68
6.1.1	Device Identification ......................................................................................................	68
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6.1.2	Reset Control ................................................................................................................	68
6.1.3	Power Control ...............................................................................................................	71
6.1.4	Clock Control ................................................................................................................	72
6.1.5	System Control .............................................................................................................	78
6.2	Initialization and Configuration .......................................................................................	79
6.3	Register Map ................................................................................................................	80
6.4	Register Descriptions ....................................................................................................	81

7	Hibernation Module ..............................................................................................	130
7.1	Block Diagram ............................................................................................................	131
7.2	Functional Description .................................................................................................	131
7.2.1	Register Access Timing ...............................................................................................	131
7.2.2	Clock Source ..............................................................................................................	132
7.2.3	Battery Management ...................................................................................................	133
7.2.4	Real-Time Clock ..........................................................................................................	133
7.2.5	Non-Volatile Memory ...................................................................................................	134
7.2.6	Power Control .............................................................................................................	134
7.2.7	Initiating Hibernate ......................................................................................................	134
7.2.8	Interrupts and Status ...................................................................................................	135
7.3	Initialization and Configuration .....................................................................................	135
7.3.1	Initialization .................................................................................................................	135
7.3.2	RTC Match Functionality (No Hibernation) ....................................................................	135
7.3.3	RTC Match/Wake-Up from Hibernation .........................................................................	136
7.3.4	External Wake-Up from Hibernation ..............................................................................	136
7.3.5	RTC/External Wake-Up from Hibernation ......................................................................	136
7.4	Register Map ..............................................................................................................	136
7.5	Register Descriptions ..................................................................................................	137

8	Internal Memory ...................................................................................................	150
8.1	Block Diagram ............................................................................................................	150
8.2	Functional Description .................................................................................................	150
8.2.1	SRAM Memory ............................................................................................................	150
8.2.2	Flash Memory .............................................................................................................	151
8.3	Flash Memory Initialization and Configuration ...............................................................	152
8.3.1	Flash Programming .....................................................................................................	152
8.3.2	Nonvolatile Register Programming ...............................................................................	153
8.4	Register Map ..............................................................................................................	154
8.5	Flash Register Descriptions (Flash Control Offset) .........................................................	154
8.6	Flash Register Descriptions (System Control Offset) ......................................................	162

9	General-Purpose Input/Outputs (GPIOs)	........................................................... 175
9.1	Functional Description .................................................................................................	175
9.1.1	Data Control ...............................................................................................................	176
9.1.2	Interrupt Control ..........................................................................................................	177
9.1.3	Mode Control ..............................................................................................................	178
9.1.4	Commit Control ...........................................................................................................	178
9.1.5	Pad Control .................................................................................................................	178
9.1.6	Identification ...............................................................................................................	179
9.2	Initialization and Configuration .....................................................................................	179
9.3	Register Map ..............................................................................................................	180
9.4	Register Descriptions ..................................................................................................	182
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10	General-Purpose Timers ......................................................................................	217
10.1	Block Diagram ............................................................................................................	218
10.2	Functional Description .................................................................................................	218
10.2.1	GPTM Reset Conditions ..............................................................................................	219
10.2.2	32-Bit Timer Operating Modes ......................................................................................	219
10.2.3	16-Bit Timer Operating Modes ......................................................................................	220
10.3	Initialization and Configuration .....................................................................................	224
10.3.1	32-Bit One-Shot/Periodic Timer Mode ...........................................................................	224
10.3.2	32-Bit Real-Time Clock (RTC) Mode .............................................................................	225
10.3.3	16-Bit One-Shot/Periodic Timer Mode ...........................................................................	225
10.3.4	16-Bit Input Edge Count Mode .....................................................................................	226
10.3.5	16-Bit Input Edge Timing Mode ....................................................................................	226
10.3.6	16-Bit PWM Mode .......................................................................................................	227
10.4	Register Map ..............................................................................................................	227
10.5	Register Descriptions ..................................................................................................	228
11	Watchdog Timer ...................................................................................................	253
11.1	Block Diagram ............................................................................................................	254
11.2	Functional Description .................................................................................................	254
11.3	Initialization and Configuration .....................................................................................	255
11.4	Register Map ..............................................................................................................	255
11.5	Register Descriptions ..................................................................................................	256
12	Analog-to-Digital Converter (ADC) .....................................................................	277
12.1	Block Diagram ............................................................................................................	277
12.2	Functional Description .................................................................................................	278
12.2.1	Sample Sequencers ....................................................................................................	278
12.2.2	Module Control ............................................................................................................	279
12.2.3	Hardware Sample Averaging Circuit .............................................................................	280
12.2.4	Analog-to-Digital Converter ..........................................................................................	280
12.2.5	Differential Sampling ...................................................................................................	280
12.2.6	Test Modes .................................................................................................................	282
12.2.7	Internal Temperature Sensor ........................................................................................	283
12.3	Initialization and Configuration .....................................................................................	283
12.3.1	Module Initialization .....................................................................................................	283
12.3.2	Sample Sequencer Configuration .................................................................................	284
12.4	Register Map ..............................................................................................................	284
12.5	Register Descriptions ..................................................................................................	285
13	Universal Asynchronous Receivers/Transmitters (UARTs) .............................	314
13.1	Block Diagram ............................................................................................................	315
13.2	Functional Description .................................................................................................	315
13.2.1	Transmit/Receive Logic ...............................................................................................	315
13.2.2	Baud-Rate Generation .................................................................................................	316
13.2.3	Data Transmission ......................................................................................................	317
13.2.4	Serial IR (SIR) .............................................................................................................	317
13.2.5	FIFO Operation ...........................................................................................................	318
13.2.6	Interrupts ....................................................................................................................	318
13.2.7	Loopback Operation ....................................................................................................	319
13.2.8	IrDA SIR block ............................................................................................................	319
13.3	Initialization and Configuration .....................................................................................	319
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13.4	Register Map ..............................................................................................................	320
13.5	Register Descriptions ..................................................................................................	321

14	Synchronous Serial Interface (SSI) ....................................................................	355
14.1	Block Diagram ............................................................................................................	355
14.2	Functional Description .................................................................................................	356
14.2.1	Bit Rate Generation .....................................................................................................	356
14.2.2	FIFO Operation ...........................................................................................................	356
14.2.3	Interrupts ....................................................................................................................	356
14.2.4	Frame Formats ...........................................................................................................	357
14.3	Initialization and Configuration .....................................................................................	364
14.4	Register Map ..............................................................................................................	365
14.5	Register Descriptions ..................................................................................................	366
15	Inter-Integrated Circuit (I2C) Interface ................................................................	392
15.1	Block Diagram ............................................................................................................	393
15.2	Functional Description .................................................................................................	393
15.2.1	I2C Bus Functional Overview ........................................................................................	393
15.2.2	Available Speed Modes ...............................................................................................	395
15.2.3	Interrupts ....................................................................................................................	396
15.2.4	Loopback Operation ....................................................................................................	397
15.2.5	Command Sequence Flow Charts ................................................................................	397
15.3	Initialization and Configuration .....................................................................................	404
15.4	Register Map ..............................................................................................................	405
15.5	Register Descriptions (I2C Master) ...............................................................................	406
15.6	Register Descriptions (I2C Slave) .................................................................................	419
16	Analog Comparator ..............................................................................................	428
16.1	Block Diagram ............................................................................................................	428
16.2	Functional Description .................................................................................................	428
16.2.1	Internal Reference Programming ..................................................................................	429
16.3	Initialization and Configuration .....................................................................................	430
16.4	Register Map ..............................................................................................................	430
16.5	Register Descriptions ..................................................................................................	431
17	Pulse Width Modulator (PWM) ............................................................................	439
17.1	Block Diagram ............................................................................................................	440
17.2	Functional Description .................................................................................................	441
17.2.1	PWM Timer .................................................................................................................	441
17.2.2	PWM Comparators ......................................................................................................	441
17.2.3	PWM Signal Generator ................................................................................................	442
17.2.4	Dead-Band Generator .................................................................................................	443
17.2.5	Interrupt/ADC-Trigger Selector .....................................................................................	443
17.2.6	Synchronization Methods ............................................................................................	444
17.2.7	Fault Conditions ..........................................................................................................	444
17.2.8	Output Control Block ...................................................................................................	444
17.3	Initialization and Configuration .....................................................................................	444
17.4	Register Map ..............................................................................................................	445
17.5	Register Descriptions ..................................................................................................	447
18	Quadrature Encoder Interface (QEI) ...................................................................	477
18.1	Block Diagram ............................................................................................................	477
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18.2	Functional Description .................................................................................................	478
18.3	Initialization and Configuration .....................................................................................	480
18.4	Register Map ..............................................................................................................	481
18.5	Register Descriptions ..................................................................................................	481
19	Pin Diagram ..........................................................................................................	494
20	Signal Tables ........................................................................................................	496
20.1	100-Pin LQFP Package Pin Tables ...............................................................................	496
20.2	108-Pin BGA Package Pin Tables ................................................................................	508
20.3	Connections for Unused Signals ...................................................................................	521
21	Operating Characteristics ...................................................................................	523
22	Electrical Characteristics ....................................................................................	524
22.1	DC Characteristics ......................................................................................................	524
22.1.1	Maximum Ratings .......................................................................................................	524
22.1.2	Recommended DC Operating Conditions ......................................................................	524
22.1.3	On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................	525
22.1.4	GPIO Module Characteristics .......................................................................................	525
22.1.5	Power Specifications ...................................................................................................	525
22.1.6	Flash Memory Characteristics ......................................................................................	527
22.1.7	Hibernation .................................................................................................................	527
22.2	AC Characteristics .......................................................................................................	527
22.2.1	Load Conditions ..........................................................................................................	527
22.2.2	Clocks ........................................................................................................................	528
22.2.3	JTAG and Boundary Scan ............................................................................................	529
22.2.4	Reset .........................................................................................................................	531
22.2.5	Sleep Modes ...............................................................................................................	533
22.2.6	Hibernation Module .....................................................................................................	533
22.2.7	General-Purpose I/O (GPIO) ........................................................................................	534
22.2.8	Analog-to-Digital Converter ..........................................................................................	534
22.2.9	Synchronous Serial Interface (SSI) ...............................................................................	535
22.2.10	Inter-Integrated Circuit (I2C) Interface ...........................................................................	537
22.2.11	Analog Comparator .....................................................................................................	538
A	Serial Flash Loader ..............................................................................................	539
A.1	Serial Flash Loader .....................................................................................................	539
A.2	Interfaces ...................................................................................................................	539
A.2.1	UART .........................................................................................................................	539
A.2.2	SSI .............................................................................................................................	539
A.3	Packet Handling ..........................................................................................................	540
A.3.1	Packet Format ............................................................................................................	540
A.3.2	Sending Packets .........................................................................................................	540
A.3.3	Receiving Packets .......................................................................................................	540
A.4	Commands .................................................................................................................	541
A.4.1	COMMAND_PING (0X20) ............................................................................................	541
A.4.2	COMMAND_GET_STATUS (0x23) ...............................................................................	541
A.4.3	COMMAND_DOWNLOAD (0x21) .................................................................................	541
A.4.4	COMMAND_SEND_DATA (0x24) .................................................................................	542
A.4.5	COMMAND_RUN (0x22) .............................................................................................	542
A.4.6	COMMAND_RESET (0x25) .........................................................................................	542
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B	Register Quick Reference ...................................................................................	544
C	Ordering and Contact Information .....................................................................	562
C.1	Ordering Information ....................................................................................................	562
C.2	Part Markings ..............................................................................................................	562
C.3	Kits .............................................................................................................................	563
C.4	Support Information .....................................................................................................	563
D	Package Information ............................................................................................	564

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List of Figures
Figure 1-1.	Stellaris® LM3S1439 Microcontroller High-Level Block Diagram .............................	37
Figure 2-1.	CPU Block Diagram .............................................................................................	46
Figure 2-2.	TPIU Block Diagram ............................................................................................	47
Figure 5-1.	JTAG Module Block Diagram ................................................................................	57
Figure 5-2.	Test Access Port State Machine ...........................................................................	60
Figure 5-3.	IDCODE Register Format .....................................................................................	66
Figure 5-4.	BYPASS Register Format ....................................................................................	66
Figure 5-5.	Boundary Scan Register Format ...........................................................................	67
Figure 6-1.	Basic RST Configuration ......................................................................................	69
Figure 6-2.	External Circuitry to Extend Power-On Reset ........................................................	70
Figure 6-3.	Reset Circuit Controlled by Switch ........................................................................	70
Figure 6-4.	Power Architecture ..............................................................................................	72
Figure 6-5.	Main Clock Tree ..................................................................................................	75
Figure 7-1.	Hibernation Module Block Diagram .....................................................................	131
Figure 7-2.	Clock Source Using Crystal ................................................................................	132
Figure 7-3.	Clock Source Using Dedicated Oscillator .............................................................	133
Figure 8-1.	Flash Block Diagram ..........................................................................................	150
Figure 9-1.	GPIO Port Block Diagram ...................................................................................	176
Figure 9-2.	GPIODATA Write Example .................................................................................	177
Figure 9-3.	GPIODATA Read Example .................................................................................	177
Figure 10-1.	GPTM Module Block Diagram ............................................................................	218
Figure 10-2.	16-Bit Input Edge Count Mode Example ..............................................................	222
Figure 10-3.	16-Bit Input Edge Time Mode Example ...............................................................	223
Figure 10-4.	16-Bit PWM Mode Example ................................................................................	224
Figure 11-1.	WDT Module Block Diagram ..............................................................................	254
Figure 12-1.	ADC Module Block Diagram ...............................................................................	278
Figure 12-2.	Differential Sampling Range, VIN_ODD = 1.5 V ......................................................	281
Figure 12-3.	Differential Sampling Range, VIN_ODD = 0.75 V ....................................................	282
Figure 12-4.	Differential Sampling Range, VIN_ODD = 2.25 V ....................................................	282
Figure 12-5.	Internal Temperature Sensor Characteristic .........................................................	283
Figure 13-1.	UART Module Block Diagram .............................................................................	315
Figure 13-2.	UART Character Frame .....................................................................................	316
Figure 13-3.	IrDA Data Modulation .........................................................................................	318
Figure 14-1.	SSI Module Block Diagram .................................................................................	355
Figure 14-2.	TI Synchronous Serial Frame Format (Single Transfer) ........................................	358
Figure 14-3.	TI Synchronous Serial Frame Format (Continuous Transfer) ................................	358
Figure 14-4.	Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ..........................	359
Figure 14-5.	Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ..................	359
Figure 14-6.	Freescale SPI Frame Format with SPO=0 and SPH=1 .........................................	360
Figure 14-7.	Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ...............	361
Figure 14-8.	Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........	361
Figure 14-9.	Freescale SPI Frame Format with SPO=1 and SPH=1 .........................................	362
Figure 14-10.	MICROWIRE Frame Format (Single Frame) ........................................................	363
Figure 14-11.	MICROWIRE Frame Format (Continuous Transfer) .............................................	364
Figure 14-12.	MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............	364

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Figure 15-1.	I2C Block Diagram .............................................................................................	393
Figure 15-2.	I2C Bus Configuration ........................................................................................	393
Figure 15-3.	START and STOP Conditions .............................................................................	394
Figure 15-4.	Complete Data Transfer with a 7-Bit Address .......................................................	394
Figure 15-5.	R/S Bit in First Byte ............................................................................................	394
Figure 15-6.	Data Validity During Bit Transfer on the I2C Bus ...................................................	395
Figure 15-7.	Master Single SEND ..........................................................................................	398
Figure 15-8.	Master Single RECEIVE .....................................................................................	399
Figure 15-9.	Master Burst SEND ...........................................................................................	400
Figure 15-10.	Master Burst RECEIVE ......................................................................................	401
Figure 15-11.	Master Burst RECEIVE after Burst SEND ............................................................	402
Figure 15-12.	Master Burst SEND after Burst RECEIVE ............................................................	403
Figure 15-13.	Slave Command Sequence ................................................................................	404
Figure 16-1.	Analog Comparator Module Block Diagram .........................................................	428
Figure 16-2.	Structure of Comparator Unit ..............................................................................	429
Figure 16-3.	Comparator Internal Reference Structure ............................................................	429
Figure 17-1.	PWM Unit Diagram ............................................................................................	440
Figure 17-2.	PWM Module Block Diagram ..............................................................................	441
Figure 17-3.	PWM Count-Down Mode ....................................................................................	442
Figure 17-4.	PWM Count-Up/Down Mode ..............................................................................	442
Figure 17-5.	PWM Generation Example In Count-Up/Down Mode ...........................................	443
Figure 17-6.	PWM Dead-Band Generator ...............................................................................	443
Figure 18-1.	QEI Block Diagram ............................................................................................	478
Figure 18-2.	Quadrature Encoder and Velocity Predivider Operation ........................................	479
Figure 19-1.	100-Pin LQFP Package Pin Diagram ..................................................................	494
Figure 19-2.	108-Ball BGA Package Pin Diagram (Top View) ...................................................	495
Figure 22-1.	Load Conditions ................................................................................................	528
Figure 22-2.	JTAG Test Clock Input Timing .............................................................................	530
Figure 22-3.	JTAG Test Access Port (TAP) Timing ..................................................................	531
Figure 22-4.	JTAG TRST Timing ............................................................................................	531
Figure 22-5.	External Reset Timing (RST) ..............................................................................	532
Figure 22-6.	Power-On Reset Timing .....................................................................................	532
Figure 22-7.	Brown-Out Reset Timing ....................................................................................	532
Figure 22-8.	Software Reset Timing .......................................................................................	532
Figure 22-9.	Watchdog Reset Timing .....................................................................................	533
Figure 22-10.	Hibernation Module Timing .................................................................................	534
Figure 22-11.	ADC Input Equivalency Diagram .........................................................................	535
Figure 22-12.	SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
	Measurement ....................................................................................................	536
Figure 22-13.	SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer .................	536
Figure 22-14.	SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .....................................	537
Figure 22-15.	I2C Timing .........................................................................................................	538
Figure D-1.	100-Pin LQFP Package ......................................................................................	564
Figure D-2.	108-Ball BGA Package ......................................................................................	566

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List of Tables
Table 1.	Revision History ..................................................................................................	20
Table 2.	Documentation Conventions ................................................................................	25
Table 3-1.	Memory Map .......................................................................................................	51
Table 4-1.	Exception Types ..................................................................................................	53
Table 4-2.	Interrupts ............................................................................................................	54
Table 5-1.	JTAG Port Pins Reset State .................................................................................	58
Table 5-2.	JTAG Instruction Register Commands ...................................................................	63
Table 6-1.	Clock Source Options ..........................................................................................	73
Table 6-2.	Possible System Clock Frequencies Using the SYSDIV Field .................................	76
Table 6-3.	Examples of Possible System Clock Frequencies Using the SYSDIV2 Field ............	76
Table 6-4.	System Control Register Map ...............................................................................	80
Table 6-5.	RCC2 Fields that Override RCC fields ..................................................................	95
Table 7-1.	Hibernation Module Register Map .......................................................................	136
Table 8-1.	Flash Protection Policy Combinations .................................................................	151
Table 8-2.	User-Programmable Flash Memory Resident Registers .......................................	153
Table 8-3.	Flash Register Map ............................................................................................	154
Table 9-1.	GPIO Pad Configuration Examples .....................................................................	179
Table 9-2.	GPIO Interrupt Configuration Example ................................................................	179
Table 9-3.	GPIO Register Map ...........................................................................................	181
Table 10-1.	Available CCP Pins ............................................................................................	218
Table 10-2.	16-Bit Timer With Prescaler Configurations .........................................................	221
Table 10-3.	Timers Register Map ..........................................................................................	227
Table 11-1.	Watchdog Timer Register Map ............................................................................	255
Table 12-1.	Samples and FIFO Depth of Sequencers ............................................................	278
Table 12-2.	Differential Sampling Pairs .................................................................................	280
Table 12-3.	ADC Register Map .............................................................................................	284
Table 13-1.	UART Register Map ...........................................................................................	320
Table 14-1.	SSI Register Map ..............................................................................................	365
Table 15-1.	Examples of I2C Master Timer Period versus Speed Mode ...................................	396
Table 15-2.	Inter-Integrated Circuit (I2C) Interface Register Map .............................................	405
Table 15-3.	Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ....................................	410
Table 16-1.	Internal Reference Voltage and ACREFCTL Field Values .....................................	430
Table 16-2.	Analog Comparators Register Map .....................................................................	431
Table 17-1.	PWM Register Map ............................................................................................	445
Table 18-1.	QEI Register Map ..............................................................................................	481
Table 20-1.	Signals by Pin Number .......................................................................................	496
Table 20-2.	Signals by Signal Name .....................................................................................	500
Table 20-3.	Signals by Function, Except for GPIO .................................................................	504
Table 20-4.	GPIO Pins and Alternate Functions .....................................................................	507
Table 20-5.	Signals by Pin Number .......................................................................................	508
Table 20-6.	Signals by Signal Name .....................................................................................	513
Table 20-7.	Signals by Function, Except for GPIO .................................................................	517
Table 20-8.	GPIO Pins and Alternate Functions .....................................................................	519
Table 20-9.	Connections for Unused Signals (100-pin LQFP) .................................................	521
Table 20-10.	Connections for Unused Signals, 108-pin BGA ....................................................	521
Table 21-1.	Temperature Characteristics ...............................................................................	523
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Table 21-2.	Thermal Characteristics .....................................................................................	523
Table 21-3.	ESD Absolute Maximum Ratings ........................................................................	523
Table 22-1.	Maximum Ratings ..............................................................................................	524
Table 22-2.	Recommended DC Operating Conditions ............................................................	524
Table 22-3.	LDO Regulator Characteristics ...........................................................................	525
Table 22-4.	GPIO Module DC Characteristics ........................................................................	525
Table 22-5.	Detailed Power Specifications ............................................................................	526
Table 22-6.	Flash Memory Characteristics ............................................................................	527
Table 22-7.	Hibernation Module DC Characteristics ...............................................................	527
Table 22-8.	Phase Locked Loop (PLL) Characteristics ...........................................................	528
Table 22-9.	Actual PLL Frequency ........................................................................................	528
Table 22-10.	Clock Characteristics .........................................................................................	528
Table 22-11.	Crystal Characteristics .......................................................................................	529
Table 22-12.	System Clock Characteristics with ADC Operation ...............................................	529
Table 22-13.	JTAG Characteristics .........................................................................................	529
Table 22-14.	Reset Characteristics .........................................................................................	531
Table 22-15.	Sleep Modes AC Characteristics .........................................................................	533
Table 22-16.	Hibernation Module AC Characteristics ...............................................................	533
Table 22-17.	GPIO Characteristics .........................................................................................	534
Table 22-18.	ADC Characteristics ...........................................................................................	534
Table 22-19.	ADC Module Internal Reference Characteristics ..................................................	535
Table 22-20.	SSI Characteristics ............................................................................................	535
Table 22-21.	I2C Characteristics .............................................................................................	537
Table 22-22.	Analog Comparator Characteristics .....................................................................	538
Table 22-23.	Analog Comparator Voltage Reference Characteristics ........................................	538
Table C-1.	Part Ordering Information ...................................................................................	562

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Stellaris® LM3S1439 Microcontroller

List of Registers
System Control ..............................................................................................................................		68
Register 1:	Device Identification 0 (DID0), offset 0x000 .......................................................................	82
Register 2:	Brown-Out Reset Control (PBORCTL), offset 0x030 ..........................................................	84
Register 3:	LDO Power Control (LDOPCTL), offset 0x034 ...................................................................	85
Register 4:	Raw Interrupt Status (RIS), offset 0x050 ...........................................................................	86
Register 5:	Interrupt Mask Control (IMC), offset 0x054 ........................................................................	87
Register 6:	Masked Interrupt Status and Clear (MISC), offset 0x058 ....................................................	88
Register 7:	Reset Cause (RESC), offset 0x05C ..................................................................................	89
Register 8:	Run-Mode Clock Configuration (RCC), offset 0x060 ..........................................................	90
Register 9:	XTAL to PLL Translation (PLLCFG), offset 0x064 ..............................................................	94
Register 10:	Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ......................................................	95
Register 11:	Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ..........................................	97
Register 12:	Device Identification 1 (DID1), offset 0x004 .......................................................................	98
Register 13:	Device Capabilities 0 (DC0), offset 0x008 ........................................................................	100
Register 14:	Device Capabilities 1 (DC1), offset 0x010 ........................................................................	101
Register 15:	Device Capabilities 2 (DC2), offset 0x014 ........................................................................	103
Register 16:	Device Capabilities 3 (DC3), offset 0x018 ........................................................................	105
Register 17:	Device Capabilities 4 (DC4), offset 0x01C .......................................................................	107
Register 18:	Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ...................................	108
Register 19:	Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................	110
Register 20:	Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 .......................	112
Register 21:	Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ...................................	114
Register 22:	Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................	116
Register 23:	Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 .......................	118
Register 24:	Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ...................................	120
Register 25:	Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................	122
Register 26:	Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 .......................	124
Register 27:	Software Reset Control 0 (SRCR0), offset 0x040 .............................................................	126
Register 28:	Software Reset Control 1 (SRCR1), offset 0x044 .............................................................	127
Register 29:	Software Reset Control 2 (SRCR2), offset 0x048 .............................................................	129
Hibernation Module .....................................................................................................................		130
Register 1:	Hibernation RTC Counter (HIBRTCC), offset 0x000 .........................................................	138
Register 2:	Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 .......................................................	139
Register 3:	Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 .......................................................	140
Register 4:	Hibernation RTC Load (HIBRTCLD), offset 0x00C ...........................................................	141
Register 5:	Hibernation Control (HIBCTL), offset 0x010 .....................................................................	142
Register 6:	Hibernation Interrupt Mask (HIBIM), offset 0x014 .............................................................	144
Register 7:	Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 ..................................................	145
Register 8:	Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................	146
Register 9:	Hibernation Interrupt Clear (HIBIC), offset 0x020 .............................................................	147
Register 10:	Hibernation RTC Trim (HIBRTCT), offset 0x024 ...............................................................	148
Register 11:	Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................	149
Internal Memory ...........................................................................................................................		150
Register 1:	Flash Memory Address (FMA), offset 0x000 ....................................................................	155
Register 2:	Flash Memory Data (FMD), offset 0x004 .........................................................................	156

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Register 3:	Flash Memory Control (FMC), offset 0x008 .....................................................................	157
Register 4:	Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................	159
Register 5:	Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................	160
Register 6:	Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 .....................	161
Register 7:	USec Reload (USECRL), offset 0x140 ............................................................................	163
Register 8:	Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ...................	164
Register 9:	Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ...............	165
Register 10:	User Debug (USER_DBG), offset 0x1D0 .........................................................................	166
Register 11:	User Register 0 (USER_REG0), offset 0x1E0 ..................................................................	167
Register 12:	User Register 1 (USER_REG1), offset 0x1E4 ..................................................................	168
Register 13:	Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 ....................................	169
Register 14:	Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 ....................................	170
Register 15:	Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ...................................	171
Register 16:	Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ...............................	172
Register 17:	Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ...............................	173
Register 18:	Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ...............................	174

General-Purpose Input/Outputs (GPIOs) ...................................................................................		175
Register 1:	GPIO Data (GPIODATA), offset 0x000 ............................................................................	183
Register 2:	GPIO Direction (GPIODIR), offset 0x400 .........................................................................	184
Register 3:	GPIO Interrupt Sense (GPIOIS), offset 0x404 ..................................................................	185
Register 4:	GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................	186
Register 5:	GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................	187
Register 6:	GPIO Interrupt Mask (GPIOIM), offset 0x410 ...................................................................	188
Register 7:	GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................	189
Register 8:	GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ...................................................	190
Register 9:	GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................	191
Register 10:	GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................	192
Register 11:	GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................	194
Register 12:	GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................	195
Register 13:	GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................	196
Register 14:	GPIO Open Drain Select (GPIOODR), offset 0x50C .........................................................	197
Register 15:	GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................	198
Register 16:	GPIO Pull-Down Select (GPIOPDR), offset 0x514 ...........................................................	199
Register 17:	GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................	200
Register 18:	GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................	201
Register 19:	GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................	202
Register 20:	GPIO Commit (GPIOCR), offset 0x524 ............................................................................	203
Register 21:	GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 .......................................	205
Register 22:	GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 .......................................	206
Register 23:	GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 .......................................	207
Register 24:	GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ......................................	208
Register 25:	GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 .......................................	209
Register 26:	GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 .......................................	210
Register 27:	GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 .......................................	211
Register 28:	GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ......................................	212
Register 29:	GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 ..........................................	213
Register 30:	GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 ..........................................	214
Register 31:	GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 ..........................................	215
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Stellaris® LM3S1439 Microcontroller

Register 32:	GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC .........................................	216
General-Purpose Timers .............................................................................................................		217
Register 1:	GPTM Configuration (GPTMCFG), offset 0x000 ..............................................................	229
Register 2:	GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................	230
Register 3:	GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................	232
Register 4:	GPTM Control (GPTMCTL), offset 0x00C ........................................................................	234
Register 5:	GPTM Interrupt Mask (GPTMIMR), offset 0x018 ..............................................................	237
Register 6:	GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .....................................................	239
Register 7:	GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................	240
Register 8:	GPTM Interrupt Clear (GPTMICR), offset 0x024 ..............................................................	241
Register 9:	GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 .................................................	243
Register 10:	GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................	244
Register 11:	GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ...................................................	245
Register 12:	GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 ..................................................	246
Register 13:	GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................	247
Register 14:	GPTM TimerB Prescale (GPTMTBPR), offset 0x03C .......................................................	248
Register 15:	GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ...........................................	249
Register 16:	GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ...........................................	250
Register 17:	GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................	251
Register 18:	GPTM TimerB (GPTMTBR), offset 0x04C .......................................................................	252
Watchdog Timer ...........................................................................................................................		253
Register 1:	Watchdog Load (WDTLOAD), offset 0x000 ......................................................................	257
Register 2:	Watchdog Value (WDTVALUE), offset 0x004 ...................................................................	258
Register 3:	Watchdog Control (WDTCTL), offset 0x008 .....................................................................	259
Register 4:	Watchdog Interrupt Clear (WDTICR), offset 0x00C ..........................................................	260
Register 5:	Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ..................................................	261
Register 6:	Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 .............................................	262
Register 7:	Watchdog Test (WDTTEST), offset 0x418 .......................................................................	263
Register 8:	Watchdog Lock (WDTLOCK), offset 0xC00 .....................................................................	264
Register 9:	Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 .................................	265
Register 10:	Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 .................................	266
Register 11:	Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 .................................	267
Register 12:	Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................	268
Register 13:	Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 .................................	269
Register 14:	Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 .................................	270
Register 15:	Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 .................................	271
Register 16:	Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................	272
Register 17:	Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 ....................................	273
Register 18:	Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 ....................................	274
Register 19:	Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 ....................................	275
Register 20:	Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ..................................	276
Analog-to-Digital Converter (ADC) .............................................................................................		277
Register 1:	ADC Active Sample Sequencer (ADCACTSS), offset 0x000 .............................................	286
Register 2:	ADC Raw Interrupt Status (ADCRIS), offset 0x004 ...........................................................	287
Register 3:	ADC Interrupt Mask (ADCIM), offset 0x008 .....................................................................	288
Register 4:	ADC Interrupt Status and Clear (ADCISC), offset 0x00C ..................................................	289
Register 5:	ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................	291
Register 6:	ADC Event Multiplexer Select (ADCEMUX), offset 0x014 .................................................	292
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Register 7:	ADC Underflow Status (ADCUSTAT), offset 0x018 ...........................................................	296
Register 8:	ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 .............................................	297
Register 9:	ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 .................................	299
Register 10:	ADC Sample Averaging Control (ADCSAC), offset 0x030 .................................................	300
Register 11:	ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ...............	301
Register 12:	ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................	303
Register 13:	ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................	306
Register 14:	ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................	306
Register 15:	ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................	306
Register 16:	ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ...............................	306
Register 17:	ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C .............................	307
Register 18:	ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C .............................	307
Register 19:	ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................	307
Register 20:	ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................	307
Register 21:	ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ...............	308
Register 22:	ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ...............	308
Register 23:	ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................	309
Register 24:	ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................	309
Register 25:	ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ...............	311
Register 26:	ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................	312
Register 27:	ADC Test Mode Loopback (ADCTMLB), offset 0x100 .......................................................	313
Universal Asynchronous Receivers/Transmitters (UARTs) .....................................................		314
Register 1:	UART Data (UARTDR), offset 0x000 ...............................................................................	322
Register 2:	UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ...........................	324
Register 3:	UART Flag (UARTFR), offset 0x018 ................................................................................	326
Register 4:	UART IrDA Low-Power Register (UARTILPR), offset 0x020 .............................................	328
Register 5:	UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................	329
Register 6:	UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 .......................................	330
Register 7:	UART Line Control (UARTLCRH), offset 0x02C ...............................................................	331
Register 8:	UART Control (UARTCTL), offset 0x030 .........................................................................	333
Register 9:	UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ...........................................	335
Register 10:	UART Interrupt Mask (UARTIM), offset 0x038 .................................................................	337
Register 11:	UART Raw Interrupt Status (UARTRIS), offset 0x03C ......................................................	339
Register 12:	UART Masked Interrupt Status (UARTMIS), offset 0x040 .................................................	340
Register 13:	UART Interrupt Clear (UARTICR), offset 0x044 ...............................................................	341
Register 14:	UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 .....................................	343
Register 15:	UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 .....................................	344
Register 16:	UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 .....................................	345
Register 17:	UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC .....................................	346
Register 18:	UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ......................................	347
Register 19:	UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ......................................	348
Register 20:	UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ......................................	349
Register 21:	UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC .....................................	350
Register 22:	UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................	351
Register 23:	UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................	352
Register 24:	UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................	353
Register 25:	UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................	354

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Synchronous Serial Interface (SSI) ............................................................................................		355
Register 1:	SSI Control 0 (SSICR0), offset 0x000 ..............................................................................	367
Register 2:	SSI Control 1 (SSICR1), offset 0x004 ..............................................................................	369
Register 3:	SSI Data (SSIDR), offset 0x008 ......................................................................................	371
Register 4:	SSI Status (SSISR), offset 0x00C ...................................................................................	372
Register 5:	SSI Clock Prescale (SSICPSR), offset 0x010 ..................................................................	374
Register 6:	SSI Interrupt Mask (SSIIM), offset 0x014 .........................................................................	375
Register 7:	SSI Raw Interrupt Status (SSIRIS), offset 0x018 ..............................................................	377
Register 8:	SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................	378
Register 9:	SSI Interrupt Clear (SSIICR), offset 0x020 .......................................................................	379
Register 10:	SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 .............................................	380
Register 11:	SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 .............................................	381
Register 12:	SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 .............................................	382
Register 13:	SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................	383
Register 14:	SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 .............................................	384
Register 15:	SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 .............................................	385
Register 16:	SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 .............................................	386
Register 17:	SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................	387
Register 18:	SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ...............................................	388
Register 19:	SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ...............................................	389
Register 20:	SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ...............................................	390
Register 21:	SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ...............................................	391
Inter-Integrated Circuit (I2C) Interface ........................................................................................		392
Register 1:	I2C Master Slave Address (I2CMSA), offset 0x000 ...........................................................	407
Register 2:	I2C Master Control/Status (I2CMCS), offset 0x004 ...........................................................	408
Register 3:	I2C Master Data (I2CMDR), offset 0x008 .........................................................................	412
Register 4:	I2C Master Timer Period (I2CMTPR), offset 0x00C ...........................................................	413
Register 5:	I2C Master Interrupt Mask (I2CMIMR), offset 0x010 .........................................................	414
Register 6:	I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 .................................................	415
Register 7:	I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ...........................................	416
Register 8:	I2C Master Interrupt Clear (I2CMICR), offset 0x01C .........................................................	417
Register 9:	I2C Master Configuration (I2CMCR), offset 0x020 ............................................................	418
Register 10:	I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................	420
Register 11:	I2C Slave Control/Status (I2CSCSR), offset 0x004 ...........................................................	421
Register 12:	I2C Slave Data (I2CSDR), offset 0x008 ...........................................................................	423
Register 13:	I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ...........................................................	424
Register 14:	I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ...................................................	425
Register 15:	I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 ..............................................	426
Register 16:	I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................	427
Analog Comparator .....................................................................................................................		428
Register 1:	Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ..................................	432
Register 2:	Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 .......................................	433
Register 3:	Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 .........................................	434
Register 4:	Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 .......................	435
Register 5:	Analog Comparator Status 0 (ACSTAT0), offset 0x020 .....................................................	436
Register 6:	Analog Comparator Control 0 (ACCTL0), offset 0x024 .....................................................	437

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Pulse Width Modulator (PWM) ....................................................................................................		439
Register 1:	PWM Master Control (PWMCTL), offset 0x000 ................................................................	448
Register 2:	PWM Time Base Sync (PWMSYNC), offset 0x004 ...........................................................	449
Register 3:	PWM Output Enable (PWMENABLE), offset 0x008 ..........................................................	450
Register 4:	PWM Output Inversion (PWMINVERT), offset 0x00C .......................................................	451
Register 5:	PWM Output Fault (PWMFAULT), offset 0x010 ................................................................	452
Register 6:	PWM Interrupt Enable (PWMINTEN), offset 0x014 ...........................................................	453
Register 7:	PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................	454
Register 8:	PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................	455
Register 9:	PWM Status (PWMSTATUS), offset 0x020 ......................................................................	456
Register 10:	PWM0 Control (PWM0CTL), offset 0x040 .......................................................................	457
Register 11:	PWM1 Control (PWM1CTL), offset 0x080 .......................................................................	457
Register 12:	PWM2 Control (PWM2CTL), offset 0x0C0 ......................................................................	457
Register 13:	PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 ....................................	459
Register 14:	PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 ....................................	459
Register 15:	PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 ....................................	459
Register 16:	PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 ....................................................	462
Register 17:	PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 ....................................................	462
Register 18:	PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ...................................................	462
Register 19:	PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ...........................................	463
Register 20:	PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ...........................................	463
Register 21:	PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ...........................................	463
Register 22:	PWM0 Load (PWM0LOAD), offset 0x050 .......................................................................	464
Register 23:	PWM1 Load (PWM1LOAD), offset 0x090 .......................................................................	464
Register 24:	PWM2 Load (PWM2LOAD), offset 0x0D0 .......................................................................	464
Register 25:	PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................	465
Register 26:	PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................	465
Register 27:	PWM2 Counter (PWM2COUNT), offset 0x0D4 ...............................................................	465
Register 28:	PWM0 Compare A (PWM0CMPA), offset 0x058 .............................................................	466
Register 29:	PWM1 Compare A (PWM1CMPA), offset 0x098 .............................................................	466
Register 30:	PWM2 Compare A (PWM2CMPA), offset 0x0D8 .............................................................	466
Register 31:	PWM0 Compare B (PWM0CMPB), offset 0x05C .............................................................	467
Register 32:	PWM1 Compare B (PWM1CMPB), offset 0x09C .............................................................	467
Register 33:	PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................	467
Register 34:	PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................	468
Register 35:	PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................	468
Register 36:	PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................	468
Register 37:	PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................	471
Register 38:	PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................	471
Register 39:	PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................	471
Register 40:	PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................	474
Register 41:	PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 .................................................	474
Register 42:	PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................	474
Register 43:	PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C .............................	475
Register 44:	PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC .............................	475
Register 45:	PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC .............................	475
Register 46:	PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 .............................	476
Register 47:	PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 .............................	476

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Register 48:	PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 .............................	476
Quadrature Encoder Interface (QEI) ..........................................................................................		477
Register 1:	QEI Control (QEICTL), offset 0x000 ................................................................................	482
Register 2:	QEI Status (QEISTAT), offset 0x004 ................................................................................	484
Register 3:	QEI Position (QEIPOS), offset 0x008 ..............................................................................	485
Register 4:	QEI Maximum Position (QEIMAXPOS), offset 0x00C .......................................................	486
Register 5:	QEI Timer Load (QEILOAD), offset 0x010 .......................................................................	487
Register 6:	QEI Timer (QEITIME), offset 0x014 .................................................................................	488
Register 7:	QEI Velocity Counter (QEICOUNT), offset 0x018 .............................................................	489
Register 8:	QEI Velocity (QEISPEED), offset 0x01C ..........................................................................	490
Register 9:	QEI Interrupt Enable (QEIINTEN), offset 0x020 ...............................................................	491
Register 10:	QEI Raw Interrupt Status (QEIRIS), offset 0x024 .............................................................	492
Register 11:	QEI Interrupt Status and Clear (QEIISC), offset 0x028 .....................................................	493

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Revision History

The revision history table notes changes made between the indicated revisions of the LM3S1439 data sheet.

Table 1. Revision History

Date	Revision	Description
June 2010	7393	■ Corrected base address for SRAM in architectural overview chapter.
		■ Clarified system clock operation, adding content to “Clock Control” on page 72.
		■ In Signal Tables chapter, added table "Connections for Unused Signals."
		■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
		■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.
		■ Additional minor data sheet clarifications and corrections.
April 2010	7007	■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
		field width to 7 bits.
		■ Removed erroneous text about restoring the Flash Protection registers.
		■ Added note about		signal routing.
			RST
		■ Clarified the function of the TnSTALL bit in the GPTMCTL register.
		■ Additional minor data sheet clarifications and corrections.
January 2010	6712	■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.
		■ Clarified wording on Flash memory access errors.
		■ Added section on Flash interrupts.

■ Changed the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers to be indeterminate.

■ Clarified operation of SSI transmit FIFO.

■ Made these changes to the Operating Characteristics chapter:

– Added storage temperature ratings to "Temperature Characteristics" table

– Added "ESD Absolute Maximum Ratings" table

■ Made these changes to the Electrical Characteristics chapter:

– In "Flash Memory Characteristics" table, corrected Mass erase time

– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)

– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time

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Table 1. Revision History (continued)

Date	Revision	Description
October 2009	6462	■ Deleted MAXADCSPD bit field from DCGC0 register as it is not applicable in Deep-Sleep mode.
		■ Removed erroneous reference to the WRC bit in the Hibernation chapter.
		■ Deletedresetvaluefor16-bitmodefrom GPTMTAILR, GPTMTAMATCHR,and GPTMTAR registers
		because the module resets in 32-bit mode.
		■ Clarified PWM source for ADC triggering.
		■ Made these changes to the Electrical Characteristics chapter:
		– Removed VSIH and VSIL parameters from Operating Conditions table.
		– Added table showing actual PLL frequency depending on input crystal.
		– Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS.
		– Revised ADC electrical specifications to clarify, including reorganizing and adding new data.
		– Changed SSI set up and hold times to be expressed in system clocks, not ns.
July 2009	5920	Corrected ordering numbers.
July 2009	5902	■ Clarified Power-on reset and		pin operation; added new diagrams.
			RST

■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)

registers.

■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.

■ AddedexplanationofresetvaluetoFMPRE0/1/2/3,FMPPE0/1/2/3,USER_DBG,andUSER_REG0/1

registers.

■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.

■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR (Internal voltage reference error) parameter.

■ Additional minor data sheet clarifications and corrections.

April 2009

5367

■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 62).

■Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor.

■Added "GPIO Module DC Characteristics" table (see Table 22-4 on page 525).

■Additional minor data sheet clarifications and corrections.

January 2009

4660

■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.

■Clarification added as to what happens when the SSI in slave mode is required to transmit but there is no data in the TX FIFO.

■Additional minor data sheet clarifications and corrections.

November 2008

4283

■ Revised High-Level Block Diagram.

■Additional minor data sheet clarifications and corrections were made.

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Revision History

Table 1. Revision History (continued)

Date	Revision	Description
October 2008	4149	■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
		register.
		■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
		Internal Memory chapter. The correct value is 0x0000.0006.
		■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.

August 2008

3447

■ Added note on clearing interrupts to Interrupts chapter.

■Added Power Architecture diagram to System Control chapter.

■Additional minor data sheet clarifications and corrections.

July 2008	3108	■ Additional minor data sheet clarifications and corrections.
May 2008	2972	■ The 108-Ball BGA pin diagram and pin tables had an error. The following signals were erroneously
		indicated as available and have now been changed to a No Connect (NC):
		– Ball C1: Changed PE7 to NC
		– Ball C2: Changed PE6 to NC
		– Ball D2: Changed PE5 to NC
		– Ball D1: Changed PE4 to NC
		■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
		the LDO output as the source of VDD25 input.
		■ Additional minor data sheet clarifications and corrections.
April 2008	2881	■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating

Characteristics chapter.

■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of 1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.

■ Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical Characteristics" chapter.

■ The "Hibernation Module DC Electricals"table was added to the "Electrical Characteristics"chapter.

■ The TVDDRISE parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter was changed from a max of 100 to 250.

■ The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical

Characteristics" chapter was changed from 4 to 3.

■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data sheets incorrectly noted it as 30 kHz ± 30%).

■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value.

■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly noted the reset was 0x0 (MOSC).

■ Two figures on clock source were added to the "Hibernation Module":

– Clock Source Using Crystal

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Table 1. Revision History (continued)

Date	Revision Description

–Clock Source Using Dedicated Oscillator

■The following notes on battery management were added to the "Hibernation Module" chapter:

–Battery voltage is not measured while in Hibernate mode.

–System level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements.

■A note on high-current applications was added to the GPIO chapter:

For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package.

■A note on Schmitt inputs was added to the GPIO chapter: Pins configured as digital inputs are Schmitt-triggered.

■The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.

■The "Differential Sampling Range" figures in the ADC chapter were clarified.

■Thelastrevisionofthedatasheet(revision2550)introducedtwoerrorsthathavenowbeencorrected:

–The LQFP pin diagrams and pin tables were missing the comparator positive and negative input pins.

–The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.

■Additional minor data sheet clarifications and corrections.

March 2008

2550

Started tracking revision history.

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About This Document

This data sheet provides reference information for the LM3S1439 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core.

Audience

This manual is intended for system software developers, hardware designers, and application developers.

About This Manual

This document is organized into sections that correspond to each major feature.

Documentation Conventions

This document uses the conventions shown in Table 2 on page 25.

Table 2. Documentation Conventions

Notation Meaning

General Register Notation

REGISTER	APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
	Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
	than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
	registers: SRCR0, SRCR1 , and SRCR2.
bit	A single bit in a register.
bit field	Two or more consecutive and related bits.
offset 0xnnn	A hexadecimal increment to a register's address, relative to that module's base address as specified
	in “Memory Map” on page 51.
Register N	Registers are numbered consecutively throughout the document to aid in referencing them. The
	register number has no meaning to software.
reserved	Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
	0; however, user software should not rely on the value of a reserved bit. To provide software
	compatibility with future products, the value of a reserved bit should be preserved across a
	read-modify-write operation.
yy:xx	The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
	that register.
Register Bit/Field	This value in the register bit diagram indicates whether software running on the controller can
Types	change the value of the bit field.
RC	Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO	Software can read this field. Always write the chip reset value.
R/W	Software can read or write this field.
R/W1C	Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
	register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
	This register type is primarily used for clearing interrupt status bits where the read operation
	provides the interrupt status and the write of the read value clears only the interrupts being reported
	at the time the register was read.
R/W1S	Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
	value in the register.
W1C	Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
	A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
	read of the register returns no meaningful data.
	This register is typically used to clear the corresponding bit in an interrupt register.
WO	Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field	This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0	Bit cleared to 0 on chip reset.
1	Bit set to 1 on chip reset.
-	Nondeterministic.
Pin/Signal Notation
[ ]	Pin alternate function; a pin defaults to the signal without the brackets.
pin	Refers to the physical connection on the package.
signal	Refers to the electrical signal encoding of a pin.

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About This Document

Table 2. Documentation Conventions (continued)


Notation	Meaning
assert a signal	Change the value of the signal from the logically False state to the logically True state. For active
	High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
	is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and
						SIGNAL
	below).
deassert a signal	Change the value of the signal from the logically True state to the logically False state.
	Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
SIGNAL
	it is active Low. To assert		is to drive it Low; to deassert		is to drive it High.
		SIGNAL		SIGNAL
SIGNAL	Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
	assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.

Numbers

XAn uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on.

0x	Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
	All other numbers within register tables are assumed to be binary. Within conceptual information,
	binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
	without a prefix or suffix.

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1Architectural Overview

The Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.

The Stellaris® family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris® LM3S1000 series extends the Stellaris® family with larger on-chip memories, enhanced power management, and expanded I/O and control capabilities.

The LM3S1439 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security.

For applications requiring extreme conservation of power, the LM3S1439 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S1439 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S1439 microcontroller perfectly for battery applications.

In addition, the LM3S1439 microcontroller offers the advantages of ARM's widely available development tools,System-on-Chip(SoC) infrastructureIPapplications,and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S1439 microcontroller is code-compatible to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise needs.

Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See “Ordering and Contact

Information” on page 562 for ordering information for Stellaris® family devices.

1.1Product Features

The LM3S1439 microcontroller includes the following product features:

■32-Bit RISC Performance

–32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications

–System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism

–Thumb®-compatible Thumb-2-only instruction set processor core for high code density

–50-MHz operation

–Hardware-division and single-cycle-multiplication

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Architectural Overview

–Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling

–33 interrupts with eight priority levels

–Memory protection unit (MPU), providing a privileged mode for protected operating system functionality

–Unaligned data access, enabling data to be efficiently packed into memory

–Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control

■ARM® Cortex™-M3 Processor Core

–Compact core.

–Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications.

–Rapid application execution through Harvard architecture characterized by separate buses for instruction and data.

–Exceptionalinterrupthandling,byimplementingtheregistermanipulationsrequiredforhandling an interrupt in hardware.

–Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining

–Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.

–Migration from the ARM7™ processor family for better performance and power efficiency.

–Full-featured debug solution

•Serial Wire JTAG Debug Port (SWJ-DP)

•Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

•Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling

•Instrumentation Trace Macrocell (ITM) for support of printf style debugging

•Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

–Optimized for single-cycle flash usage

–Three sleep modes with clock gating for low power

–Single-cycle multiply instruction and hardware divide

–Atomic operations

–ARM Thumb2 mixed 16-/32-bit instruction set

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–1.25 DMIPS/MHz

■JTAG

–IEEE 1149.1-1990 compatible Test Access Port (TAP) controller

–Four-bit Instruction Register (IR) chain for storing JTAG instructions

–IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST

–ARM additional instructions: APACC, DPACC and ABORT

–Integrated ARM Serial Wire Debug (SWD)

■Hibernation

–System power control using discrete external regulator

–Dedicated pin for waking from an external signal

–Low-battery detection, signaling, and interrupt generation

–32-bit real-time clock (RTC)

–Two 32-bit RTC match registers for timed wake-up and interrupt generation

–Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal

–RTC predivider trim for making fine adjustments to the clock rate

–64 32-bit words of non-volatile memory

–Programmable interrupts for RTC match, external wake, and low battery events

■Internal Memory

–96 KB single-cycle flash

•User-managed flash block protection on a 2-KB block basis

•User-managed flash data programming

•User-defined and managed flash-protection block

–32 KB single-cycle SRAM

■GPIOs

–14-52 GPIOs, depending on configuration

–5-V-tolerant input/outputs

–Programmable control for GPIO interrupts

•Interrupt generation masking

•Edge-triggered on rising, falling, or both

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Architectural Overview

•Level-sensitive on High or Low values

–Bit masking in both read and write operations through address lines

–Can initiate an ADC sample sequence

–Pins configured as digital inputs are Schmitt-triggered.

–Programmable control for GPIO pad configuration

•Weak pull-up or pull-down resistors

•2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications

•Slew rate control for the 8-mA drive

•Open drain enables

•Digital input enables

■General-Purpose Timers

–Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently:

•As a single 32-bit timer

•As one 32-bit Real-Time Clock (RTC) to event capture

•For Pulse Width Modulation (PWM)

•To trigger analog-to-digital conversions

–32-bit Timer modes

•Programmable one-shot timer

•Programmable periodic timer

•Real-Time Clock when using an external 32.768-KHz clock as the input

•User-enabled stalling when the controller asserts CPU Halt flag during debug

•ADC event trigger

–16-bit Timer modes

•General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)

•Programmable one-shot timer

•Programmable periodic timer

•User-enabled stalling when the controller asserts CPU Halt flag during debug

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+ 538 hidden pages

Texas instruments STELLARIS LM3S1439 DATA SHEET

Stellaris® LM3S1439 Microcontroller

Table of Contents

List of Figures

List of Tables

List of Registers

Revision History

About This Document

Audience

About This Manual

Related Documents

Documentation Conventions

1Architectural Overview

1.1Product Features