Texas instruments STELLARIS LM3S1332 DATA SHEET

TEXAS INSTRUMENTS-PRODUCTION DATA

Stellaris® LM3S1332 Microcontroller

DATA SHEET

DS-LM3S1332-7393	Copyright © 2007-2010 Texas Instruments
	Incorporated

Copyright

Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Pleasebe awarethatan importantnoticeconcerningavailability, standardwarranty, and use in criticalapplicationsof TexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated

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http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

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		Stellaris® LM3S1332 Microcontroller
Table of Contents
Revision History .............................................................................................................................		17
About This Document ....................................................................................................................		21
Audience ..............................................................................................................................................		21
About This Manual ................................................................................................................................		21
Related Documents ...............................................................................................................................		21
Documentation Conventions ..................................................................................................................		22
1	Architectural Overview ..........................................................................................	24
1.1	Product Features ..........................................................................................................	24
1.2	Target Applications ........................................................................................................	30
1.3	High-Level Block Diagram .............................................................................................	31
1.4	Functional Overview ......................................................................................................	33
1.4.1	ARM Cortex™-M3 .........................................................................................................	33
1.4.2	Motor Control Peripherals ..............................................................................................	33
1.4.3	Analog Peripherals ........................................................................................................	34
1.4.4	Serial Communications Peripherals ................................................................................	35
1.4.5	System Peripherals .......................................................................................................	35
1.4.6	Memory Peripherals ......................................................................................................	36
1.4.7	Additional Features .......................................................................................................	37
1.4.8	Hardware Details ..........................................................................................................	37
2	ARM Cortex-M3 Processor Core ...........................................................................	39
2.1	Block Diagram ..............................................................................................................	40
2.2	Functional Description ...................................................................................................	40
2.2.1	Serial Wire and JTAG Debug .........................................................................................	40
2.2.2	Embedded Trace Macrocell (ETM) .................................................................................	41
2.2.3	Trace Port Interface Unit (TPIU) .....................................................................................	41
2.2.4	ROM Table ...................................................................................................................	41
2.2.5	Memory Protection Unit (MPU) .......................................................................................	41
2.2.6	Nested Vectored Interrupt Controller (NVIC) ....................................................................	41
3	Memory Map ...........................................................................................................	45
4	Interrupts .................................................................................................................	47
5	JTAG Interface ........................................................................................................	50
5.1	Block Diagram ..............................................................................................................	51
5.2	Functional Description ...................................................................................................	51
5.2.1	JTAG Interface Pins ......................................................................................................	51
5.2.2	JTAG TAP Controller .....................................................................................................	53
5.2.3	Shift Registers ..............................................................................................................	54
5.2.4	Operational Considerations ............................................................................................	54
5.3	Initialization and Configuration .......................................................................................	57
5.4	Register Descriptions ....................................................................................................	57
5.4.1	Instruction Register (IR) .................................................................................................	57
5.4.2	Data Registers ..............................................................................................................	59
6	System Control .......................................................................................................	62
6.1	Functional Description ...................................................................................................	62
6.1.1	Device Identification ......................................................................................................	62
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6.1.2	Reset Control ................................................................................................................	62
6.1.3	Power Control ...............................................................................................................	65
6.1.4	Clock Control ................................................................................................................	66
6.1.5	System Control .............................................................................................................	71
6.2	Initialization and Configuration .......................................................................................	72
6.3	Register Map ................................................................................................................	73
6.4	Register Descriptions ....................................................................................................	74

7	Hibernation Module ..............................................................................................	124
7.1	Block Diagram ............................................................................................................	125
7.2	Functional Description .................................................................................................	125
7.2.1	Register Access Timing ...............................................................................................	125
7.2.2	Clock Source ..............................................................................................................	126
7.2.3	Battery Management ...................................................................................................	127
7.2.4	Real-Time Clock ..........................................................................................................	127
7.2.5	Non-Volatile Memory ...................................................................................................	128
7.2.6	Power Control .............................................................................................................	128
7.2.7	Initiating Hibernate ......................................................................................................	128
7.2.8	Interrupts and Status ...................................................................................................	129
7.3	Initialization and Configuration .....................................................................................	129
7.3.1	Initialization .................................................................................................................	129
7.3.2	RTC Match Functionality (No Hibernation) ....................................................................	129
7.3.3	RTC Match/Wake-Up from Hibernation .........................................................................	130
7.3.4	External Wake-Up from Hibernation ..............................................................................	130
7.3.5	RTC/External Wake-Up from Hibernation ......................................................................	130
7.4	Register Map ..............................................................................................................	130
7.5	Register Descriptions ..................................................................................................	131

8	Internal Memory ...................................................................................................	144
8.1	Block Diagram ............................................................................................................	144
8.2	Functional Description .................................................................................................	144
8.2.1	SRAM Memory ............................................................................................................	144
8.2.2	Flash Memory .............................................................................................................	145
8.3	Flash Memory Initialization and Configuration ...............................................................	146
8.3.1	Flash Programming .....................................................................................................	146
8.3.2	Nonvolatile Register Programming ...............................................................................	147
8.4	Register Map ..............................................................................................................	148
8.5	Flash Register Descriptions (Flash Control Offset) .........................................................	148
8.6	Flash Register Descriptions (System Control Offset) ......................................................	156

9	General-Purpose Input/Outputs (GPIOs)	........................................................... 169
9.1	Functional Description .................................................................................................	169
9.1.1	Data Control ...............................................................................................................	170
9.1.2	Interrupt Control ..........................................................................................................	171
9.1.3	Mode Control ..............................................................................................................	172
9.1.4	Commit Control ...........................................................................................................	172
9.1.5	Pad Control .................................................................................................................	172
9.1.6	Identification ...............................................................................................................	173
9.2	Initialization and Configuration .....................................................................................	173
9.3	Register Map ..............................................................................................................	174
9.4	Register Descriptions ..................................................................................................	176
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10	General-Purpose Timers ......................................................................................	211
10.1	Block Diagram ............................................................................................................	212
10.2	Functional Description .................................................................................................	213
10.2.1	GPTM Reset Conditions ..............................................................................................	213
10.2.2	32-Bit Timer Operating Modes ......................................................................................	213
10.2.3	16-Bit Timer Operating Modes ......................................................................................	214
10.3	Initialization and Configuration .....................................................................................	218
10.3.1	32-Bit One-Shot/Periodic Timer Mode ...........................................................................	218
10.3.2	32-Bit Real-Time Clock (RTC) Mode .............................................................................	219
10.3.3	16-Bit One-Shot/Periodic Timer Mode ...........................................................................	219
10.3.4	16-Bit Input Edge Count Mode .....................................................................................	220
10.3.5	16-Bit Input Edge Timing Mode ....................................................................................	220
10.3.6	16-Bit PWM Mode .......................................................................................................	221
10.4	Register Map ..............................................................................................................	221
10.5	Register Descriptions ..................................................................................................	222
11	Watchdog Timer ...................................................................................................	247
11.1	Block Diagram ............................................................................................................	248
11.2	Functional Description .................................................................................................	248
11.3	Initialization and Configuration .....................................................................................	249
11.4	Register Map ..............................................................................................................	249
11.5	Register Descriptions ..................................................................................................	250
12	Analog-to-Digital Converter (ADC) .....................................................................	271
12.1	Block Diagram ............................................................................................................	271
12.2	Functional Description .................................................................................................	272
12.2.1	Sample Sequencers ....................................................................................................	272
12.2.2	Module Control ............................................................................................................	273
12.2.3	Hardware Sample Averaging Circuit .............................................................................	274
12.2.4	Analog-to-Digital Converter ..........................................................................................	274
12.2.5	Differential Sampling ...................................................................................................	274
12.2.6	Test Modes .................................................................................................................	276
12.2.7	Internal Temperature Sensor ........................................................................................	277
12.3	Initialization and Configuration .....................................................................................	277
12.3.1	Module Initialization .....................................................................................................	277
12.3.2	Sample Sequencer Configuration .................................................................................	278
12.4	Register Map ..............................................................................................................	278
12.5	Register Descriptions ..................................................................................................	279
13	Universal Asynchronous Receivers/Transmitters (UARTs) .............................	307
13.1	Block Diagram ............................................................................................................	308
13.2	Functional Description .................................................................................................	308
13.2.1	Transmit/Receive Logic ...............................................................................................	308
13.2.2	Baud-Rate Generation .................................................................................................	309
13.2.3	Data Transmission ......................................................................................................	310
13.2.4	Serial IR (SIR) .............................................................................................................	310
13.2.5	FIFO Operation ...........................................................................................................	311
13.2.6	Interrupts ....................................................................................................................	311
13.2.7	Loopback Operation ....................................................................................................	312
13.2.8	IrDA SIR block ............................................................................................................	312
13.3	Initialization and Configuration .....................................................................................	312
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13.4	Register Map ..............................................................................................................	313
13.5	Register Descriptions ..................................................................................................	314

14	Synchronous Serial Interface (SSI) ....................................................................	348
14.1	Block Diagram ............................................................................................................	348
14.2	Functional Description .................................................................................................	348
14.2.1	Bit Rate Generation .....................................................................................................	349
14.2.2	FIFO Operation ...........................................................................................................	349
14.2.3	Interrupts ....................................................................................................................	349
14.2.4	Frame Formats ...........................................................................................................	350
14.3	Initialization and Configuration .....................................................................................	357
14.4	Register Map ..............................................................................................................	358
14.5	Register Descriptions ..................................................................................................	359

15	Analog Comparators ............................................................................................	385
15.1	Block Diagram ............................................................................................................	386
15.2	Functional Description .................................................................................................	386
15.2.1	Internal Reference Programming ..................................................................................	387
15.3	Initialization and Configuration .....................................................................................	388
15.4	Register Map ..............................................................................................................	388
15.5	Register Descriptions ..................................................................................................	389
16	Pin Diagram ..........................................................................................................	397
17	Signal Tables ........................................................................................................	399
17.1	100-Pin LQFP Package Pin Tables ...............................................................................	399
17.2	108-Pin BGA Package Pin Tables ................................................................................	410
17.3	Connections for Unused Signals ...................................................................................	422
18	Operating Characteristics ...................................................................................	424
19	Electrical Characteristics ....................................................................................	425
19.1	DC Characteristics ......................................................................................................	425
19.1.1	Maximum Ratings .......................................................................................................	425
19.1.2	Recommended DC Operating Conditions ......................................................................	425
19.1.3	On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................	426
19.1.4	GPIO Module Characteristics .......................................................................................	426
19.1.5	Power Specifications ...................................................................................................	426
19.1.6	Flash Memory Characteristics ......................................................................................	428
19.1.7	Hibernation .................................................................................................................	428
19.2	AC Characteristics .......................................................................................................	428
19.2.1	Load Conditions ..........................................................................................................	428
19.2.2	Clocks ........................................................................................................................	429
19.2.3	JTAG and Boundary Scan ............................................................................................	430
19.2.4	Reset .........................................................................................................................	432
19.2.5	Sleep Modes ...............................................................................................................	434
19.2.6	Hibernation Module .....................................................................................................	434
19.2.7	General-Purpose I/O (GPIO) ........................................................................................	435
19.2.8	Analog-to-Digital Converter ..........................................................................................	435
19.2.9	Synchronous Serial Interface (SSI) ...............................................................................	436
19.2.10	Analog Comparator .....................................................................................................	438
A	Serial Flash Loader ..............................................................................................	439
A.1	Serial Flash Loader .....................................................................................................	439
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A.2	Interfaces ...................................................................................................................	439
A.2.1	UART .........................................................................................................................	439
A.2.2	SSI .............................................................................................................................	439
A.3	Packet Handling ..........................................................................................................	440
A.3.1	Packet Format ............................................................................................................	440
A.3.2	Sending Packets .........................................................................................................	440
A.3.3	Receiving Packets .......................................................................................................	440
A.4	Commands .................................................................................................................	441
A.4.1	COMMAND_PING (0X20) ............................................................................................	441
A.4.2	COMMAND_GET_STATUS (0x23) ...............................................................................	441
A.4.3	COMMAND_DOWNLOAD (0x21) .................................................................................	441
A.4.4	COMMAND_SEND_DATA (0x24) .................................................................................	442
A.4.5	COMMAND_RUN (0x22) .............................................................................................	442
A.4.6	COMMAND_RESET (0x25) .........................................................................................	442
B	Register Quick Reference ...................................................................................	444
C	Ordering and Contact Information .....................................................................	457
C.1	Ordering Information ....................................................................................................	457
C.2	Part Markings ..............................................................................................................	457
C.3	Kits .............................................................................................................................	458
C.4	Support Information .....................................................................................................	458
D	Package Information ............................................................................................	459

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Table of Contents

List of Figures
Figure 1-1.	Stellaris® LM3S1332 Microcontroller High-Level Block Diagram .............................	32
Figure 2-1.	CPU Block Diagram .............................................................................................	40
Figure 2-2.	TPIU Block Diagram ............................................................................................	41
Figure 5-1.	JTAG Module Block Diagram ................................................................................	51
Figure 5-2.	Test Access Port State Machine ...........................................................................	54
Figure 5-3.	IDCODE Register Format .....................................................................................	60
Figure 5-4.	BYPASS Register Format ....................................................................................	60
Figure 5-5.	Boundary Scan Register Format ...........................................................................	61
Figure 6-1.	Basic RST Configuration ......................................................................................	63
Figure 6-2.	External Circuitry to Extend Power-On Reset ........................................................	64
Figure 6-3.	Reset Circuit Controlled by Switch ........................................................................	64
Figure 6-4.	Power Architecture ..............................................................................................	66
Figure 6-5.	Main Clock Tree ..................................................................................................	68
Figure 7-1.	Hibernation Module Block Diagram .....................................................................	125
Figure 7-2.	Clock Source Using Crystal ................................................................................	126
Figure 7-3.	Clock Source Using Dedicated Oscillator .............................................................	127
Figure 8-1.	Flash Block Diagram ..........................................................................................	144
Figure 9-1.	GPIO Port Block Diagram ...................................................................................	170
Figure 9-2.	GPIODATA Write Example .................................................................................	171
Figure 9-3.	GPIODATA Read Example .................................................................................	171
Figure 10-1.	GPTM Module Block Diagram ............................................................................	212
Figure 10-2.	16-Bit Input Edge Count Mode Example ..............................................................	216
Figure 10-3.	16-Bit Input Edge Time Mode Example ...............................................................	217
Figure 10-4.	16-Bit PWM Mode Example ................................................................................	218
Figure 11-1.	WDT Module Block Diagram ..............................................................................	248
Figure 12-1.	ADC Module Block Diagram ...............................................................................	272
Figure 12-2.	Differential Sampling Range, VIN_ODD = 1.5 V ......................................................	275
Figure 12-3.	Differential Sampling Range, VIN_ODD = 0.75 V ....................................................	276
Figure 12-4.	Differential Sampling Range, VIN_ODD = 2.25 V ....................................................	276
Figure 12-5.	Internal Temperature Sensor Characteristic .........................................................	277
Figure 13-1.	UART Module Block Diagram .............................................................................	308
Figure 13-2.	UART Character Frame .....................................................................................	309
Figure 13-3.	IrDA Data Modulation .........................................................................................	311
Figure 14-1.	SSI Module Block Diagram .................................................................................	348
Figure 14-2.	TI Synchronous Serial Frame Format (Single Transfer) ........................................	351
Figure 14-3.	TI Synchronous Serial Frame Format (Continuous Transfer) ................................	351
Figure 14-4.	Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ..........................	352
Figure 14-5.	Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ..................	352
Figure 14-6.	Freescale SPI Frame Format with SPO=0 and SPH=1 .........................................	353
Figure 14-7.	Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ...............	354
Figure 14-8.	Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........	354
Figure 14-9.	Freescale SPI Frame Format with SPO=1 and SPH=1 .........................................	355
Figure 14-10.	MICROWIRE Frame Format (Single Frame) ........................................................	356
Figure 14-11.	MICROWIRE Frame Format (Continuous Transfer) .............................................	357
Figure 14-12.	MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............	357

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Figure 15-1.	Analog Comparator Module Block Diagram .........................................................	386
Figure 15-2.	Structure of Comparator Unit ..............................................................................	387
Figure 15-3.	Comparator Internal Reference Structure ............................................................	387
Figure 16-1.	100-Pin LQFP Package Pin Diagram ..................................................................	397
Figure 16-2.	108-Ball BGA Package Pin Diagram (Top View) ...................................................	398
Figure 19-1.	Load Conditions ................................................................................................	429
Figure 19-2.	JTAG Test Clock Input Timing .............................................................................	431
Figure 19-3.	JTAG Test Access Port (TAP) Timing ..................................................................	432
Figure 19-4.	JTAG TRST Timing ............................................................................................	432
Figure 19-5.	External Reset Timing (RST) ..............................................................................	433
Figure 19-6.	Power-On Reset Timing .....................................................................................	433
Figure 19-7.	Brown-Out Reset Timing ....................................................................................	433
Figure 19-8.	Software Reset Timing .......................................................................................	433
Figure 19-9.	Watchdog Reset Timing .....................................................................................	434
Figure 19-10.	Hibernation Module Timing .................................................................................	435
Figure 19-11.	ADC Input Equivalency Diagram .........................................................................	436
Figure 19-12.	SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
	Measurement ....................................................................................................	437
Figure 19-13.	SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer .................	437
Figure 19-14.	SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .....................................	438
Figure D-1.	100-Pin LQFP Package ......................................................................................	459
Figure D-2.	108-Ball BGA Package ......................................................................................	461

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Table of Contents
List of Tables
Table 1.	Revision History ..................................................................................................	17
Table 2.	Documentation Conventions ................................................................................	22
Table 3-1.	Memory Map .......................................................................................................	45
Table 4-1.	Exception Types ..................................................................................................	47
Table 4-2.	Interrupts ............................................................................................................	48
Table 5-1.	JTAG Port Pins Reset State .................................................................................	52
Table 5-2.	JTAG Instruction Register Commands ...................................................................	57
Table 6-1.	Clock Source Options ..........................................................................................	67
Table 6-2.	Possible System Clock Frequencies Using the SYSDIV Field .................................	69
Table 6-3.	Examples of Possible System Clock Frequencies Using the SYSDIV2 Field ............	69
Table 6-4.	System Control Register Map ...............................................................................	73
Table 6-5.	RCC2 Fields that Override RCC fields ..................................................................	88
Table 7-1.	Hibernation Module Register Map .......................................................................	130
Table 8-1.	Flash Protection Policy Combinations .................................................................	145
Table 8-2.	User-Programmable Flash Memory Resident Registers .......................................	147
Table 8-3.	Flash Register Map ............................................................................................	148
Table 9-1.	GPIO Pad Configuration Examples .....................................................................	173
Table 9-2.	GPIO Interrupt Configuration Example ................................................................	173
Table 9-3.	GPIO Register Map ...........................................................................................	175
Table 10-1.	Available CCP Pins ............................................................................................	212
Table 10-2.	16-Bit Timer With Prescaler Configurations .........................................................	215
Table 10-3.	Timers Register Map ..........................................................................................	221
Table 11-1.	Watchdog Timer Register Map ............................................................................	249
Table 12-1.	Samples and FIFO Depth of Sequencers ............................................................	272
Table 12-2.	Differential Sampling Pairs .................................................................................	274
Table 12-3.	ADC Register Map .............................................................................................	278
Table 13-1.	UART Register Map ...........................................................................................	313
Table 14-1.	SSI Register Map ..............................................................................................	358
Table 15-1.	Internal Reference Voltage and ACREFCTL Field Values .....................................	387
Table 15-2.	Analog Comparators Register Map .....................................................................	389
Table 17-1.	Signals by Pin Number .......................................................................................	399
Table 17-2.	Signals by Signal Name .....................................................................................	403
Table 17-3.	Signals by Function, Except for GPIO .................................................................	406
Table 17-4.	GPIO Pins and Alternate Functions .....................................................................	409
Table 17-5.	Signals by Pin Number .......................................................................................	410
Table 17-6.	Signals by Signal Name .....................................................................................	415
Table 17-7.	Signals by Function, Except for GPIO .................................................................	418
Table 17-8.	GPIO Pins and Alternate Functions .....................................................................	421
Table 17-9.	Connections for Unused Signals (100-pin LQFP) .................................................	423
Table 17-10.	Connections for Unused Signals, 108-pin BGA ....................................................	423
Table 18-1.	Temperature Characteristics ...............................................................................	424
Table 18-2.	Thermal Characteristics .....................................................................................	424
Table 18-3.	ESD Absolute Maximum Ratings ........................................................................	424
Table 19-1.	Maximum Ratings ..............................................................................................	425
Table 19-2.	Recommended DC Operating Conditions ............................................................	425
Table 19-3.	LDO Regulator Characteristics ...........................................................................	426
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Table 19-4.	GPIO Module DC Characteristics ........................................................................	426
Table 19-5.	Detailed Power Specifications ............................................................................	427
Table 19-6.	Flash Memory Characteristics ............................................................................	428
Table 19-7.	Hibernation Module DC Characteristics ...............................................................	428
Table 19-8.	Phase Locked Loop (PLL) Characteristics ...........................................................	429
Table 19-9.	Actual PLL Frequency ........................................................................................	429
Table 19-10.	Clock Characteristics .........................................................................................	429
Table 19-11.	Crystal Characteristics .......................................................................................	430
Table 19-12.	System Clock Characteristics with ADC Operation ...............................................	430
Table 19-13.	JTAG Characteristics .........................................................................................	430
Table 19-14.	Reset Characteristics .........................................................................................	432
Table 19-15.	Sleep Modes AC Characteristics .........................................................................	434
Table 19-16.	Hibernation Module AC Characteristics ...............................................................	434
Table 19-17.	GPIO Characteristics .........................................................................................	435
Table 19-18.	ADC Characteristics ...........................................................................................	435
Table 19-19.	ADC Module Internal Reference Characteristics ..................................................	436
Table 19-20.	SSI Characteristics ............................................................................................	436
Table 19-21.	Analog Comparator Characteristics .....................................................................	438
Table 19-22.	Analog Comparator Voltage Reference Characteristics ........................................	438
Table C-1.	Part Ordering Information ...................................................................................	457

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Table of Contents

List of Registers
System Control ..............................................................................................................................		62
Register 1:	Device Identification 0 (DID0), offset 0x000 .......................................................................	75
Register 2:	Brown-Out Reset Control (PBORCTL), offset 0x030 ..........................................................	77
Register 3:	LDO Power Control (LDOPCTL), offset 0x034 ...................................................................	78
Register 4:	Raw Interrupt Status (RIS), offset 0x050 ...........................................................................	79
Register 5:	Interrupt Mask Control (IMC), offset 0x054 ........................................................................	80
Register 6:	Masked Interrupt Status and Clear (MISC), offset 0x058 ....................................................	81
Register 7:	Reset Cause (RESC), offset 0x05C ..................................................................................	82
Register 8:	Run-Mode Clock Configuration (RCC), offset 0x060 ..........................................................	83
Register 9:	XTAL to PLL Translation (PLLCFG), offset 0x064 ..............................................................	87
Register 10:	Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ......................................................	88
Register 11:	Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ..........................................	90
Register 12:	Device Identification 1 (DID1), offset 0x004 .......................................................................	91
Register 13:	Device Capabilities 0 (DC0), offset 0x008 .........................................................................	93
Register 14:	Device Capabilities 1 (DC1), offset 0x010 .........................................................................	94
Register 15:	Device Capabilities 2 (DC2), offset 0x014 .........................................................................	96
Register 16:	Device Capabilities 3 (DC3), offset 0x018 .........................................................................	98
Register 17:	Device Capabilities 4 (DC4), offset 0x01C .......................................................................	100
Register 18:	Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ...................................	102
Register 19:	Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................	104
Register 20:	Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 .......................	106
Register 21:	Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ...................................	108
Register 22:	Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................	110
Register 23:	Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 .......................	112
Register 24:	Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ...................................	114
Register 25:	Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................	116
Register 26:	Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 .......................	118
Register 27:	Software Reset Control 0 (SRCR0), offset 0x040 .............................................................	120
Register 28:	Software Reset Control 1 (SRCR1), offset 0x044 .............................................................	121
Register 29:	Software Reset Control 2 (SRCR2), offset 0x048 .............................................................	123
Hibernation Module .....................................................................................................................		124
Register 1:	Hibernation RTC Counter (HIBRTCC), offset 0x000 .........................................................	132
Register 2:	Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 .......................................................	133
Register 3:	Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 .......................................................	134
Register 4:	Hibernation RTC Load (HIBRTCLD), offset 0x00C ...........................................................	135
Register 5:	Hibernation Control (HIBCTL), offset 0x010 .....................................................................	136
Register 6:	Hibernation Interrupt Mask (HIBIM), offset 0x014 .............................................................	138
Register 7:	Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 ..................................................	139
Register 8:	Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................	140
Register 9:	Hibernation Interrupt Clear (HIBIC), offset 0x020 .............................................................	141
Register 10:	Hibernation RTC Trim (HIBRTCT), offset 0x024 ...............................................................	142
Register 11:	Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................	143
Internal Memory ...........................................................................................................................		144
Register 1:	Flash Memory Address (FMA), offset 0x000 ....................................................................	149
Register 2:	Flash Memory Data (FMD), offset 0x004 .........................................................................	150

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Register 3:	Flash Memory Control (FMC), offset 0x008 .....................................................................	151
Register 4:	Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................	153
Register 5:	Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................	154
Register 6:	Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 .....................	155
Register 7:	USec Reload (USECRL), offset 0x140 ............................................................................	157
Register 8:	Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ...................	158
Register 9:	Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ...............	159
Register 10:	User Debug (USER_DBG), offset 0x1D0 .........................................................................	160
Register 11:	User Register 0 (USER_REG0), offset 0x1E0 ..................................................................	161
Register 12:	User Register 1 (USER_REG1), offset 0x1E4 ..................................................................	162
Register 13:	Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 ....................................	163
Register 14:	Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 ....................................	164
Register 15:	Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ...................................	165
Register 16:	Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ...............................	166
Register 17:	Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ...............................	167
Register 18:	Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ...............................	168
General-Purpose Input/Outputs (GPIOs) ...................................................................................		169
Register 1:	GPIO Data (GPIODATA), offset 0x000 ............................................................................	177
Register 2:	GPIO Direction (GPIODIR), offset 0x400 .........................................................................	178
Register 3:	GPIO Interrupt Sense (GPIOIS), offset 0x404 ..................................................................	179
Register 4:	GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................	180
Register 5:	GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................	181
Register 6:	GPIO Interrupt Mask (GPIOIM), offset 0x410 ...................................................................	182
Register 7:	GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................	183
Register 8:	GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ...................................................	184
Register 9:	GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................	185
Register 10:	GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................	186
Register 11:	GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................	188
Register 12:	GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................	189
Register 13:	GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................	190
Register 14:	GPIO Open Drain Select (GPIOODR), offset 0x50C .........................................................	191
Register 15:	GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................	192
Register 16:	GPIO Pull-Down Select (GPIOPDR), offset 0x514 ...........................................................	193
Register 17:	GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................	194
Register 18:	GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................	195
Register 19:	GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................	196
Register 20:	GPIO Commit (GPIOCR), offset 0x524 ............................................................................	197
Register 21:	GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 .......................................	199
Register 22:	GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 .......................................	200
Register 23:	GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 .......................................	201
Register 24:	GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ......................................	202
Register 25:	GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 .......................................	203
Register 26:	GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 .......................................	204
Register 27:	GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 .......................................	205
Register 28:	GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ......................................	206
Register 29:	GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 ..........................................	207
Register 30:	GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 ..........................................	208
Register 31:	GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 ..........................................	209
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Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC .........................................

210

General-Purpose Timers .............................................................................................................		211
Register 1:	GPTM Configuration (GPTMCFG), offset 0x000 ..............................................................	223
Register 2:	GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................	224
Register 3:	GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................	226
Register 4:	GPTM Control (GPTMCTL), offset 0x00C ........................................................................	228
Register 5:	GPTM Interrupt Mask (GPTMIMR), offset 0x018 ..............................................................	231
Register 6:	GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .....................................................	233
Register 7:	GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................	234
Register 8:	GPTM Interrupt Clear (GPTMICR), offset 0x024 ..............................................................	235
Register 9:	GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 .................................................	237
Register 10:	GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................	238
Register 11:	GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ...................................................	239
Register 12:	GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 ..................................................	240
Register 13:	GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................	241
Register 14:	GPTM TimerB Prescale (GPTMTBPR), offset 0x03C .......................................................	242
Register 15:	GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ...........................................	243
Register 16:	GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ...........................................	244
Register 17:	GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................	245
Register 18:	GPTM TimerB (GPTMTBR), offset 0x04C .......................................................................	246

Watchdog Timer ...........................................................................................................................		247
Register 1:	Watchdog Load (WDTLOAD), offset 0x000 ......................................................................	251
Register 2:	Watchdog Value (WDTVALUE), offset 0x004 ...................................................................	252
Register 3:	Watchdog Control (WDTCTL), offset 0x008 .....................................................................	253
Register 4:	Watchdog Interrupt Clear (WDTICR), offset 0x00C ..........................................................	254
Register 5:	Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ..................................................	255
Register 6:	Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 .............................................	256
Register 7:	Watchdog Test (WDTTEST), offset 0x418 .......................................................................	257
Register 8:	Watchdog Lock (WDTLOCK), offset 0xC00 .....................................................................	258
Register 9:	Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 .................................	259
Register 10:	Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 .................................	260
Register 11:	Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 .................................	261
Register 12:	Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................	262
Register 13:	Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 .................................	263
Register 14:	Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 .................................	264
Register 15:	Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 .................................	265
Register 16:	Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................	266
Register 17:	Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 ....................................	267
Register 18:	Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 ....................................	268
Register 19:	Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 ....................................	269
Register 20:	Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ..................................	270

Analog-to-Digital Converter (ADC) .............................................................................................	271
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 .............................................	280
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ...........................................................	281
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 .....................................................................	282
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C ..................................................	283
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................	285
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 .................................................	286
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Register 7:	ADC Underflow Status (ADCUSTAT), offset 0x018 ...........................................................	289
Register 8:	ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 .............................................	290
Register 9:	ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 .................................	292
Register 10:	ADC Sample Averaging Control (ADCSAC), offset 0x030 .................................................	293
Register 11:	ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ...............	294
Register 12:	ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................	296
Register 13:	ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................	299
Register 14:	ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................	299
Register 15:	ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................	299
Register 16:	ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ...............................	299
Register 17:	ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C .............................	300
Register 18:	ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C .............................	300
Register 19:	ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................	300
Register 20:	ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................	300
Register 21:	ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ...............	301
Register 22:	ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ...............	301
Register 23:	ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................	302
Register 24:	ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................	302
Register 25:	ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ...............	304
Register 26:	ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................	305
Register 27:	ADC Test Mode Loopback (ADCTMLB), offset 0x100 .......................................................	306
Universal Asynchronous Receivers/Transmitters (UARTs) .....................................................		307
Register 1:	UART Data (UARTDR), offset 0x000 ...............................................................................	315
Register 2:	UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ...........................	317
Register 3:	UART Flag (UARTFR), offset 0x018 ................................................................................	319
Register 4:	UART IrDA Low-Power Register (UARTILPR), offset 0x020 .............................................	321
Register 5:	UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................	322
Register 6:	UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 .......................................	323
Register 7:	UART Line Control (UARTLCRH), offset 0x02C ...............................................................	324
Register 8:	UART Control (UARTCTL), offset 0x030 .........................................................................	326
Register 9:	UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ...........................................	328
Register 10:	UART Interrupt Mask (UARTIM), offset 0x038 .................................................................	330
Register 11:	UART Raw Interrupt Status (UARTRIS), offset 0x03C ......................................................	332
Register 12:	UART Masked Interrupt Status (UARTMIS), offset 0x040 .................................................	333
Register 13:	UART Interrupt Clear (UARTICR), offset 0x044 ...............................................................	334
Register 14:	UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 .....................................	336
Register 15:	UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 .....................................	337
Register 16:	UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 .....................................	338
Register 17:	UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC .....................................	339
Register 18:	UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ......................................	340
Register 19:	UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ......................................	341
Register 20:	UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ......................................	342
Register 21:	UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC .....................................	343
Register 22:	UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................	344
Register 23:	UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................	345
Register 24:	UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................	346
Register 25:	UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................	347

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Synchronous Serial Interface (SSI) ............................................................................................		348
Register 1:	SSI Control 0 (SSICR0), offset 0x000 ..............................................................................	360
Register 2:	SSI Control 1 (SSICR1), offset 0x004 ..............................................................................	362
Register 3:	SSI Data (SSIDR), offset 0x008 ......................................................................................	364
Register 4:	SSI Status (SSISR), offset 0x00C ...................................................................................	365
Register 5:	SSI Clock Prescale (SSICPSR), offset 0x010 ..................................................................	367
Register 6:	SSI Interrupt Mask (SSIIM), offset 0x014 .........................................................................	368
Register 7:	SSI Raw Interrupt Status (SSIRIS), offset 0x018 ..............................................................	370
Register 8:	SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................	371
Register 9:	SSI Interrupt Clear (SSIICR), offset 0x020 .......................................................................	372
Register 10:	SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 .............................................	373
Register 11:	SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 .............................................	374
Register 12:	SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 .............................................	375
Register 13:	SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................	376
Register 14:	SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 .............................................	377
Register 15:	SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 .............................................	378
Register 16:	SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 .............................................	379
Register 17:	SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................	380
Register 18:	SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ...............................................	381
Register 19:	SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ...............................................	382
Register 20:	SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ...............................................	383
Register 21:	SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ...............................................	384
Analog Comparators ...................................................................................................................		385
Register 1:	Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ..................................	390
Register 2:	Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 .......................................	391
Register 3:	Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 .........................................	392
Register 4:	Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 .......................	393
Register 5:	Analog Comparator Status 0 (ACSTAT0), offset 0x020 .....................................................	394
Register 6:	Analog Comparator Status 1 (ACSTAT1), offset 0x040 .....................................................	394
Register 7:	Analog Comparator Status 2 (ACSTAT2), offset 0x060 .....................................................	394
Register 8:	Analog Comparator Control 0 (ACCTL0), offset 0x024 .....................................................	395
Register 9:	Analog Comparator Control 1 (ACCTL1), offset 0x044 .....................................................	395
Register 10:	Analog Comparator Control 2 (ACCTL2), offset 0x064 ....................................................	395

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Revision History

The revision history table notes changes made between the indicated revisions of the LM3S1332 data sheet.

Table 1. Revision History

Date	Revision	Description
June 2010	7393	■ Corrected base address for SRAM in architectural overview chapter.
		■ Clarified system clock operation, adding content to “Clock Control” on page 66.
		■ In Signal Tables chapter, added table "Connections for Unused Signals."
		■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
		■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.
		■ Additional minor data sheet clarifications and corrections.
April 2010	7007	■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
		field width to 7 bits.
		■ Removed erroneous text about restoring the Flash Protection registers.
		■ Added note about		signal routing.
			RST
		■ Clarified the function of the TnSTALL bit in the GPTMCTL register.
		■ Additional minor data sheet clarifications and corrections.
January 2010	6712	■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.
		■ Clarified wording on Flash memory access errors.
		■ Added section on Flash interrupts.

■ Changed the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers to be indeterminate.

■ Clarified operation of SSI transmit FIFO.

■ Made these changes to the Operating Characteristics chapter:

– Added storage temperature ratings to "Temperature Characteristics" table

– Added "ESD Absolute Maximum Ratings" table

■ Made these changes to the Electrical Characteristics chapter:

– In "Flash Memory Characteristics" table, corrected Mass erase time

– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)

– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time

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Table 1. Revision History (continued)

Date	Revision	Description
October 2009	6462	■ Deleted MAXADCSPD bit field from DCGC0 register as it is not applicable in Deep-Sleep mode.
		■ Removed erroneous reference to the WRC bit in the Hibernation chapter.
		■ Deletedresetvaluefor16-bitmodefrom GPTMTAILR, GPTMTAMATCHR,and GPTMTAR registers
		because the module resets in 32-bit mode.
		■ Clarified PWM source for ADC triggering.
		■ Made these changes to the Electrical Characteristics chapter:
		– Removed VSIH and VSIL parameters from Operating Conditions table.
		– Added table showing actual PLL frequency depending on input crystal.
		– Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS.
		– Revised ADC electrical specifications to clarify, including reorganizing and adding new data.
		– Changed SSI set up and hold times to be expressed in system clocks, not ns.
July 2009	5920	Corrected ordering numbers.
July 2009	5902	■ Clarified Power-on reset and		pin operation; added new diagrams.
			RST

■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)

registers.

■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.

■ AddedexplanationofresetvaluetoFMPRE0/1/2/3,FMPPE0/1/2/3,USER_DBG,andUSER_REG0/1

registers.

■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.

■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR (Internal voltage reference error) parameter.

■ Additional minor data sheet clarifications and corrections.

April 2009

5367

■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 56).

■Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application of the output divisor.

■Added "GPIO Module DC Characteristics" table (see Table 19-4 on page 426).

■Additional minor data sheet clarifications and corrections.

January 2009

4660

■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.

■Clarification added as to what happens when the SSI in slave mode is required to transmit but there is no data in the TX FIFO.

■Additional minor data sheet clarifications and corrections.

November 2008

4283

■ Revised High-Level Block Diagram.

■Additional minor data sheet clarifications and corrections were made.

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Table 1. Revision History (continued)

Date	Revision	Description
October 2008	4149	■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
		register.
		■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
		Internal Memory chapter. The correct value is 0x0000.0006.
		■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.

August 2008

3447

■ Added note on clearing interrupts to Interrupts chapter.

■Added Power Architecture diagram to System Control chapter.

■Additional minor data sheet clarifications and corrections.

July 2008	3108	■ Additional minor data sheet clarifications and corrections.
May 2008	2972	■ The 108-Ball BGA pin diagram and pin tables had an error. The following signals were erroneously
		indicated as available and have now been changed to a No Connect (NC):
		– Ball C1: Changed PE7 to NC
		– Ball C2: Changed PE6 to NC
		– Ball D2: Changed PE5 to NC
		■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
		the LDO output as the source of VDD25 input.
		■ Additional minor data sheet clarifications and corrections.
April 2008	2881	■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating

Characteristics chapter.

■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of 1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.

■ Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical Characteristics" chapter.

■ The "Hibernation Module DC Electricals"table was added to the "Electrical Characteristics"chapter.

■ The TVDDRISE parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter was changed from a max of 100 to 250.

■ The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical

Characteristics" chapter was changed from 4 to 3.

■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data sheets incorrectly noted it as 30 kHz ± 30%).

■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value.

■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly noted the reset was 0x0 (MOSC).

■ Two figures on clock source were added to the "Hibernation Module":

– Clock Source Using Crystal

– Clock Source Using Dedicated Oscillator

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Revision History

Table 1. Revision History (continued)

Date	Revision Description

■The following notes on battery management were added to the "Hibernation Module" chapter:

–Battery voltage is not measured while in Hibernate mode.

–System level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements.

■A note on high-current applications was added to the GPIO chapter:

For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package.

■A note on Schmitt inputs was added to the GPIO chapter: Pins configured as digital inputs are Schmitt-triggered.

■The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.

■The "Differential Sampling Range" figures in the ADC chapter were clarified.

■Thelastrevisionofthedatasheet(revision2550)introducedtwoerrorsthathavenowbeencorrected:

–The LQFP pin diagrams and pin tables were missing the comparator positive and negative input pins.

–The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.

■Additional minor data sheet clarifications and corrections.

March 2008

2550

Started tracking revision history.

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About This Document

This data sheet provides reference information for the LM3S1332 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core.

Audience

This manual is intended for system software developers, hardware designers, and application developers.

About This Manual

This document is organized into sections that correspond to each major feature.

Related Documents

The following related documents are available on the documentation CD or from the Stellaris® web site at www.ti.com/stellaris:

■ARM® CoreSight Technical Reference Manual

■ARM® Cortex™-M3 Errata

■ARM® Cortex™-M3 Technical Reference Manual

■ARM® v7-M Architecture Application Level Reference Manual

■Stellaris® Graphics Library User's Guide

■Stellaris® Peripheral Driver Library User's Guide

■Stellaris® Errata

The following related documents are also referenced:

■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture

This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers.

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About This Document

Documentation Conventions

This document uses the conventions shown in Table 2 on page 22.

Table 2. Documentation Conventions

Notation Meaning

General Register Notation

REGISTER	APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
	Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
	than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
	registers: SRCR0, SRCR1 , and SRCR2.
bit	A single bit in a register.
bit field	Two or more consecutive and related bits.
offset 0xnnn	A hexadecimal increment to a register's address, relative to that module's base address as specified
	in “Memory Map” on page 45.
Register N	Registers are numbered consecutively throughout the document to aid in referencing them. The
	register number has no meaning to software.
reserved	Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
	0; however, user software should not rely on the value of a reserved bit. To provide software
	compatibility with future products, the value of a reserved bit should be preserved across a
	read-modify-write operation.
yy:xx	The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
	that register.
Register Bit/Field	This value in the register bit diagram indicates whether software running on the controller can
Types	change the value of the bit field.
RC	Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO	Software can read this field. Always write the chip reset value.
R/W	Software can read or write this field.
R/W1C	Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
	register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
	This register type is primarily used for clearing interrupt status bits where the read operation
	provides the interrupt status and the write of the read value clears only the interrupts being reported
	at the time the register was read.
R/W1S	Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
	value in the register.
W1C	Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
	A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
	read of the register returns no meaningful data.
	This register is typically used to clear the corresponding bit in an interrupt register.
WO	Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field	This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0	Bit cleared to 0 on chip reset.
1	Bit set to 1 on chip reset.
-	Nondeterministic.
Pin/Signal Notation
[ ]	Pin alternate function; a pin defaults to the signal without the brackets.
pin	Refers to the physical connection on the package.
signal	Refers to the electrical signal encoding of a pin.

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Table 2. Documentation Conventions (continued)

Notation		Meaning
assert a signal		Change the value of the signal from the logically False state to the logically True state. For active
		High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
		is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and
							SIGNAL
		below).
deassert a signal		Change the value of the signal from the logically True state to the logically False state.
		Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
SIGNAL
		it is active Low. To assert		is to drive it Low; to deassert		is to drive it High.
			SIGNAL		SIGNAL
SIGNAL		Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
		assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.

Numbers

XAn uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on.

0x	Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
	All other numbers within register tables are assumed to be binary. Within conceptual information,
	binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
	without a prefix or suffix.

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Architectural Overview

1Architectural Overview

The Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.

The Stellaris® family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris® LM3S1000 series extends the Stellaris® family with larger on-chip memories, enhanced power management, and expanded I/O and control capabilities.

The LM3S1332 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security.

For applications requiring extreme conservation of power, the LM3S1332 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S1332 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S1332 microcontroller perfectly for battery applications.

In addition, the LM3S1332 microcontroller offers the advantages of ARM's widely available development tools,System-on-Chip(SoC) infrastructureIPapplications,and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S1332 microcontroller is code-compatible to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise needs.

Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See “Ordering and Contact

Information” on page 457 for ordering information for Stellaris® family devices.

1.1Product Features

The LM3S1332 microcontroller includes the following product features:

■32-Bit RISC Performance

–32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications

–System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism

–Thumb®-compatible Thumb-2-only instruction set processor core for high code density

–50-MHz operation

–Hardware-division and single-cycle-multiplication

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–Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling

–30 interrupts with eight priority levels

–Memory protection unit (MPU), providing a privileged mode for protected operating system functionality

–Unaligned data access, enabling data to be efficiently packed into memory

–Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control

■ARM® Cortex™-M3 Processor Core

–Compact core.

–Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications.

–Rapid application execution through Harvard architecture characterized by separate buses for instruction and data.

–Exceptionalinterrupthandling,byimplementingtheregistermanipulationsrequiredforhandling an interrupt in hardware.

–Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining

–Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.

–Migration from the ARM7™ processor family for better performance and power efficiency.

–Full-featured debug solution

•Serial Wire JTAG Debug Port (SWJ-DP)

•Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

•Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling

•Instrumentation Trace Macrocell (ITM) for support of printf style debugging

•Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

–Optimized for single-cycle flash usage

–Three sleep modes with clock gating for low power

–Single-cycle multiply instruction and hardware divide

–Atomic operations

–ARM Thumb2 mixed 16-/32-bit instruction set

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Architectural Overview

–1.25 DMIPS/MHz

■JTAG

–IEEE 1149.1-1990 compatible Test Access Port (TAP) controller

–Four-bit Instruction Register (IR) chain for storing JTAG instructions

–IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST

–ARM additional instructions: APACC, DPACC and ABORT

–Integrated ARM Serial Wire Debug (SWD)

■Hibernation

–System power control using discrete external regulator

–Dedicated pin for waking from an external signal

–Low-battery detection, signaling, and interrupt generation

–32-bit real-time clock (RTC)

–Two 32-bit RTC match registers for timed wake-up and interrupt generation

–Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal

–RTC predivider trim for making fine adjustments to the clock rate

–64 32-bit words of non-volatile memory

–Programmable interrupts for RTC match, external wake, and low battery events

■Internal Memory

–96 KB single-cycle flash

•User-managed flash block protection on a 2-KB block basis

•User-managed flash data programming

•User-defined and managed flash-protection block

–16 KB single-cycle SRAM

■GPIOs

–29-57 GPIOs, depending on configuration

–5-V-tolerant input/outputs

–Programmable control for GPIO interrupts

•Interrupt generation masking

•Edge-triggered on rising, falling, or both

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•Level-sensitive on High or Low values

–Bit masking in both read and write operations through address lines

–Can initiate an ADC sample sequence

–Pins configured as digital inputs are Schmitt-triggered.

–Programmable control for GPIO pad configuration

•Weak pull-up or pull-down resistors

•2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications

•Slew rate control for the 8-mA drive

•Open drain enables

•Digital input enables

■General-Purpose Timers

–Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently:

•As a single 32-bit timer

•As one 32-bit Real-Time Clock (RTC) to event capture

•For Pulse Width Modulation (PWM)

•To trigger analog-to-digital conversions

–32-bit Timer modes

•Programmable one-shot timer

•Programmable periodic timer

•Real-Time Clock when using an external 32.768-KHz clock as the input

•User-enabled stalling when the controller asserts CPU Halt flag during debug

•ADC event trigger

–16-bit Timer modes

•General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)

•Programmable one-shot timer

•Programmable periodic timer

•User-enabled stalling when the controller asserts CPU Halt flag during debug

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Architectural Overview

•ADC event trigger

–16-bit Input Capture modes

•Input edge count capture

•Input edge time capture

–16-bit PWM mode

•Simple PWM mode with software-programmable output inversion of the PWM signal

■ARM FiRM-compliant Watchdog Timer

–32-bit down counter with a programmable load register

–Separate watchdog clock with an enable

–Programmable interrupt generation logic with interrupt masking

–Lock register protection from runaway software

–Reset generation logic with an enable/disable

–User-enabled stalling when the controller asserts the CPU Halt flag during debug

■ADC

–Three analog input channels

–Single-ended and differential-input configurations

–On-chip internal temperature sensor

–Sample rate of 250 thousand samples/second

–Flexible, configurable analog-to-digital conversion

–Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs

–Flexible trigger control

•Controller (software)

•Timers

•Analog Comparators

•GPIO

–Hardware averaging of up to 64 samples for improved accuracy

–Converter uses an internal 3-V reference

–Power and ground for the analog circuitry is separate from the digital power and ground

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■UART

–Two fully programmable 16C550-type UARTs with IrDA support

–Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading

–Programmable baud-rate generator allowing speeds up to 3.125 Mbps

–Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface

–FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

–Standard asynchronous communication bits for start, stop, and parity

–False-start bit detection

–Line-break generation and detection

–Fully programmable serial interface characteristics

•5, 6, 7, or 8 data bits

•Even, odd, stick, or no-parity bit generation/detection

•1 or 2 stop bit generation

–IrDA serial-IR (SIR) encoder/decoder providing

•Programmable use of IrDA Serial Infrared (SIR) or UART input/output

•Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex

•Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations

•Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration

■Synchronous Serial Interface (SSI)

–Master or slave operation

–Programmable clock bit rate and prescale

–Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

–Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces

–Programmable data frame size from 4 to 16 bits

–Internal loopback test mode for diagnostic/debug testing

■Analog Comparators

–Three independent integrated analog comparators

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Architectural Overview

–Configurable for output to drive an output pin, generate an interrupt, or initiate an ADC sample sequence

–Compare external pin input to external pin input or to internal programmable voltage reference

–Compare a test voltage against any one of these voltages

•An individual external reference voltage

•A shared single external reference voltage

•A shared internal reference voltage

■Power

–On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V

–Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits

–Low-power options on controller: Sleep and Deep-sleep modes

–Low-power options for peripherals: software controls shutdown of individual peripherals

–3.3-V supply brown-out detection and reporting via interrupt or reset

■Flexible Reset Sources

–Power-on reset (POR)

–Reset pin assertion

–Brown-out (BOR) detector alerts to system power drops

–Software reset

–Watchdog timer reset

–Internal low drop-out (LDO) regulator output goes unregulated

■Industrial and extended temperature 100-pin RoHS-compliant LQFP package

■Industrial-range 108-ball RoHS-compliant BGA package

1.2Target Applications

■Remote monitoring

■Electronic point-of-sale (POS) machines

■Test and measurement equipment

■Network appliances and switches

■Factory automation

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