Texas instruments STELLARIS LM3S1165 DATA SHEET

TEXAS INSTRUMENTS-PRODUCTION DATA

Stellaris® LM3S1165 Microcontroller

DATA SHEET

DS-LM3S1165-7787	Copyright © 2007-2010 Texas Instruments
	Incorporated

Copyright

Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Pleasebe awarethatan importantnoticeconcerningavailability, standardwarranty, and use in criticalapplicationsof TexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated

108 Wild Basin, Suite 350 Austin, TX 78746

http://www.ti.com/stellaris http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

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Table of Contents
Revision History .............................................................................................................................		23
About This Document ....................................................................................................................		27
Audience ..............................................................................................................................................		27
About This Manual ................................................................................................................................		27
Related Documents ...............................................................................................................................		27
Documentation Conventions ..................................................................................................................		28
1	Architectural Overview ..........................................................................................	30
1.1	Product Features ..........................................................................................................	30
1.2	Target Applications ........................................................................................................	38
1.3	High-Level Block Diagram .............................................................................................	38
1.4	Functional Overview ......................................................................................................	40
1.4.1	ARM Cortex™-M3 .........................................................................................................	40
1.4.2	Motor Control Peripherals ..............................................................................................	41
1.4.3	Analog Peripherals ........................................................................................................	41
1.4.4	Serial Communications Peripherals ................................................................................	42
1.4.5	System Peripherals .......................................................................................................	43
1.4.6	Memory Peripherals ......................................................................................................	44
1.4.7	Additional Features .......................................................................................................	45
1.4.8	Hardware Details ..........................................................................................................	45
2	The Cortex-M3 Processor ......................................................................................	46
2.1	Block Diagram ..............................................................................................................	47
2.2	Overview ......................................................................................................................	48
2.2.1	System-Level Interface ..................................................................................................	48
2.2.2	Integrated Configurable Debug ......................................................................................	48
2.2.3	Trace Port Interface Unit (TPIU) .....................................................................................	49
2.2.4	Cortex-M3 System Component Details ...........................................................................	49
2.3	Programming Model ......................................................................................................	50
2.3.1	Processor Mode and Privilege Levels for Software Execution ...........................................	50
2.3.2	Stacks ..........................................................................................................................	50
2.3.3	Register Map ................................................................................................................	51
2.3.4	Register Descriptions ....................................................................................................	52
2.3.5	Exceptions and Interrupts ..............................................................................................	65
2.3.6	Data Types ...................................................................................................................	65
2.4	Memory Model ..............................................................................................................	65
2.4.1	Memory Regions, Types and Attributes ...........................................................................	67
2.4.2	Memory System Ordering of Memory Accesses ..............................................................	67
2.4.3	Behavior of Memory Accesses .......................................................................................	67
2.4.4	Software Ordering of Memory Accesses .........................................................................	68
2.4.5	Bit-Banding ...................................................................................................................	69
2.4.6	Data Storage ................................................................................................................	71
2.4.7	Synchronization Primitives .............................................................................................	72
2.5	Exception Model ...........................................................................................................	73
2.5.1	Exception States ...........................................................................................................	73
2.5.2	Exception Types ............................................................................................................	74
2.5.3	Exception Handlers .......................................................................................................	77
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2.5.4	Vector Table ..................................................................................................................	77
2.5.5	Exception Priorities .......................................................................................................	78
2.5.6	Interrupt Priority Grouping ..............................................................................................	79
2.5.7	Exception Entry and Return ...........................................................................................	79
2.6	Fault Handling ..............................................................................................................	81
2.6.1	Fault Types ...................................................................................................................	82
2.6.2	Fault Escalation and Hard Faults ....................................................................................	82
2.6.3	Fault Status Registers and Fault Address Registers ........................................................	83
2.6.4	Lockup .........................................................................................................................	83
2.7	Power Management ......................................................................................................	83
2.7.1	Entering Sleep Modes ...................................................................................................	84
2.7.2	Wake Up from Sleep Mode ............................................................................................	84
2.8	Instruction Set Summary ...............................................................................................	85
3	Cortex-M3 Peripherals ...........................................................................................	88
3.1	Functional Description ...................................................................................................	88
3.1.1	System Timer (SysTick) .................................................................................................	88
3.1.2	Nested Vectored Interrupt Controller (NVIC) ....................................................................	89
3.1.3	System Control Block (SCB) ..........................................................................................	91
3.1.4	Memory Protection Unit (MPU) .......................................................................................	91
3.2	Register Map ................................................................................................................	96
3.3	System Timer (SysTick) Register Descriptions ................................................................	98
3.4	NVIC Register Descriptions ..........................................................................................	102
3.5	System Control Block (SCB) Register Descriptions ........................................................	115
3.6	Memory Protection Unit (MPU) Register Descriptions ....................................................	144
4	JTAG Interface ......................................................................................................	154
4.1	Block Diagram ............................................................................................................	155
4.2	Functional Description .................................................................................................	155
4.2.1	JTAG Interface Pins .....................................................................................................	155
4.2.2	JTAG TAP Controller ...................................................................................................	157
4.2.3	Shift Registers ............................................................................................................	158
4.2.4	Operational Considerations ..........................................................................................	158
4.3	Initialization and Configuration .....................................................................................	161
4.4	Register Descriptions ..................................................................................................	161
4.4.1	Instruction Register (IR) ...............................................................................................	161
4.4.2	Data Registers ............................................................................................................	163
5	System Control .....................................................................................................	166
5.1	Functional Description .................................................................................................	166
5.1.1	Device Identification ....................................................................................................	166
5.1.2	Reset Control ..............................................................................................................	166
5.1.3	Power Control .............................................................................................................	169
5.1.4	Clock Control ..............................................................................................................	170
5.1.5	System Control ...........................................................................................................	176
5.2	Initialization and Configuration .....................................................................................	177
5.3	Register Map ..............................................................................................................	177
5.4	Register Descriptions ..................................................................................................	179
6	Hibernation Module ..............................................................................................	232
6.1	Block Diagram ............................................................................................................	233

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6.2	Functional Description .................................................................................................	233
6.2.1	Register Access Timing ...............................................................................................	233
6.2.2	Clock Source ..............................................................................................................	234
6.2.3	Battery Management ...................................................................................................	235
6.2.4	Real-Time Clock ..........................................................................................................	236
6.2.5	Non-Volatile Memory ...................................................................................................	236
6.2.6	Power Control .............................................................................................................	236
6.2.7	Initiating Hibernate ......................................................................................................	237
6.2.8	Interrupts and Status ...................................................................................................	237
6.3	Initialization and Configuration .....................................................................................	237
6.3.1	Initialization .................................................................................................................	238
6.3.2	RTC Match Functionality (No Hibernation) ....................................................................	238
6.3.3	RTC Match/Wake-Up from Hibernation .........................................................................	238
6.3.4	External Wake-Up from Hibernation ..............................................................................	238
6.3.5	RTC/External Wake-Up from Hibernation ......................................................................	239
6.4	Register Map ..............................................................................................................	239
6.5	Register Descriptions ..................................................................................................	239
7	Internal Memory ...................................................................................................	252
7.1	Block Diagram ............................................................................................................	252
7.2	Functional Description .................................................................................................	252
7.2.1	SRAM Memory ............................................................................................................	252
7.2.2	Flash Memory .............................................................................................................	253
7.3	Flash Memory Initialization and Configuration ...............................................................	254
7.3.1	Flash Programming .....................................................................................................	254
7.3.2	Nonvolatile Register Programming ...............................................................................	255
7.4	Register Map ..............................................................................................................	256
7.5	Flash Register Descriptions (Flash Control Offset) .........................................................	257
7.6	Flash Register Descriptions (System Control Offset) ......................................................	265
8	General-Purpose Input/Outputs (GPIOs) ...........................................................	278
8.1	Functional Description .................................................................................................	278
8.1.1	Data Control ...............................................................................................................	279
8.1.2	Interrupt Control ..........................................................................................................	280
8.1.3	Mode Control ..............................................................................................................	281
8.1.4	Commit Control ...........................................................................................................	281
8.1.5	Pad Control .................................................................................................................	281
8.1.6	Identification ...............................................................................................................	282
8.2	Initialization and Configuration .....................................................................................	282
8.3	Register Map ..............................................................................................................	283
8.4	Register Descriptions ..................................................................................................	285
9	General-Purpose Timers ......................................................................................	320
9.1	Block Diagram ............................................................................................................	321
9.2	Functional Description .................................................................................................	322
9.2.1	GPTM Reset Conditions ..............................................................................................	322
9.2.2	32-Bit Timer Operating Modes ......................................................................................	322
9.2.3	16-Bit Timer Operating Modes ......................................................................................	323
9.3	Initialization and Configuration .....................................................................................	327
9.3.1	32-Bit One-Shot/Periodic Timer Mode ...........................................................................	327
9.3.2	32-Bit Real-Time Clock (RTC) Mode .............................................................................	328
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9.3.3	16-Bit One-Shot/Periodic Timer Mode ...........................................................................	328
9.3.4	16-Bit Input Edge Count Mode .....................................................................................	329
9.3.5	16-Bit Input Edge Timing Mode ....................................................................................	329
9.3.6	16-Bit PWM Mode .......................................................................................................	330
9.4	Register Map ..............................................................................................................	330
9.5	Register Descriptions ..................................................................................................	331
10	Watchdog Timer ...................................................................................................	356
10.1	Block Diagram ............................................................................................................	357
10.2	Functional Description .................................................................................................	357
10.3	Initialization and Configuration .....................................................................................	358
10.4	Register Map ..............................................................................................................	358
10.5	Register Descriptions ..................................................................................................	359
11	Analog-to-Digital Converter (ADC) .....................................................................	380
11.1	Block Diagram ............................................................................................................	380
11.2	Functional Description .................................................................................................	381
11.2.1	Sample Sequencers ....................................................................................................	381
11.2.2	Module Control ............................................................................................................	382
11.2.3	Hardware Sample Averaging Circuit .............................................................................	383
11.2.4	Analog-to-Digital Converter ..........................................................................................	383
11.2.5	Differential Sampling ...................................................................................................	383
11.2.6	Test Modes .................................................................................................................	385
11.2.7	Internal Temperature Sensor ........................................................................................	386
11.3	Initialization and Configuration .....................................................................................	386
11.3.1	Module Initialization .....................................................................................................	386
11.3.2	Sample Sequencer Configuration .................................................................................	387
11.4	Register Map ..............................................................................................................	387
11.5	Register Descriptions ..................................................................................................	388
12	Universal Asynchronous Receivers/Transmitters (UARTs) .............................	417
12.1	Block Diagram ............................................................................................................	418
12.2	Functional Description .................................................................................................	418
12.2.1	Transmit/Receive Logic ...............................................................................................	418
12.2.2	Baud-Rate Generation .................................................................................................	419
12.2.3	Data Transmission ......................................................................................................	420
12.2.4	Serial IR (SIR) .............................................................................................................	420
12.2.5	FIFO Operation ...........................................................................................................	421
12.2.6	Interrupts ....................................................................................................................	421
12.2.7	Loopback Operation ....................................................................................................	422
12.2.8	IrDA SIR block ............................................................................................................	422
12.3	Initialization and Configuration .....................................................................................	422
12.4	Register Map ..............................................................................................................	423
12.5	Register Descriptions ..................................................................................................	424
13	Synchronous Serial Interface (SSI) ....................................................................	458
13.1	Block Diagram ............................................................................................................	458
13.2	Functional Description .................................................................................................	459
13.2.1	Bit Rate Generation .....................................................................................................	459
13.2.2	FIFO Operation ...........................................................................................................	459
13.2.3	Interrupts ....................................................................................................................	459

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13.2.4	Frame Formats ...........................................................................................................	460
13.3	Initialization and Configuration .....................................................................................	467
13.4	Register Map ..............................................................................................................	468
13.5	Register Descriptions ..................................................................................................	469
14	Inter-Integrated Circuit (I2C) Interface ................................................................	495
14.1	Block Diagram ............................................................................................................	496
14.2	Functional Description .................................................................................................	496
14.2.1	I2C Bus Functional Overview ........................................................................................	496
14.2.2	Available Speed Modes ...............................................................................................	498
14.2.3	Interrupts ....................................................................................................................	499
14.2.4	Loopback Operation ....................................................................................................	500
14.2.5	Command Sequence Flow Charts ................................................................................	500
14.3	Initialization and Configuration .....................................................................................	507
14.4	Register Map ..............................................................................................................	508
14.5	Register Descriptions (I2C Master) ...............................................................................	509
14.6	Register Descriptions (I2C Slave) .................................................................................	522
15	Analog Comparator ..............................................................................................	531
15.1	Block Diagram ............................................................................................................	531
15.2	Functional Description .................................................................................................	531
15.2.1	Internal Reference Programming ..................................................................................	532
15.3	Initialization and Configuration .....................................................................................	533
15.4	Register Map ..............................................................................................................	533
15.5	Register Descriptions ..................................................................................................	534
16	Pulse Width Modulator (PWM) ............................................................................	542
16.1	Block Diagram ............................................................................................................	543
16.2	Functional Description .................................................................................................	544
16.2.1	PWM Timer .................................................................................................................	544
16.2.2	PWM Comparators ......................................................................................................	544
16.2.3	PWM Signal Generator ................................................................................................	545
16.2.4	Dead-Band Generator .................................................................................................	546
16.2.5	Interrupt/ADC-Trigger Selector .....................................................................................	546
16.2.6	Synchronization Methods ............................................................................................	547
16.2.7	Fault Conditions ..........................................................................................................	547
16.2.8	Output Control Block ...................................................................................................	547
16.3	Initialization and Configuration .....................................................................................	547
16.4	Register Map ..............................................................................................................	548
16.5	Register Descriptions ..................................................................................................	550
17	Pin Diagram ..........................................................................................................	580
18	Signal Tables ........................................................................................................	582
18.1	100-Pin LQFP Package Pin Tables ...............................................................................	582
18.2	108-Pin BGA Package Pin Tables ................................................................................	594
18.3	Connections for Unused Signals ...................................................................................	606
19	Operating Characteristics ...................................................................................	608
20	Electrical Characteristics ....................................................................................	609
20.1	DC Characteristics ......................................................................................................	609
20.1.1	Maximum Ratings .......................................................................................................	609

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20.1.2	Recommended DC Operating Conditions ......................................................................	609
20.1.3	On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................	610
20.1.4	GPIO Module Characteristics .......................................................................................	610
20.1.5	Power Specifications ...................................................................................................	610
20.1.6	Flash Memory Characteristics ......................................................................................	612
20.1.7	Hibernation .................................................................................................................	612
20.2	AC Characteristics .......................................................................................................	612
20.2.1	Load Conditions ..........................................................................................................	612
20.2.2	Clocks ........................................................................................................................	613
20.2.3	JTAG and Boundary Scan ............................................................................................	614
20.2.4	Reset .........................................................................................................................	616
20.2.5	Sleep Modes ...............................................................................................................	618
20.2.6	Hibernation Module .....................................................................................................	618
20.2.7	General-Purpose I/O (GPIO) ........................................................................................	619
20.2.8	Analog-to-Digital Converter ..........................................................................................	619
20.2.9	Synchronous Serial Interface (SSI) ...............................................................................	620
20.2.10	Inter-Integrated Circuit (I2C) Interface ...........................................................................	622
20.2.11	Analog Comparator .....................................................................................................	623
A	Serial Flash Loader ..............................................................................................	624
A.1	Serial Flash Loader .....................................................................................................	624
A.2	Interfaces ...................................................................................................................	624
A.2.1	UART .........................................................................................................................	624
A.2.2	SSI .............................................................................................................................	624
A.3	Packet Handling ..........................................................................................................	625
A.3.1	Packet Format ............................................................................................................	625
A.3.2	Sending Packets .........................................................................................................	625
A.3.3	Receiving Packets .......................................................................................................	625
A.4	Commands .................................................................................................................	626
A.4.1	COMMAND_PING (0X20) ............................................................................................	626
A.4.2	COMMAND_GET_STATUS (0x23) ...............................................................................	626
A.4.3	COMMAND_DOWNLOAD (0x21) .................................................................................	626
A.4.4	COMMAND_SEND_DATA (0x24) .................................................................................	627
A.4.5	COMMAND_RUN (0x22) .............................................................................................	627
A.4.6	COMMAND_RESET (0x25) .........................................................................................	627
B	Register Quick Reference ...................................................................................	629
C	Ordering and Contact Information .....................................................................	651
C.1	Ordering Information ....................................................................................................	651
C.2	Part Markings ..............................................................................................................	651
C.3	Kits .............................................................................................................................	652
C.4	Support Information .....................................................................................................	652
D	Package Information ............................................................................................	653
D.1	108-Ball BGA Package ................................................................................................	653
D.1.1	Package Dimensions ...................................................................................................	653
D.1.2	Tray Dimensions .........................................................................................................	655
D.1.3	Tape and Reel Dimensions ..........................................................................................	656
D.2	100-Pin LQFP Package ...............................................................................................	657
D.2.1	Package Dimensions ...................................................................................................	657

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D.2.2	Tray Dimensions .........................................................................................................	659
D.2.3	Tape and Reel Dimensions ..........................................................................................	660

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Table of Contents

List of Figures
Figure 1-1.	Stellaris® LM3S1165 Microcontroller High-Level Block Diagram .............................	39
Figure 2-1.	CPU Block Diagram .............................................................................................	48
Figure 2-2.	TPIU Block Diagram ............................................................................................	49
Figure 2-3.	Cortex-M3 Register Set ........................................................................................	51
Figure 2-4.	Bit-Band Mapping ................................................................................................	71
Figure 2-5.	Data Storage .......................................................................................................	72
Figure 2-6.	Vector table .........................................................................................................	78
Figure 2-7.	Exception Stack Frame ........................................................................................	80
Figure 3-1.	SRD Use Example ...............................................................................................	94
Figure 4-1.	JTAG Module Block Diagram ..............................................................................	155
Figure 4-2.	Test Access Port State Machine .........................................................................	158
Figure 4-3.	IDCODE Register Format ...................................................................................	164
Figure 4-4.	BYPASS Register Format ...................................................................................	164
Figure 4-5.	Boundary Scan Register Format .........................................................................	165
Figure 5-1.	Basic RST Configuration ....................................................................................	167
Figure 5-2.	External Circuitry to Extend Power-On Reset .......................................................	168
Figure 5-3.	Reset Circuit Controlled by Switch ......................................................................	168
Figure 5-4.	Power Architecture ............................................................................................	170
Figure 5-5.	Main Clock Tree ................................................................................................	173
Figure 6-1.	Hibernation Module Block Diagram .....................................................................	233
Figure 6-2.	Clock Source Using Crystal ................................................................................	235
Figure 6-3.	Clock Source Using Dedicated Oscillator .............................................................	235
Figure 7-1.	Flash Block Diagram ..........................................................................................	252
Figure 8-1.	GPIO Port Block Diagram ...................................................................................	279
Figure 8-2.	GPIODATA Write Example .................................................................................	280
Figure 8-3.	GPIODATA Read Example .................................................................................	280
Figure 9-1.	GPTM Module Block Diagram ............................................................................	321
Figure 9-2.	16-Bit Input Edge Count Mode Example ..............................................................	325
Figure 9-3.	16-Bit Input Edge Time Mode Example ...............................................................	326
Figure 9-4.	16-Bit PWM Mode Example ................................................................................	327
Figure 10-1.	WDT Module Block Diagram ..............................................................................	357
Figure 11-1.	ADC Module Block Diagram ...............................................................................	381
Figure 11-2.	Differential Sampling Range, VIN_ODD = 1.5 V ......................................................	384
Figure 11-3.	Differential Sampling Range, VIN_ODD = 0.75 V ....................................................	385
Figure 11-4.	Differential Sampling Range, VIN_ODD = 2.25 V ....................................................	385
Figure 11-5.	Internal Temperature Sensor Characteristic .........................................................	386
Figure 12-1.	UART Module Block Diagram .............................................................................	418
Figure 12-2.	UART Character Frame .....................................................................................	419
Figure 12-3.	IrDA Data Modulation .........................................................................................	421
Figure 13-1.	SSI Module Block Diagram .................................................................................	458
Figure 13-2.	TI Synchronous Serial Frame Format (Single Transfer) ........................................	461
Figure 13-3.	TI Synchronous Serial Frame Format (Continuous Transfer) ................................	461
Figure 13-4.	Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ..........................	462
Figure 13-5.	Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ..................	462
Figure 13-6.	Freescale SPI Frame Format with SPO=0 and SPH=1 .........................................	463

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Figure 13-7.	Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ...............	464
Figure 13-8.	Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........	464
Figure 13-9.	Freescale SPI Frame Format with SPO=1 and SPH=1 .........................................	465
Figure 13-10.	MICROWIRE Frame Format (Single Frame) ........................................................	466
Figure 13-11.	MICROWIRE Frame Format (Continuous Transfer) .............................................	467
Figure 13-12.	MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............	467
Figure 14-1.	I2C Block Diagram .............................................................................................	496
Figure 14-2.	I2C Bus Configuration ........................................................................................	496
Figure 14-3.	START and STOP Conditions .............................................................................	497
Figure 14-4.	Complete Data Transfer with a 7-Bit Address .......................................................	497
Figure 14-5.	R/S Bit in First Byte ............................................................................................	497
Figure 14-6.	Data Validity During Bit Transfer on the I2C Bus ...................................................	498
Figure 14-7.	Master Single SEND ..........................................................................................	501
Figure 14-8.	Master Single RECEIVE .....................................................................................	502
Figure 14-9.	Master Burst SEND ...........................................................................................	503
Figure 14-10.	Master Burst RECEIVE ......................................................................................	504
Figure 14-11.	Master Burst RECEIVE after Burst SEND ............................................................	505
Figure 14-12.	Master Burst SEND after Burst RECEIVE ............................................................	506
Figure 14-13.	Slave Command Sequence ................................................................................	507
Figure 15-1.	Analog Comparator Module Block Diagram .........................................................	531
Figure 15-2.	Structure of Comparator Unit ..............................................................................	532
Figure 15-3.	Comparator Internal Reference Structure ............................................................	532
Figure 16-1.	PWM Unit Diagram ............................................................................................	543
Figure 16-2.	PWM Module Block Diagram ..............................................................................	544
Figure 16-3.	PWM Count-Down Mode ....................................................................................	545
Figure 16-4.	PWM Count-Up/Down Mode ..............................................................................	545
Figure 16-5.	PWM Generation Example In Count-Up/Down Mode ...........................................	546
Figure 16-6.	PWM Dead-Band Generator ...............................................................................	546
Figure 17-1.	100-Pin LQFP Package Pin Diagram ..................................................................	580
Figure 17-2.	108-Ball BGA Package Pin Diagram (Top View) ...................................................	581
Figure 20-1.	Load Conditions ................................................................................................	613
Figure 20-2.	JTAG Test Clock Input Timing .............................................................................	615
Figure 20-3.	JTAG Test Access Port (TAP) Timing ..................................................................	616
Figure 20-4.	JTAG TRST Timing ............................................................................................	616
Figure 20-5.	External Reset Timing (RST) ..............................................................................	617
Figure 20-6.	Power-On Reset Timing .....................................................................................	617
Figure 20-7.	Brown-Out Reset Timing ....................................................................................	617
Figure 20-8.	Software Reset Timing .......................................................................................	617
Figure 20-9.	Watchdog Reset Timing .....................................................................................	618
Figure 20-10.	Hibernation Module Timing .................................................................................	619
Figure 20-11.	ADC Input Equivalency Diagram .........................................................................	620
Figure 20-12.	SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
	Measurement ....................................................................................................	621
Figure 20-13.	SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer .................	621
Figure 20-14.	SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .....................................	622
Figure 20-15.	I2C Timing .........................................................................................................	623
Figure D-1.	108-Ball BGA Package Dimensions ....................................................................	653
Figure D-2.	108-Ball BGA Tray Dimensions ...........................................................................	655

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Figure D-3.	108-Ball BGA Tape and Reel Dimensions ............................................................	656
Figure D-4.	100-Pin LQFP Package Dimensions ...................................................................	657
Figure D-5.	100-Pin LQFP Tray Dimensions ..........................................................................	659
Figure D-6.	100-Pin LQFP Tape and Reel Dimensions ...........................................................	660

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List of Tables
Table 1.	Revision History ..................................................................................................	23
Table 2.	Documentation Conventions ................................................................................	28
Table 2-1.	Summary of Processor Mode, Privilege Level, and Stack Use ................................	51
Table 2-2.	Processor Register Map .......................................................................................	52
Table 2-3.	PSR Register Combinations .................................................................................	57
Table 2-4.	Memory Map .......................................................................................................	65
Table 2-5.	Memory Access Behavior .....................................................................................	67
Table 2-6.	SRAM Memory Bit-Banding Regions ....................................................................	69
Table 2-7.	Peripheral Memory Bit-Banding Regions ...............................................................	70
Table 2-8.	Exception Types ..................................................................................................	75
Table 2-9.	Interrupts ............................................................................................................	76
Table 2-10.	Exception Return Behavior ...................................................................................	81
Table 2-11.	Faults .................................................................................................................	82
Table 2-12.	Fault Status and Fault Address Registers ..............................................................	83
Table 2-13.	Cortex-M3 Instruction Summary ...........................................................................	85
Table 3-1.	Core Peripheral Register Regions .........................................................................	88
Table 3-2.	Memory Attributes Summary ................................................................................	91
Table 3-3.	TEX, S, C, and B Bit Field Encoding .....................................................................	94
Table 3-4.	Cache Policy for Memory Attribute Encoding .........................................................	95
Table 3-5.	AP Bit Field Encoding ..........................................................................................	95
Table 3-6.	Memory Region Attributes for Stellaris® Microcontrollers ........................................	95
Table 3-7.	Peripherals Register Map .....................................................................................	96
Table 3-8.	Interrupt Priority Levels ......................................................................................	122
Table 3-9.	Example SIZE Field Values ................................................................................	151
Table 4-1.	JTAG Port Pins Reset State ...............................................................................	156
Table 4-2.	JTAG Instruction Register Commands .................................................................	161
Table 5-1.	Clock Source Options ........................................................................................	171
Table 5-2.	Possible System Clock Frequencies Using the SYSDIV Field ...............................	174
Table 5-3.	Examples of Possible System Clock Frequencies Using the SYSDIV2 Field ..........	174
Table 5-4.	System Control Register Map .............................................................................	178
Table 5-5.	RCC2 Fields that Override RCC fields .................................................................	193
Table 6-1.	Hibernation Module Register Map .......................................................................	239
Table 7-1.	Flash Protection Policy Combinations .................................................................	253
Table 7-2.	User-Programmable Flash Memory Resident Registers .......................................	255
Table 7-3.	Flash Register Map ............................................................................................	256
Table 8-1.	GPIO Pad Configuration Examples .....................................................................	282
Table 8-2.	GPIO Interrupt Configuration Example ................................................................	282
Table 8-3.	GPIO Register Map ...........................................................................................	284
Table 9-1.	Available CCP Pins ............................................................................................	321
Table 9-2.	16-Bit Timer With Prescaler Configurations .........................................................	324
Table 9-3.	Timers Register Map ..........................................................................................	330
Table 10-1.	Watchdog Timer Register Map ............................................................................	358
Table 11-1.	Samples and FIFO Depth of Sequencers ............................................................	381
Table 11-2.	Differential Sampling Pairs .................................................................................	383
Table 11-3.	ADC Register Map .............................................................................................	387
Table 12-1.	UART Register Map ...........................................................................................	423
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Table 13-1.	SSI Register Map ..............................................................................................	468
Table 14-1.	Examples of I2C Master Timer Period versus Speed Mode ...................................	499
Table 14-2.	Inter-Integrated Circuit (I2C) Interface Register Map .............................................	508
Table 14-3.	Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ....................................	513
Table 15-1.	Internal Reference Voltage and ACREFCTL Field Values .....................................	533
Table 15-2.	Analog Comparators Register Map .....................................................................	534
Table 16-1.	PWM Register Map ............................................................................................	548
Table 18-1.	Signals by Pin Number .......................................................................................	582
Table 18-2.	Signals by Signal Name .....................................................................................	586
Table 18-3.	Signals by Function, Except for GPIO .................................................................	590
Table 18-4.	GPIO Pins and Alternate Functions .....................................................................	593
Table 18-5.	Signals by Pin Number .......................................................................................	594
Table 18-6.	Signals by Signal Name .....................................................................................	599
Table 18-7.	Signals by Function, Except for GPIO .................................................................	603
Table 18-8.	GPIO Pins and Alternate Functions .....................................................................	605
Table 18-9.	Connections for Unused Signals (100-pin LQFP) .................................................	607
Table 18-10.	Connections for Unused Signals, 108-pin BGA ....................................................	607
Table 19-1.	Temperature Characteristics ...............................................................................	608
Table 19-2.	Thermal Characteristics .....................................................................................	608
Table 19-3.	ESD Absolute Maximum Ratings ........................................................................	608
Table 20-1.	Maximum Ratings ..............................................................................................	609
Table 20-2.	Recommended DC Operating Conditions ............................................................	609
Table 20-3.	LDO Regulator Characteristics ...........................................................................	610
Table 20-4.	GPIO Module DC Characteristics ........................................................................	610
Table 20-5.	Detailed Power Specifications ............................................................................	611
Table 20-6.	Flash Memory Characteristics ............................................................................	612
Table 20-7.	Hibernation Module DC Characteristics ...............................................................	612
Table 20-8.	Phase Locked Loop (PLL) Characteristics ...........................................................	613
Table 20-9.	Actual PLL Frequency ........................................................................................	613
Table 20-10.	Clock Characteristics .........................................................................................	613
Table 20-11.	Crystal Characteristics .......................................................................................	614
Table 20-12.	System Clock Characteristics with ADC Operation ...............................................	614
Table 20-13.	JTAG Characteristics .........................................................................................	614
Table 20-14.	Reset Characteristics .........................................................................................	616
Table 20-15.	Sleep Modes AC Characteristics .........................................................................	618
Table 20-16.	Hibernation Module AC Characteristics ...............................................................	618
Table 20-17.	GPIO Characteristics .........................................................................................	619
Table 20-18.	ADC Characteristics ...........................................................................................	619
Table 20-19.	ADC Module Internal Reference Characteristics ..................................................	620
Table 20-20.	SSI Characteristics ............................................................................................	620
Table 20-21.	I2C Characteristics .............................................................................................	622
Table 20-22.	Analog Comparator Characteristics .....................................................................	623
Table 20-23.	Analog Comparator Voltage Reference Characteristics ........................................	623
Table C-1.	Part Ordering Information ...................................................................................	651

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List of Registers
The Cortex-M3 Processor .............................................................................................................		46
Register 1:	Cortex General-Purpose Register 0 (R0) ...........................................................................	53
Register 2:	Cortex General-Purpose Register 1 (R1) ...........................................................................	53
Register 3:	Cortex General-Purpose Register 2 (R2) ...........................................................................	53
Register 4:	Cortex General-Purpose Register 3 (R3) ...........................................................................	53
Register 5:	Cortex General-Purpose Register 4 (R4) ...........................................................................	53
Register 6:	Cortex General-Purpose Register 5 (R5) ...........................................................................	53
Register 7:	Cortex General-Purpose Register 6 (R6) ...........................................................................	53
Register 8:	Cortex General-Purpose Register 7 (R7) ...........................................................................	53
Register 9:	Cortex General-Purpose Register 8 (R8) ...........................................................................	53
Register 10:	Cortex General-Purpose Register 9 (R9) ...........................................................................	53
Register 11:	Cortex General-Purpose Register 10 (R10) .......................................................................	53
Register 12:	Cortex General-Purpose Register 11 (R11) ........................................................................	53
Register 13:	Cortex General-Purpose Register 12 (R12) .......................................................................	53
Register 14:	Stack Pointer (SP) ...........................................................................................................	54
Register 15:	Link Register (LR) ............................................................................................................	55
Register 16:	Program Counter (PC) .....................................................................................................	56
Register 17:	Program Status Register (PSR) ........................................................................................	57
Register 18:	Priority Mask Register (PRIMASK) ....................................................................................	61
Register 19:	Fault Mask Register (FAULTMASK) ..................................................................................	62
Register 20:	Base Priority Mask Register (BASEPRI) ............................................................................	63
Register 21:	Control Register (CONTROL) ...........................................................................................	64
Cortex-M3 Peripherals ...................................................................................................................		88
Register 1:	SysTick Control and Status Register (STCTRL), offset 0x010 .............................................	99
Register 2:	SysTick Reload Value Register (STRELOAD), offset 0x014 ..............................................	101
Register 3:	SysTick Current Value Register (STCURRENT), offset 0x018 ...........................................	102
Register 4:	Interrupt 0-31 Set Enable (EN0), offset 0x100 ..................................................................	103
Register 5:	Interrupt 32-43 Set Enable (EN1), offset 0x104 ................................................................	104
Register 6:	Interrupt 0-31 Clear Enable (DIS0), offset 0x180 ..............................................................	105
Register 7:	Interrupt 32-43 Clear Enable (DIS1), offset 0x184 ............................................................	106
Register 8:	Interrupt 0-31 Set Pending (PEND0), offset 0x200 ...........................................................	107
Register 9:	Interrupt 32-43 Set Pending (PEND1), offset 0x204 .........................................................	108
Register 10:	Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ...................................................	109
Register 11:	Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 ..................................................	110
Register 12:	Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 .............................................................	111
Register 13:	Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 ...........................................................	112
Register 14:	Interrupt 0-3 Priority (PRI0), offset 0x400 .........................................................................	113
Register 15:	Interrupt 4-7 Priority (PRI1), offset 0x404 .........................................................................	113
Register 16:	Interrupt 8-11 Priority (PRI2), offset 0x408 .......................................................................	113
Register 17:	Interrupt 12-15 Priority (PRI3), offset 0x40C ....................................................................	113
Register 18:	Interrupt 16-19 Priority (PRI4), offset 0x410 .....................................................................	113
Register 19:	Interrupt 20-23 Priority (PRI5), offset 0x414 .....................................................................	113
Register 20:	Interrupt 24-27 Priority (PRI6), offset 0x418 .....................................................................	113
Register 21:	Interrupt 28-31 Priority (PRI7), offset 0x41C ....................................................................	113
Register 22:	Interrupt 32-35 Priority (PRI8), offset 0x420 .....................................................................	113

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Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 .....................................................................	113
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ...................................................................	113
Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 ..........................................................	115
Register 26: CPU ID Base (CPUID), offset 0xD00 ...............................................................................	116
Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................	117
Register 28: Vector Table Offset (VTABLE), offset 0xD08 ....................................................................	121
Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C .........................................	122
Register 30: System Control (SYSCTRL), offset 0xD10 .......................................................................	124
Register 31: Configuration and Control (CFGCTRL), offset 0xD14 .......................................................	126
Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 .........................................................	128
Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................	129
Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 .........................................................	130
Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 ....................................	131
Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 .....................................................	135
Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C ..............................................................	141
Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................	143
Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 ..............................................................	144
Register 40: MPU Type (MPUTYPE), offset 0xD90 .............................................................................	145
Register 41: MPU Control (MPUCTRL), offset 0xD94 ..........................................................................	146
Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 .......................................................	148
Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C ...................................................	149
Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 .......................................	149
Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ......................................	149
Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 .......................................	149
Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ...............................................	151
Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 ..................................	151
Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 ..................................	151
Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 ..................................	151

System Control ............................................................................................................................		166
Register 1:	Device Identification 0 (DID0), offset 0x000 .....................................................................	180
Register 2:	Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................	182
Register 3:	LDO Power Control (LDOPCTL), offset 0x034 .................................................................	183
Register 4:	Raw Interrupt Status (RIS), offset 0x050 ..........................................................................	184
Register 5:	Interrupt Mask Control (IMC), offset 0x054 ......................................................................	185
Register 6:	Masked Interrupt Status and Clear (MISC), offset 0x058 ..................................................	186
Register 7:	Reset Cause (RESC), offset 0x05C ................................................................................	187
Register 8:	Run-Mode Clock Configuration (RCC), offset 0x060 .........................................................	188
Register 9:	XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................	192
Register 10:	Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ....................................................	193
Register 11:	Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................	195
Register 12:	Device Identification 1 (DID1), offset 0x004 .....................................................................	196
Register 13:	Device Capabilities 0 (DC0), offset 0x008 ........................................................................	198
Register 14:	Device Capabilities 1 (DC1), offset 0x010 ........................................................................	199
Register 15:	Device Capabilities 2 (DC2), offset 0x014 ........................................................................	201
Register 16:	Device Capabilities 3 (DC3), offset 0x018 ........................................................................	203
Register 17:	Device Capabilities 4 (DC4), offset 0x01C .......................................................................	205
Register 18:	Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ...................................	207
Register 19:	Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................	209
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Stellaris® LM3S1165 Microcontroller

Register 20:	Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 .......................	211
Register 21:	Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ...................................	213
Register 22:	Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................	216
Register 23:	Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 .......................	219
Register 24:	Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ...................................	222
Register 25:	Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................	224
Register 26:	Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 .......................	226
Register 27:	Software Reset Control 0 (SRCR0), offset 0x040 .............................................................	228
Register 28:	Software Reset Control 1 (SRCR1), offset 0x044 .............................................................	229
Register 29:	Software Reset Control 2 (SRCR2), offset 0x048 .............................................................	231
Hibernation Module .....................................................................................................................		232
Register 1:	Hibernation RTC Counter (HIBRTCC), offset 0x000 .........................................................	240
Register 2:	Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 .......................................................	241
Register 3:	Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 .......................................................	242
Register 4:	Hibernation RTC Load (HIBRTCLD), offset 0x00C ...........................................................	243
Register 5:	Hibernation Control (HIBCTL), offset 0x010 .....................................................................	244
Register 6:	Hibernation Interrupt Mask (HIBIM), offset 0x014 .............................................................	246
Register 7:	Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 ..................................................	247
Register 8:	Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................	248
Register 9:	Hibernation Interrupt Clear (HIBIC), offset 0x020 .............................................................	249
Register 10:	Hibernation RTC Trim (HIBRTCT), offset 0x024 ...............................................................	250
Register 11:	Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................	251
Internal Memory ...........................................................................................................................		252
Register 1:	Flash Memory Address (FMA), offset 0x000 ....................................................................	258
Register 2:	Flash Memory Data (FMD), offset 0x004 .........................................................................	259
Register 3:	Flash Memory Control (FMC), offset 0x008 .....................................................................	260
Register 4:	Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................	262
Register 5:	Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................	263
Register 6:	Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 .....................	264
Register 7:	USec Reload (USECRL), offset 0x140 ............................................................................	266
Register 8:	Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ...................	267
Register 9:	Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ...............	268
Register 10:	User Debug (USER_DBG), offset 0x1D0 .........................................................................	269
Register 11:	User Register 0 (USER_REG0), offset 0x1E0 ..................................................................	270
Register 12:	User Register 1 (USER_REG1), offset 0x1E4 ..................................................................	271
Register 13:	Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 ....................................	272
Register 14:	Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 ....................................	273
Register 15:	Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ...................................	274
Register 16:	Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ...............................	275
Register 17:	Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ...............................	276
Register 18:	Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ...............................	277
General-Purpose Input/Outputs (GPIOs) ...................................................................................		278
Register 1:	GPIO Data (GPIODATA), offset 0x000 ............................................................................	286
Register 2:	GPIO Direction (GPIODIR), offset 0x400 .........................................................................	287
Register 3:	GPIO Interrupt Sense (GPIOIS), offset 0x404 ..................................................................	288
Register 4:	GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................	289
Register 5:	GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................	290
Register 6:	GPIO Interrupt Mask (GPIOIM), offset 0x410 ...................................................................	291
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Register 7:	GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................	292
Register 8:	GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ...................................................	293
Register 9:	GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................	294
Register 10:	GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................	295
Register 11:	GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................	297
Register 12:	GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................	298
Register 13:	GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................	299
Register 14:	GPIO Open Drain Select (GPIOODR), offset 0x50C .........................................................	300
Register 15:	GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................	301
Register 16:	GPIO Pull-Down Select (GPIOPDR), offset 0x514 ...........................................................	302
Register 17:	GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................	303
Register 18:	GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................	304
Register 19:	GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................	305
Register 20:	GPIO Commit (GPIOCR), offset 0x524 ............................................................................	306
Register 21:	GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 .......................................	308
Register 22:	GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 .......................................	309
Register 23:	GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 .......................................	310
Register 24:	GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ......................................	311
Register 25:	GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 .......................................	312
Register 26:	GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 .......................................	313
Register 27:	GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 .......................................	314
Register 28:	GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ......................................	315
Register 29:	GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 ..........................................	316
Register 30:	GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 ..........................................	317
Register 31:	GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 ..........................................	318
Register 32:	GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC .........................................	319

General-Purpose Timers .............................................................................................................		320
Register 1:	GPTM Configuration (GPTMCFG), offset 0x000 ..............................................................	332
Register 2:	GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................	333
Register 3:	GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................	335
Register 4:	GPTM Control (GPTMCTL), offset 0x00C ........................................................................	337
Register 5:	GPTM Interrupt Mask (GPTMIMR), offset 0x018 ..............................................................	340
Register 6:	GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C .....................................................	342
Register 7:	GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................	343
Register 8:	GPTM Interrupt Clear (GPTMICR), offset 0x024 ..............................................................	344
Register 9:	GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 .................................................	346
Register 10:	GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................	347
Register 11:	GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ...................................................	348
Register 12:	GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 ..................................................	349
Register 13:	GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................	350
Register 14:	GPTM TimerB Prescale (GPTMTBPR), offset 0x03C .......................................................	351
Register 15:	GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ...........................................	352
Register 16:	GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ...........................................	353
Register 17:	GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................	354
Register 18:	GPTM TimerB (GPTMTBR), offset 0x04C .......................................................................	355

Watchdog Timer ...........................................................................................................................	356
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ......................................................................	360
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ...................................................................	361
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Stellaris® LM3S1165 Microcontroller

Register 3:	Watchdog Control (WDTCTL), offset 0x008 .....................................................................	362
Register 4:	Watchdog Interrupt Clear (WDTICR), offset 0x00C ..........................................................	363
Register 5:	Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ..................................................	364
Register 6:	Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 .............................................	365
Register 7:	Watchdog Test (WDTTEST), offset 0x418 .......................................................................	366
Register 8:	Watchdog Lock (WDTLOCK), offset 0xC00 .....................................................................	367
Register 9:	Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 .................................	368
Register 10:	Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 .................................	369
Register 11:	Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 .................................	370
Register 12:	Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................	371
Register 13:	Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 .................................	372
Register 14:	Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 .................................	373
Register 15:	Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 .................................	374
Register 16:	Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................	375
Register 17:	Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 ....................................	376
Register 18:	Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 ....................................	377
Register 19:	Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 ....................................	378
Register 20:	Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ..................................	379
Analog-to-Digital Converter (ADC) .............................................................................................		380
Register 1:	ADC Active Sample Sequencer (ADCACTSS), offset 0x000 .............................................	389
Register 2:	ADC Raw Interrupt Status (ADCRIS), offset 0x004 ...........................................................	390
Register 3:	ADC Interrupt Mask (ADCIM), offset 0x008 .....................................................................	391
Register 4:	ADC Interrupt Status and Clear (ADCISC), offset 0x00C ..................................................	392
Register 5:	ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................	394
Register 6:	ADC Event Multiplexer Select (ADCEMUX), offset 0x014 .................................................	395
Register 7:	ADC Underflow Status (ADCUSTAT), offset 0x018 ...........................................................	399
Register 8:	ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 .............................................	400
Register 9:	ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 .................................	402
Register 10:	ADC Sample Averaging Control (ADCSAC), offset 0x030 .................................................	403
Register 11:	ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ...............	404
Register 12:	ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................	406
Register 13:	ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................	409
Register 14:	ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................	409
Register 15:	ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................	409
Register 16:	ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ...............................	409
Register 17:	ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C .............................	410
Register 18:	ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C .............................	410
Register 19:	ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................	410
Register 20:	ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................	410
Register 21:	ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ...............	411
Register 22:	ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ...............	411
Register 23:	ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................	412
Register 24:	ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................	412
Register 25:	ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ...............	414
Register 26:	ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................	415
Register 27:	ADC Test Mode Loopback (ADCTMLB), offset 0x100 .......................................................	416
Universal Asynchronous Receivers/Transmitters (UARTs) .....................................................		417
Register 1:	UART Data (UARTDR), offset 0x000 ...............................................................................	425
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Register 2:	UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ...........................	427
Register 3:	UART Flag (UARTFR), offset 0x018 ................................................................................	429
Register 4:	UART IrDA Low-Power Register (UARTILPR), offset 0x020 .............................................	431
Register 5:	UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................	432
Register 6:	UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 .......................................	433
Register 7:	UART Line Control (UARTLCRH), offset 0x02C ...............................................................	434
Register 8:	UART Control (UARTCTL), offset 0x030 .........................................................................	436
Register 9:	UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ...........................................	438
Register 10:	UART Interrupt Mask (UARTIM), offset 0x038 .................................................................	440
Register 11:	UART Raw Interrupt Status (UARTRIS), offset 0x03C ......................................................	442
Register 12:	UART Masked Interrupt Status (UARTMIS), offset 0x040 .................................................	443
Register 13:	UART Interrupt Clear (UARTICR), offset 0x044 ...............................................................	444
Register 14:	UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 .....................................	446
Register 15:	UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 .....................................	447
Register 16:	UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 .....................................	448
Register 17:	UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC .....................................	449
Register 18:	UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ......................................	450
Register 19:	UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ......................................	451
Register 20:	UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ......................................	452
Register 21:	UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC .....................................	453
Register 22:	UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................	454
Register 23:	UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................	455
Register 24:	UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................	456
Register 25:	UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................	457

Synchronous Serial Interface (SSI) ............................................................................................		458
Register 1:	SSI Control 0 (SSICR0), offset 0x000 ..............................................................................	470
Register 2:	SSI Control 1 (SSICR1), offset 0x004 ..............................................................................	472
Register 3:	SSI Data (SSIDR), offset 0x008 ......................................................................................	474
Register 4:	SSI Status (SSISR), offset 0x00C ...................................................................................	475
Register 5:	SSI Clock Prescale (SSICPSR), offset 0x010 ..................................................................	477
Register 6:	SSI Interrupt Mask (SSIIM), offset 0x014 .........................................................................	478
Register 7:	SSI Raw Interrupt Status (SSIRIS), offset 0x018 ..............................................................	480
Register 8:	SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................	481
Register 9:	SSI Interrupt Clear (SSIICR), offset 0x020 .......................................................................	482
Register 10:	SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 .............................................	483
Register 11:	SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 .............................................	484
Register 12:	SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 .............................................	485
Register 13:	SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................	486
Register 14:	SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 .............................................	487
Register 15:	SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 .............................................	488
Register 16:	SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 .............................................	489
Register 17:	SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................	490
Register 18:	SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ...............................................	491
Register 19:	SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ...............................................	492
Register 20:	SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ...............................................	493
Register 21:	SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ...............................................	494

Inter-Integrated Circuit (I2C) Interface ........................................................................................		495
Register 1:	I2C Master Slave Address (I2CMSA), offset 0x000 ...........................................................	510
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Register 2:	I2C Master Control/Status (I2CMCS), offset 0x004 ...........................................................	511
Register 3:	I2C Master Data (I2CMDR), offset 0x008 .........................................................................	515
Register 4:	I2C Master Timer Period (I2CMTPR), offset 0x00C ...........................................................	516
Register 5:	I2C Master Interrupt Mask (I2CMIMR), offset 0x010 .........................................................	517
Register 6:	I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 .................................................	518
Register 7:	I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ...........................................	519
Register 8:	I2C Master Interrupt Clear (I2CMICR), offset 0x01C .........................................................	520
Register 9:	I2C Master Configuration (I2CMCR), offset 0x020 ............................................................	521
Register 10:	I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................	523
Register 11:	I2C Slave Control/Status (I2CSCSR), offset 0x004 ...........................................................	524
Register 12:	I2C Slave Data (I2CSDR), offset 0x008 ...........................................................................	526
Register 13:	I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ...........................................................	527
Register 14:	I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ...................................................	528
Register 15:	I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 ..............................................	529
Register 16:	I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................	530
Analog Comparator .....................................................................................................................		531
Register 1:	Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ..................................	535
Register 2:	Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 .......................................	536
Register 3:	Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 .........................................	537
Register 4:	Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 .......................	538
Register 5:	Analog Comparator Status 0 (ACSTAT0), offset 0x020 .....................................................	539
Register 6:	Analog Comparator Control 0 (ACCTL0), offset 0x024 .....................................................	540
Pulse Width Modulator (PWM) ....................................................................................................		542
Register 1:	PWM Master Control (PWMCTL), offset 0x000 ................................................................	551
Register 2:	PWM Time Base Sync (PWMSYNC), offset 0x004 ...........................................................	552
Register 3:	PWM Output Enable (PWMENABLE), offset 0x008 ..........................................................	553
Register 4:	PWM Output Inversion (PWMINVERT), offset 0x00C .......................................................	554
Register 5:	PWM Output Fault (PWMFAULT), offset 0x010 ................................................................	555
Register 6:	PWM Interrupt Enable (PWMINTEN), offset 0x014 ...........................................................	556
Register 7:	PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................	557
Register 8:	PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................	558
Register 9:	PWM Status (PWMSTATUS), offset 0x020 ......................................................................	559
Register 10:	PWM0 Control (PWM0CTL), offset 0x040 .......................................................................	560
Register 11:	PWM1 Control (PWM1CTL), offset 0x080 .......................................................................	560
Register 12:	PWM2 Control (PWM2CTL), offset 0x0C0 ......................................................................	560
Register 13:	PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 ....................................	562
Register 14:	PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 ....................................	562
Register 15:	PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 ....................................	562
Register 16:	PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 ....................................................	565
Register 17:	PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 ....................................................	565
Register 18:	PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ...................................................	565
Register 19:	PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ...........................................	566
Register 20:	PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ...........................................	566
Register 21:	PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ...........................................	566
Register 22:	PWM0 Load (PWM0LOAD), offset 0x050 .......................................................................	567
Register 23:	PWM1 Load (PWM1LOAD), offset 0x090 .......................................................................	567
Register 24:	PWM2 Load (PWM2LOAD), offset 0x0D0 .......................................................................	567
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Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................	568
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................	568
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 ...............................................................	568
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 .............................................................	569
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 .............................................................	569
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 .............................................................	569
Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C .............................................................	570
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C .............................................................	570
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................	570
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................	571
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................	571
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................	571
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................	574
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................	574
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................	574
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................	577
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 .................................................	577
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................	577
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C .............................	578
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC .............................	578
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC .............................	578
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 .............................	579
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 .............................	579
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 .............................	579

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Revision History

The revision history table notes changes made between the indicated revisions of the LM3S1165 data sheet.

Table 1. Revision History

Date	Revision	Description
September 2010	7787	■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
		new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
		added, including all the Cortex-M3 registers.
		■ Changed register names to be consistent with StellarisWare® names: the Cortex-M3 Interrupt
		Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and
		the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0)
		register.
		■ Added clarification of instruction execution during Flash operations.
		■ Modified Figure 8-1 on page 279 to clarify operation of the GPIO inputs when used as an alternate
		function.
		■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits
		wide, bits[7:0].
		■ Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes
		the JTAG controller to be reset, resulting in a loss of JTAG communication.
		■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
		■ In Electrical Characteristics chapter:
		– Added ILKG parameter (GPIO input leakage current) to Table 20-4 on page 610.
		– Corrected values for tCLKRF parameter (SSIClk rise/fall time) in Table 20-20 on page 620.
		■ Added dimensions for Tray and Tape and Reel shipping mediums.
June 2010	7393	■ Corrected base address for SRAM in architectural overview chapter.
		■ Clarified system clock operation, adding content to “Clock Control” on page 170.
		■ In Signal Tables chapter, added table "Connections for Unused Signals."
		■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
		■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.
		■ Additional minor data sheet clarifications and corrections.
April 2010	7007	■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed

field width to 7 bits.

■ Removed erroneous text about restoring the Flash Protection registers. ■ Added note about RST signal routing.

■ Clarified the function of the TnSTALL bit in the GPTMCTL register. ■ Additional minor data sheet clarifications and corrections.

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Table 1. Revision History (continued)

Date	Revision	Description
January 2010	6712	■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.
		■ Clarified wording on Flash memory access errors.
		■ Added section on Flash interrupts.
		■ Changed the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers
		to be indeterminate.
		■ Clarified operation of SSI transmit FIFO.
		■ Made these changes to the Operating Characteristics chapter:
		– Added storage temperature ratings to "Temperature Characteristics" table
		– Added "ESD Absolute Maximum Ratings" table
		■ Made these changes to the Electrical Characteristics chapter:
		– In "Flash Memory Characteristics" table, corrected Mass erase time
		– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
		– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
October 2009	6462	■ Deleted MAXADCSPD bit field from DCGC0 register as it is not applicable in Deep-Sleep mode.
		■ Removed erroneous reference to the WRC bit in the Hibernation chapter.
		■ Deletedresetvaluefor16-bitmodefrom GPTMTAILR, GPTMTAMATCHR,and GPTMTAR registers
		because the module resets in 32-bit mode.
		■ Clarified PWM source for ADC triggering.
		■ Made these changes to the Electrical Characteristics chapter:
		– Removed VSIH and VSIL parameters from Operating Conditions table.
		– Added table showing actual PLL frequency depending on input crystal.
		– Changed the name of the tHIB_REG_WRITE parameter to tHIB_REG_ACCESS.
		– Revised ADC electrical specifications to clarify, including reorganizing and adding new data.
		– Changed SSI set up and hold times to be expressed in system clocks, not ns.
July 2009	5920	Corrected ordering numbers.
July 2009	5902	■ Clarified Power-on reset and		pin operation; added new diagrams.
			RST

■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)

registers.

■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.

■ AddedexplanationofresetvaluetoFMPRE0/1/2/3,FMPPE0/1/2/3,USER_DBG,andUSER_REG0/1

registers.

■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.

■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added EIR (Internal voltage reference error) parameter.

■ Additional minor data sheet clarifications and corrections.

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Table 1. Revision History (continued)

Date	Revision	Description
April 2009	5367	■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 160).
		■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
		of the output divisor.
		■ Added "GPIO Module DC Characteristics" table (see Table 20-4 on page 610).
		■ Additional minor data sheet clarifications and corrections.
January 2009	4660	■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
		■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
		is no data in the TX FIFO.
		■ Additional minor data sheet clarifications and corrections.
November 2008	4283	■ Revised High-Level Block Diagram.
		■ Additional minor data sheet clarifications and corrections were made.
October 2008	4149	■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
		register.
		■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
		Internal Memory chapter. The correct value is 0x0000.0006.
		■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
August 2008	3447	■ Added note on clearing interrupts to Interrupts chapter.
		■ Added Power Architecture diagram to System Control chapter.
		■ Additional minor data sheet clarifications and corrections.
July 2008	3108	■ Additional minor data sheet clarifications and corrections.
May 2008	2972	■ The 108-Ball BGA pin diagram and pin tables had an error. The following signals were erroneously
		indicated as available and have now been changed to a No Connect (NC):
		– Ball C1: Changed PE7 to NC
		– Ball C2: Changed PE6 to NC
		– Ball D2: Changed PE5 to NC
		– Ball D1: Changed PE4 to NC
		■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
		the LDO output as the source of VDD25 input.
		■ Additional minor data sheet clarifications and corrections.
April 2008	2881	■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating
		Characteristics chapter.

■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of 1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.

■ Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical Characteristics" chapter.

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Revision History

Table 1. Revision History (continued)

Date	Revision Description

■The "Hibernation Module DC Electricals"table was added to the "Electrical Characteristics"chapter.

■The TVDDRISE parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter was changed from a max of 100 to 250.

■The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical Characteristics" chapter was changed from 4 to 3.

■The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data sheets incorrectly noted it as 30 kHz ± 30%).

■A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value.

■The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly noted the reset was 0x0 (MOSC).

■Two figures on clock source were added to the "Hibernation Module":

–Clock Source Using Crystal

–Clock Source Using Dedicated Oscillator

■The following notes on battery management were added to the "Hibernation Module" chapter:

–Battery voltage is not measured while in Hibernate mode.

–System level factors may affect the accuracy of the low battery detect circuit. The designer should consider battery type, discharge characteristics, and a test load during battery voltage measurements.

■A note on high-current applications was added to the GPIO chapter:

For special high-current applications, the GPIO output buffers may be used with the following restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only a maximum of two per side of the physical package or BGA pin group with the total number of high-current GPIO outputs not exceeding four for the entire package.

■A note on Schmitt inputs was added to the GPIO chapter: Pins configured as digital inputs are Schmitt-triggered.

■The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.

■The "Differential Sampling Range" figures in the ADC chapter were clarified.

■Thelastrevisionofthedatasheet(revision2550)introducedtwoerrorsthathavenowbeencorrected:

–The LQFP pin diagrams and pin tables were missing the comparator positive and negative input pins.

–The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.

■Additional minor data sheet clarifications and corrections.

March 2008

2550

Started tracking revision history.

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About This Document

This data sheet provides reference information for the LM3S1165 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core.

Audience

This manual is intended for system software developers, hardware designers, and application developers.

About This Manual

This document is organized into sections that correspond to each major feature.

Related Documents

The following related documents are available on the Stellaris® web site at www.ti.com/stellaris:

■Stellaris® Errata

■ARM® Cortex™-M3 Errata

■Cortex™-M3 Instruction Set Technical User's Manual

■Stellaris® Graphics Library User's Guide

■Stellaris® Peripheral Driver Library User's Guide

The following related documents are also referenced:

■ARM® Debug Interface V5 Architecture Specification

■IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture

This documentation list was current as of publication date. Please check the web site for additional documentation, including application notes and white papers.

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About This Document

Documentation Conventions

This document uses the conventions shown in Table 2 on page 28.

Table 2. Documentation Conventions

Notation Meaning

General Register Notation

REGISTER	APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
	Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
	than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
	registers: SRCR0, SRCR1 , and SRCR2.
bit	A single bit in a register.
bit field	Two or more consecutive and related bits.
offset 0xnnn	A hexadecimal increment to a register's address, relative to that module's base address as specified
	in Table 2-4 on page 65.
Register N	Registers are numbered consecutively throughout the document to aid in referencing them. The
	register number has no meaning to software.
reserved	Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
	0; however, user software should not rely on the value of a reserved bit. To provide software
	compatibility with future products, the value of a reserved bit should be preserved across a
	read-modify-write operation.
yy:xx	The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
	that register.
Register Bit/Field	This value in the register bit diagram indicates whether software running on the controller can
Types	change the value of the bit field.
RC	Software can read this field. The bit or field is cleared by hardware after reading the bit/field.
RO	Software can read this field. Always write the chip reset value.
R/W	Software can read or write this field.
R/WC	Software can read or write this field. Writing to it with any value clears the register.
R/W1C	Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
	register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
	This register type is primarily used for clearing interrupt status bits where the read operation
	provides the interrupt status and the write of the read value clears only the interrupts being reported
	at the time the register was read.
R/W1S	Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
	value in the register.
W1C	Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
	A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
	read of the register returns no meaningful data.
	This register is typically used to clear the corresponding bit in an interrupt register.
WO	Only a write by software is valid; a read of the register returns no meaningful data.
Register Bit/Field	This value in the register bit diagram shows the bit/field value after any reset, unless noted.
Reset Value
0	Bit cleared to 0 on chip reset.
1	Bit set to 1 on chip reset.
-	Nondeterministic.
Pin/Signal Notation
[ ]	Pin alternate function; a pin defaults to the signal without the brackets.
pin	Refers to the physical connection on the package.

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Table 2. Documentation Conventions (continued)

Notation		Meaning
signal		Refers to the electrical signal encoding of a pin.
assert a signal		Change the value of the signal from the logically False state to the logically True state. For active
		High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
		is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and
							SIGNAL
		below).
deassert a signal		Change the value of the signal from the logically True state to the logically False state.
		Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
SIGNAL
		it is active Low. To assert		is to drive it Low; to deassert		is to drive it High.
			SIGNAL		SIGNAL
SIGNAL		Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
		assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.

Numbers

XAn uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on.

0x	Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
	All other numbers within register tables are assumed to be binary. Within conceptual information,
	binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
	without a prefix or suffix.

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Architectural Overview

1Architectural Overview

The Stellaris® family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.

The Stellaris® family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. The Stellaris® LM3S1000 series extends the Stellaris® family with larger on-chip memories, enhanced power management, and expanded I/O and control capabilities.

The LM3S1165 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security.

For applications requiring extreme conservation of power, the LM3S1165 microcontroller features a battery-backed Hibernation module to efficiently power down the LM3S1165 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S1165 microcontroller perfectly for battery applications.

In addition, the LM3S1165 microcontroller offers the advantages of ARM's widely available development tools,System-on-Chip(SoC) infrastructureIPapplications,and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S1165 microcontroller is code-compatible to all members of the extensive Stellaris® family; providing flexibility to fit our customers' precise needs.

Texas Instruments offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. See “Ordering and Contact

Information” on page 651 for ordering information for Stellaris® family devices.

1.1Product Features

The LM3S1165 microcontroller includes the following product features:

■32-Bit RISC Performance

–32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications

–System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism

–Thumb®-compatible Thumb-2-only instruction set processor core for high code density

–50-MHz operation

–Hardware-division and single-cycle-multiplication

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