Texas instruments STELLARIS LM3S1150 DATA SHEET
TEXAS INSTRUMENTS-PRODUCTION DATA
Stellaris® LM3S1150 Microcontroller
DATA SHEET
DS-LM3S1150-7787
Copyright © 2007-2010 Texas Instruments
Incorporated
Copyright
Copyright ©2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
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http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Table of Contents
Revision History ............................................................................................................................. 21
About This Document .................................................................................................................... 25
Audience .............................................................................................................................................. 25
About This Manual ................................................................................................................................ 25
Related Documents ............................................................................................................................... 25
Documentation Conventions .................................................................................................................. 26
1 Architectural Overview .......................................................................................... 28
1.1 Product Features .......................................................................................................... 28
1.2 Target Applications ........................................................................................................ 35
1.3 High-Level Block Diagram ............................................................................................. 36
1.4 Functional Overview ...................................................................................................... 38
1.4.1 ARM Cortex™-M3 ......................................................................................................... 38
1.4.2 Motor Control Peripherals .............................................................................................. 39
1.4.3 Analog Peripherals ........................................................................................................ 40
1.4.4 Serial Communications Peripherals ................................................................................ 40
1.4.5 System Peripherals ....................................................................................................... 41
1.4.6 Memory Peripherals ...................................................................................................... 42
1.4.7 Additional Features ....................................................................................................... 42
1.4.8 Hardware Details .......................................................................................................... 43
2 The Cortex-M3 Processor ...................................................................................... 44
2.1 Block Diagram .............................................................................................................. 45
2.2 Overview ...................................................................................................................... 46
2.2.1 System-Level Interface .................................................................................................. 46
2.2.2 Integrated Configurable Debug ...................................................................................... 46
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 47
2.2.4 Cortex-M3 System Component Details ........................................................................... 47
2.3 Programming Model ...................................................................................................... 48
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 48
2.3.2 Stacks .......................................................................................................................... 48
2.3.3 Register Map ................................................................................................................ 49
2.3.4 Register Descriptions .................................................................................................... 50
2.3.5 Exceptions and Interrupts .............................................................................................. 63
2.3.6 Data Types ................................................................................................................... 63
2.4 Memory Model .............................................................................................................. 63
2.4.1 Memory Regions, Types and Attributes ........................................................................... 65
2.4.2 Memory System Ordering of Memory Accesses .............................................................. 65
2.4.3 Behavior of Memory Accesses ....................................................................................... 65
2.4.4 Software Ordering of Memory Accesses ......................................................................... 66
2.4.5 Bit-Banding ................................................................................................................... 67
2.4.6 Data Storage ................................................................................................................ 69
2.4.7 Synchronization Primitives ............................................................................................. 70
2.5 Exception Model ........................................................................................................... 71
2.5.1 Exception States ........................................................................................................... 71
2.5.2 Exception Types ............................................................................................................ 72
2.5.3 Exception Handlers ....................................................................................................... 75
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2.5.4 Vector Table .................................................................................................................. 75
2.5.5 Exception Priorities ....................................................................................................... 76
2.5.6 Interrupt Priority Grouping .............................................................................................. 77
2.5.7 Exception Entry and Return ........................................................................................... 77
2.6 Fault Handling .............................................................................................................. 79
2.6.1 Fault Types ................................................................................................................... 80
2.6.2 Fault Escalation and Hard Faults .................................................................................... 80
2.6.3 Fault Status Registers and Fault Address Registers ........................................................ 81
2.6.4 Lockup ......................................................................................................................... 81
2.7 Power Management ...................................................................................................... 81
2.7.1 Entering Sleep Modes ................................................................................................... 82
2.7.2 Wake Up from Sleep Mode ............................................................................................ 82
2.8 Instruction Set Summary ............................................................................................... 83
3 Cortex-M3 Peripherals ........................................................................................... 86
3.1 Functional Description ................................................................................................... 86
3.1.1 System Timer (SysTick) ................................................................................................. 86
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 87
3.1.3 System Control Block (SCB) .......................................................................................... 89
3.1.4 Memory Protection Unit (MPU) ....................................................................................... 89
3.2 Register Map ................................................................................................................ 94
3.3 System Timer (SysTick) Register Descriptions ................................................................ 96
3.4 NVIC Register Descriptions .......................................................................................... 100
3.5 System Control Block (SCB) Register Descriptions ........................................................ 113
3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 142
4 JTAG Interface ...................................................................................................... 152
4.1 Block Diagram ............................................................................................................ 153
4.2 Functional Description ................................................................................................. 153
4.2.1 JTAG Interface Pins ..................................................................................................... 153
4.2.2 JTAG TAP Controller ................................................................................................... 155
4.2.3 Shift Registers ............................................................................................................ 156
4.2.4 Operational Considerations .......................................................................................... 156
4.3 Initialization and Configuration ..................................................................................... 159
4.4 Register Descriptions .................................................................................................. 159
4.4.1 Instruction Register (IR) ............................................................................................... 159
4.4.2 Data Registers ............................................................................................................ 161
5 System Control ..................................................................................................... 164
5.1 Functional Description ................................................................................................. 164
5.1.1 Device Identification .................................................................................................... 164
5.1.2 Reset Control .............................................................................................................. 164
5.1.3 Power Control ............................................................................................................. 167
5.1.4 Clock Control .............................................................................................................. 168
5.1.5 System Control ........................................................................................................... 174
5.2 Initialization and Configuration ..................................................................................... 175
5.3 Register Map .............................................................................................................. 175
5.4 Register Descriptions .................................................................................................. 177
6 Hibernation Module .............................................................................................. 229
6.1 Block Diagram ............................................................................................................ 230
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6.2 Functional Description ................................................................................................. 230
6.2.1 Register Access Timing ............................................................................................... 230
6.2.2 Clock Source .............................................................................................................. 231
6.2.3 Battery Management ................................................................................................... 232
6.2.4 Real-Time Clock .......................................................................................................... 233
6.2.5 Non-Volatile Memory ................................................................................................... 233
6.2.6 Power Control ............................................................................................................. 233
6.2.7 Initiating Hibernate ...................................................................................................... 234
6.2.8 Interrupts and Status ................................................................................................... 234
6.3 Initialization and Configuration ..................................................................................... 234
6.3.1 Initialization ................................................................................................................. 235
6.3.2 RTC Match Functionality (No Hibernation) .................................................................... 235
6.3.3 RTC Match/Wake-Up from Hibernation ......................................................................... 235
6.3.4 External Wake-Up from Hibernation .............................................................................. 235
6.3.5 RTC/External Wake-Up from Hibernation ...................................................................... 236
6.4 Register Map .............................................................................................................. 236
6.5 Register Descriptions .................................................................................................. 236
7 Internal Memory ................................................................................................... 249
7.1 Block Diagram ............................................................................................................ 249
7.2 Functional Description ................................................................................................. 249
7.2.1 SRAM Memory ............................................................................................................ 249
7.2.2 Flash Memory ............................................................................................................. 250
7.3 Flash Memory Initialization and Configuration ............................................................... 251
7.3.1 Flash Programming ..................................................................................................... 251
7.3.2 Nonvolatile Register Programming ............................................................................... 252
7.4 Register Map .............................................................................................................. 253
7.5 Flash Register Descriptions (Flash Control Offset) ......................................................... 254
7.6 Flash Register Descriptions (System Control Offset) ...................................................... 262
8 General-Purpose Input/Outputs (GPIOs) ........................................................... 275
8.1 Functional Description ................................................................................................. 275
8.1.1 Data Control ............................................................................................................... 276
8.1.2 Interrupt Control .......................................................................................................... 277
8.1.3 Mode Control .............................................................................................................. 278
8.1.4 Commit Control ........................................................................................................... 278
8.1.5 Pad Control ................................................................................................................. 278
8.1.6 Identification ............................................................................................................... 278
8.2 Initialization and Configuration ..................................................................................... 278
8.3 Register Map .............................................................................................................. 280
8.4 Register Descriptions .................................................................................................. 281
9 General-Purpose Timers ...................................................................................... 316
9.1 Block Diagram ............................................................................................................ 317
9.2 Functional Description ................................................................................................. 317
9.2.1 GPTM Reset Conditions .............................................................................................. 318
9.2.2 32-Bit Timer Operating Modes ...................................................................................... 318
9.2.3 16-Bit Timer Operating Modes ...................................................................................... 319
9.3 Initialization and Configuration ..................................................................................... 323
9.3.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 323
9.3.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 324
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9.3.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 324
9.3.4 16-Bit Input Edge Count Mode ..................................................................................... 325
9.3.5 16-Bit Input Edge Timing Mode .................................................................................... 325
9.3.6 16-Bit PWM Mode ....................................................................................................... 326
9.4 Register Map .............................................................................................................. 326
9.5 Register Descriptions .................................................................................................. 327
10 Watchdog Timer ................................................................................................... 352
10.1 Block Diagram ............................................................................................................ 353
10.2 Functional Description ................................................................................................. 353
10.3 Initialization and Configuration ..................................................................................... 354
10.4 Register Map .............................................................................................................. 354
10.5 Register Descriptions .................................................................................................. 355
11 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 376
11.1 Block Diagram ............................................................................................................ 377
11.2 Functional Description ................................................................................................. 377
11.2.1 Transmit/Receive Logic ............................................................................................... 377
11.2.2 Baud-Rate Generation ................................................................................................. 378
11.2.3 Data Transmission ...................................................................................................... 379
11.2.4 Serial IR (SIR) ............................................................................................................. 379
11.2.5 FIFO Operation ........................................................................................................... 380
11.2.6 Interrupts .................................................................................................................... 380
11.2.7 Loopback Operation .................................................................................................... 381
11.2.8 IrDA SIR block ............................................................................................................ 381
11.3 Initialization and Configuration ..................................................................................... 381
11.4 Register Map .............................................................................................................. 382
11.5 Register Descriptions .................................................................................................. 383
12 Synchronous Serial Interface (SSI) .................................................................... 417
12.1 Block Diagram ............................................................................................................ 417
12.2 Functional Description ................................................................................................. 418
12.2.1 Bit Rate Generation ..................................................................................................... 418
12.2.2 FIFO Operation ........................................................................................................... 418
12.2.3 Interrupts .................................................................................................................... 418
12.2.4 Frame Formats ........................................................................................................... 419
12.3 Initialization and Configuration ..................................................................................... 426
12.4 Register Map .............................................................................................................. 427
12.5 Register Descriptions .................................................................................................. 428
13 Inter-Integrated Circuit (I2C) Interface ................................................................ 454
13.1 Block Diagram ............................................................................................................ 455
13.2 Functional Description ................................................................................................. 455
13.2.1 I2C Bus Functional Overview ........................................................................................ 455
13.2.2 Available Speed Modes ............................................................................................... 457
13.2.3 Interrupts .................................................................................................................... 458
13.2.4 Loopback Operation .................................................................................................... 459
13.2.5 Command Sequence Flow Charts ................................................................................ 459
13.3 Initialization and Configuration ..................................................................................... 466
13.4 Register Map .............................................................................................................. 467
13.5 Register Descriptions (I2C Master) ............................................................................... 468
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13.6 Register Descriptions (I2C Slave) ................................................................................. 481
14 Analog Comparators ............................................................................................ 490
14.1 Block Diagram ............................................................................................................ 491
14.2 Functional Description ................................................................................................. 491
14.2.1 Internal Reference Programming .................................................................................. 492
14.3 Initialization and Configuration ..................................................................................... 493
14.4 Register Map .............................................................................................................. 493
14.5 Register Descriptions .................................................................................................. 494
15 Pulse Width Modulator (PWM) ............................................................................ 502
15.1 Block Diagram ............................................................................................................ 503
15.2 Functional Description ................................................................................................. 504
15.2.1 PWM Timer ................................................................................................................. 504
15.2.2 PWM Comparators ...................................................................................................... 504
15.2.3 PWM Signal Generator ................................................................................................ 505
15.2.4 Dead-Band Generator ................................................................................................. 506
15.2.5 Interrupt Selector ......................................................................................................... 506
15.2.6 Synchronization Methods ............................................................................................ 507
15.2.7 Fault Conditions .......................................................................................................... 507
15.2.8 Output Control Block ................................................................................................... 507
15.3 Initialization and Configuration ..................................................................................... 507
15.4 Register Map .............................................................................................................. 508
15.5 Register Descriptions .................................................................................................. 510
16 Quadrature Encoder Interface (QEI) ................................................................... 539
16.1 Block Diagram ............................................................................................................ 539
16.2 Functional Description ................................................................................................. 540
16.3 Initialization and Configuration ..................................................................................... 542
16.4 Register Map .............................................................................................................. 543
16.5 Register Descriptions .................................................................................................. 543
17 Pin Diagram .......................................................................................................... 556
18 Signal Tables ........................................................................................................ 558
18.1 100-Pin LQFP Package Pin Tables ............................................................................... 558
18.2 108-Pin BGA Package Pin Tables ................................................................................ 570
18.3 Connections for Unused Signals ................................................................................... 583
19 Operating Characteristics ................................................................................... 585
20 Electrical Characteristics .................................................................................... 586
20.1 DC Characteristics ...................................................................................................... 586
20.1.1 Maximum Ratings ....................................................................................................... 586
20.1.2 Recommended DC Operating Conditions ...................................................................... 586
20.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 587
20.1.4 GPIO Module Characteristics ....................................................................................... 587
20.1.5 Power Specifications ................................................................................................... 587
20.1.6 Flash Memory Characteristics ...................................................................................... 589
20.1.7 Hibernation ................................................................................................................. 589
20.2 AC Characteristics ....................................................................................................... 589
20.2.1 Load Conditions .......................................................................................................... 589
20.2.2 Clocks ........................................................................................................................ 590
20.2.3 JTAG and Boundary Scan ............................................................................................ 591
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20.2.4 Reset ......................................................................................................................... 593
20.2.5 Sleep Modes ............................................................................................................... 595
20.2.6 Hibernation Module ..................................................................................................... 595
20.2.7 General-Purpose I/O (GPIO) ........................................................................................ 595
20.2.8 Synchronous Serial Interface (SSI) ............................................................................... 596
20.2.9 Inter-Integrated Circuit (I2C) Interface ........................................................................... 597
20.2.10 Analog Comparator ..................................................................................................... 598
A Serial Flash Loader .............................................................................................. 599
A.1 Serial Flash Loader ..................................................................................................... 599
A.2 Interfaces ................................................................................................................... 599
A.2.1 UART ......................................................................................................................... 599
A.2.2 SSI ............................................................................................................................. 599
A.3 Packet Handling .......................................................................................................... 600
A.3.1 Packet Format ............................................................................................................ 600
A.3.2 Sending Packets ......................................................................................................... 600
A.3.3 Receiving Packets ....................................................................................................... 600
A.4 Commands ................................................................................................................. 601
A.4.1 COMMAND_PING (0X20) ............................................................................................ 601
A.4.2 COMMAND_GET_STATUS (0x23) ............................................................................... 601
A.4.3 COMMAND_DOWNLOAD (0x21) ................................................................................. 601
A.4.4 COMMAND_SEND_DATA (0x24) ................................................................................. 602
A.4.5 COMMAND_RUN (0x22) ............................................................................................. 602
A.4.6 COMMAND_RESET (0x25) ......................................................................................... 602
B Register Quick Reference ................................................................................... 604
C Ordering and Contact Information ..................................................................... 625
C.1 Ordering Information .................................................................................................... 625
C.2 Part Markings .............................................................................................................. 625
C.3 Kits ............................................................................................................................. 626
C.4 Support Information ..................................................................................................... 626
D Package Information ............................................................................................ 627
D.1 108-Ball BGA Package ................................................................................................ 627
D.1.1 Package Dimensions ................................................................................................... 627
D.1.2 Tray Dimensions ......................................................................................................... 629
D.1.3 Tape and Reel Dimensions .......................................................................................... 630
D.2 100-Pin LQFP Package ............................................................................................... 631
D.2.1 Package Dimensions ................................................................................................... 631
D.2.2 Tray Dimensions ......................................................................................................... 633
D.2.3 Tape and Reel Dimensions .......................................................................................... 634
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List of Figures
Figure 1-1. Stellaris®LM3S1150 Microcontroller High-Level Block Diagram ............................. 37
Figure 2-1. CPU Block Diagram ............................................................................................. 46
Figure 2-2. TPIU Block Diagram ............................................................................................ 47
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 49
Figure 2-4. Bit-Band Mapping ................................................................................................ 69
Figure 2-5. Data Storage ....................................................................................................... 70
Figure 2-6. Vector table ......................................................................................................... 76
Figure 2-7. Exception Stack Frame ........................................................................................ 78
Figure 3-1. SRD Use Example ............................................................................................... 92
Figure 4-1. JTAG Module Block Diagram .............................................................................. 153
Figure 4-2. Test Access Port State Machine ......................................................................... 156
Figure 4-3. IDCODE Register Format ................................................................................... 162
Figure 4-4. BYPASS Register Format ................................................................................... 162
Figure 4-5. Boundary Scan Register Format ......................................................................... 163
Figure 5-1. Basic RST Configuration .................................................................................... 165
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 166
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 166
Figure 5-4. Power Architecture ............................................................................................ 168
Figure 5-5. Main Clock Tree ................................................................................................ 171
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 230
Figure 6-2. Clock Source Using Crystal ................................................................................ 232
Figure 6-3. Clock Source Using Dedicated Oscillator ............................................................. 232
Figure 7-1. Flash Block Diagram .......................................................................................... 249
Figure 8-1. GPIO Port Block Diagram ................................................................................... 276
Figure 8-2. GPIODATA Write Example ................................................................................. 277
Figure 8-3. GPIODATA Read Example ................................................................................. 277
Figure 9-1. GPTM Module Block Diagram ............................................................................ 317
Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 321
Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 322
Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 323
Figure 10-1. WDT Module Block Diagram .............................................................................. 353
Figure 11-1. UART Module Block Diagram ............................................................................. 377
Figure 11-2. UART Character Frame ..................................................................................... 378
Figure 11-3. IrDA Data Modulation ......................................................................................... 380
Figure 12-1. SSI Module Block Diagram ................................................................................. 417
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 420
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 420
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 421
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 421
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 422
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 423
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 423
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 424
Figure 12-10. MICROWIRE Frame Format (Single Frame) ........................................................ 425
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 426
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 426
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Table of Contents
Figure 13-1. I2C Block Diagram ............................................................................................. 455
Figure 13-2. I2C Bus Configuration ........................................................................................ 455
Figure 13-3. START and STOP Conditions ............................................................................. 456
Figure 13-4. Complete Data Transfer with a 7-Bit Address ....................................................... 456
Figure 13-5. R/S Bit in First Byte ............................................................................................ 456
Figure 13-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 457
Figure 13-7. Master Single SEND .......................................................................................... 460
Figure 13-8. Master Single RECEIVE ..................................................................................... 461
Figure 13-9. Master Burst SEND ........................................................................................... 462
Figure 13-10. Master Burst RECEIVE ...................................................................................... 463
Figure 13-11. Master Burst RECEIVE after Burst SEND ............................................................ 464
Figure 13-12. Master Burst SEND after Burst RECEIVE ............................................................ 465
Figure 13-13. Slave Command Sequence ................................................................................ 466
Figure 14-1. Analog Comparator Module Block Diagram ......................................................... 491
Figure 14-2. Structure of Comparator Unit .............................................................................. 492
Figure 14-3. Comparator Internal Reference Structure ............................................................ 492
Figure 15-1. PWM Unit Diagram ............................................................................................ 503
Figure 15-2. PWM Module Block Diagram .............................................................................. 504
Figure 15-3. PWM Count-Down Mode .................................................................................... 505
Figure 15-4. PWM Count-Up/Down Mode .............................................................................. 505
Figure 15-5. PWM Generation Example In Count-Up/Down Mode ........................................... 506
Figure 15-6. PWM Dead-Band Generator ............................................................................... 506
Figure 16-1. QEI Block Diagram ............................................................................................ 540
Figure 16-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 541
Figure 17-1. 100-Pin LQFP Package Pin Diagram .................................................................. 556
Figure 17-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 557
Figure 20-1. Load Conditions ................................................................................................ 590
Figure 20-2. JTAG Test Clock Input Timing ............................................................................. 592
Figure 20-3. JTAG Test Access Port (TAP) Timing .................................................................. 592
Figure 20-4. JTAG TRST Timing ............................................................................................ 593
Figure 20-5. External Reset Timing (RST) .............................................................................. 593
Figure 20-6. Power-On Reset Timing ..................................................................................... 594
Figure 20-7. Brown-Out Reset Timing .................................................................................... 594
Figure 20-8. Software Reset Timing ....................................................................................... 594
Figure 20-9. Watchdog Reset Timing ..................................................................................... 594
Figure 20-10. Hibernation Module Timing ................................................................................. 595
Figure 20-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Figure 20-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 597
Figure 20-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 597
Figure 20-14. I2C Timing ......................................................................................................... 598
Figure D-1. 108-Ball BGA Package Dimensions .................................................................... 627
Figure D-2. 108-Ball BGA Tray Dimensions ........................................................................... 629
Figure D-3. 108-Ball BGA Tape and Reel Dimensions ............................................................ 630
Figure D-4. 100-Pin LQFP Package Dimensions ................................................................... 631
Figure D-5. 100-Pin LQFP Tray Dimensions .......................................................................... 633
Figure D-6. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 634
Measurement .................................................................................................... 596
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List of Tables
Table 1. Revision History .................................................................................................. 21
Table 2. Documentation Conventions ................................................................................ 26
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 49
Table 2-2. Processor Register Map ....................................................................................... 50
Table 2-3. PSR Register Combinations ................................................................................. 55
Table 2-4. Memory Map ....................................................................................................... 63
Table 2-5. Memory Access Behavior ..................................................................................... 65
Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 67
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 68
Table 2-8. Exception Types .................................................................................................. 73
Table 2-9. Interrupts ............................................................................................................ 74
Table 2-10. Exception Return Behavior ................................................................................... 79
Table 2-11. Faults ................................................................................................................. 80
Table 2-12. Fault Status and Fault Address Registers .............................................................. 81
Table 2-13. Cortex-M3 Instruction Summary ........................................................................... 83
Table 3-1. Core Peripheral Register Regions ......................................................................... 86
Table 3-2. Memory Attributes Summary ................................................................................ 89
Table 3-3. TEX, S, C, and B Bit Field Encoding ..................................................................... 92
Table 3-4. Cache Policy for Memory Attribute Encoding ......................................................... 93
Table 3-5. AP Bit Field Encoding .......................................................................................... 93
Table 3-6. Memory Region Attributes for Stellaris®Microcontrollers ........................................ 93
Table 3-7. Peripherals Register Map ..................................................................................... 94
Table 3-8. Interrupt Priority Levels ...................................................................................... 120
Table 3-9. Example SIZE Field Values ................................................................................ 149
Table 4-1. JTAG Port Pins Reset State ............................................................................... 154
Table 4-2. JTAG Instruction Register Commands ................................................................. 159
Table 5-1. Clock Source Options ........................................................................................ 169
Table 5-2. Possible System Clock Frequencies Using the SYSDIV Field ............................... 172
Table 5-3. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 172
Table 5-4. System Control Register Map ............................................................................. 176
Table 5-5. RCC2 Fields that Override RCC fields ................................................................. 191
Table 6-1. Hibernation Module Register Map ....................................................................... 236
Table 7-1. Flash Protection Policy Combinations ................................................................. 250
Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 252
Table 7-3. Flash Register Map ............................................................................................ 253
Table 8-1. GPIO Pad Configuration Examples ..................................................................... 279
Table 8-2. GPIO Interrupt Configuration Example ................................................................ 279
Table 8-3. GPIO Register Map ........................................................................................... 280
Table 9-1. Available CCP Pins ............................................................................................ 317
Table 9-2. 16-Bit Timer With Prescaler Configurations ......................................................... 320
Table 9-3. Timers Register Map .......................................................................................... 326
Table 10-1. Watchdog Timer Register Map ............................................................................ 354
Table 11-1. UART Register Map ........................................................................................... 382
Table 12-1. SSI Register Map .............................................................................................. 427
Table 13-1. Examples of I2C Master Timer Period versus Speed Mode ................................... 458
Table 13-2. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 467
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Table 13-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 472
Table 14-1. Internal Reference Voltage and ACREFCTL Field Values ..................................... 492
Table 14-2. Analog Comparators Register Map ..................................................................... 494
Table 15-1. PWM Register Map ............................................................................................ 508
Table 16-1. QEI Register Map .............................................................................................. 543
Table 18-1. Signals by Pin Number ....................................................................................... 558
Table 18-2. Signals by Signal Name ..................................................................................... 562
Table 18-3. Signals by Function, Except for GPIO ................................................................. 566
Table 18-4. GPIO Pins and Alternate Functions ..................................................................... 569
Table 18-5. Signals by Pin Number ....................................................................................... 570
Table 18-6. Signals by Signal Name ..................................................................................... 575
Table 18-7. Signals by Function, Except for GPIO ................................................................. 579
Table 18-8. GPIO Pins and Alternate Functions ..................................................................... 582
Table 18-9. Connections for Unused Signals (100-pin LQFP) ................................................. 584
Table 18-10. Connections for Unused Signals, 108-pin BGA .................................................... 584
Table 19-1. Temperature Characteristics ............................................................................... 585
Table 19-2. Thermal Characteristics ..................................................................................... 585
Table 19-3. ESD Absolute Maximum Ratings ........................................................................ 585
Table 20-1. Maximum Ratings .............................................................................................. 586
Table 20-2. Recommended DC Operating Conditions ............................................................ 586
Table 20-3. LDO Regulator Characteristics ........................................................................... 587
Table 20-4. GPIO Module DC Characteristics ........................................................................ 587
Table 20-5. Detailed Power Specifications ............................................................................ 588
Table 20-6. Flash Memory Characteristics ............................................................................ 589
Table 20-7. Hibernation Module DC Characteristics ............................................................... 589
Table 20-8. Phase Locked Loop (PLL) Characteristics ........................................................... 590
Table 20-9. Actual PLL Frequency ........................................................................................ 590
Table 20-10. Clock Characteristics ......................................................................................... 590
Table 20-11. Crystal Characteristics ....................................................................................... 591
Table 20-12. JTAG Characteristics ......................................................................................... 591
Table 20-13. Reset Characteristics ......................................................................................... 593
Table 20-14. Sleep Modes AC Characteristics ......................................................................... 595
Table 20-15. Hibernation Module AC Characteristics ............................................................... 595
Table 20-16. GPIO Characteristics ......................................................................................... 596
Table 20-17. SSI Characteristics ............................................................................................ 596
Table 20-18. I2C Characteristics ............................................................................................. 597
Table 20-19. Analog Comparator Characteristics ..................................................................... 598
Table 20-20. Analog Comparator Voltage Reference Characteristics ........................................ 598
Table C-1. Part Ordering Information ................................................................................... 625
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List of Registers
The Cortex-M3 Processor ............................................................................................................. 44
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 51
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 51
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 51
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 51
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 51
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 51
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 51
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 51
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 51
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 51
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 51
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 51
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 51
Register 14: Stack Pointer (SP) ........................................................................................................... 52
Register 15: Link Register (LR) ............................................................................................................ 53
Register 16: Program Counter (PC) ..................................................................................................... 54
Register 17: Program Status Register (PSR) ........................................................................................ 55
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 59
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 60
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 61
Register 21: Control Register (CONTROL) ........................................................................................... 62
Cortex-M3 Peripherals ................................................................................................................... 86
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ............................................. 97
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 ................................................ 99
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 100
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 101
Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104 ................................................................ 102
Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 103
Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184 ............................................................ 104
Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 105
Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204 ......................................................... 106
Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 107
Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 .................................................. 108
Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 109
Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 ........................................................... 110
Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 111
Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 111
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 111
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 111
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 111
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 111
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 111
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 111
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 111
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Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 111
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 111
Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 113
Register 26: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 114
Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 115
Register 28: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 119
Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 120
Register 30: System Control (SYSCTRL), offset 0xD10 ....................................................................... 122
Register 31: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 124
Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 126
Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 127
Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 128
Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 129
Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 133
Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 139
Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 141
Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 142
Register 40: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 143
Register 41: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 144
Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 146
Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 147
Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 147
Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 147
Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 147
Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 149
Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 149
Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 149
Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 149
System Control ............................................................................................................................ 164
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 178
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 180
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 181
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 182
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 183
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 184
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 185
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 186
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 190
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 191
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 193
Register 12: Device Identification 1 (DID1), offset 0x004 ..................................................................... 194
Register 13: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 196
Register 14: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 197
Register 15: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 199
Register 16: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 201
Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 203
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 204
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 206
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Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 208
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 210
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 213
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 216
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 219
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 221
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 223
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 225
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 226
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 228
Hibernation Module ..................................................................................................................... 229
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 237
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 238
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 239
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 240
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 241
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 243
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 244
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 245
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 246
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 247
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 248
Internal Memory ........................................................................................................................... 249
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 255
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 256
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 257
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 259
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 260
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 261
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 263
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 264
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 265
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 266
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 267
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 268
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 269
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 270
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 271
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 272
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 273
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 274
General-Purpose Input/Outputs (GPIOs) ................................................................................... 275
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 282
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 283
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 284
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 285
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 286
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 287
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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 288
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 289
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 290
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 291
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 293
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 294
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 295
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 296
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 297
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 298
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 299
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 300
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 301
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 302
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 304
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 305
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 306
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 307
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 308
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 309
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 310
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 311
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 312
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 313
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 314
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 315
General-Purpose Timers ............................................................................................................. 316
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 328
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 329
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 331
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 333
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 336
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 338
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 339
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 340
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 342
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 343
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 344
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 345
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 346
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 347
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 348
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 349
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 350
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 351
Watchdog Timer ........................................................................................................................... 352
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 356
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 357
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Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 358
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 359
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 360
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 361
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 362
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 363
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 364
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 365
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 366
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 367
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 368
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 369
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 370
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 371
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 372
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 373
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 374
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 375
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 376
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 384
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 386
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 388
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 390
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 391
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 392
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 393
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 395
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 397
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 399
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 401
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 402
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 403
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 405
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 406
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 407
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 408
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 409
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 410
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 411
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 412
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 413
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 414
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 415
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 416
Synchronous Serial Interface (SSI) ............................................................................................ 417
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 429
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 431
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 433
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Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 434
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 436
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 437
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 439
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 440
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 441
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 442
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 443
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 444
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 445
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 446
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 447
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 448
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 449
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 450
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 451
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 452
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 453
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 454
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 469
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 470
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 474
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 475
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 476
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 477
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 478
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 479
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 480
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 482
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 483
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 485
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 486
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 487
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 488
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 489
Analog Comparators ................................................................................................................... 490
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 495
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 496
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 497
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 498
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 499
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 499
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 ..................................................... 499
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 500
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 500
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 .................................................... 500
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Pulse Width Modulator (PWM) .................................................................................................... 502
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 511
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 512
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 513
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 514
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 515
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 516
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 517
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 518
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 519
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 520
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 520
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 520
Register 13: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044 ...................................................... 522
Register 14: PWM1 Interrupt Enable (PWM1INTEN), offset 0x084 ...................................................... 522
Register 15: PWM2 InterruptEnable (PWM2INTEN), offset 0x0C4 ...................................................... 522
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 524
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 524
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 524
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 525
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 525
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 525
Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 526
Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 526
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 526
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 527
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 527
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 527
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 528
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 528
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 528
Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 529
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 529
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 529
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 530
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 530
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 530
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 533
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 533
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 533
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 536
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 536
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 536
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 537
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 537
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 537
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 538
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 538
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Table of Contents
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 538
Quadrature Encoder Interface (QEI) .......................................................................................... 539
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 544
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 546
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 547
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 548
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 549
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 550
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 551
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 552
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 553
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 554
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 555
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Revision History
The revision history table notes changes made between the indicated revisions of the LM3S1150
data sheet.
Table 1. Revision History
DescriptionRevisionDate
7787September 2010
■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
■ Changed register names to be consistent with StellarisWare®names: the Cortex-M3 Interrupt
■ Added clarification of instruction execution during Flash operations.
■ Modified Figure 8-1 on page 276 to clarify operation of the GPIO inputs when used as an alternate
■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits
Stellaris® LM3S1150 Microcontroller
new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
added, including all the Cortex-M3 registers.
Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and
the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0)
register.
function.
wide, bits[7:0].
■ Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes
the JTAG controller to be reset, resulting in a loss of JTAG communication.
■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
■ In Electrical Characteristics chapter:
– Added I
– Corrected values for t
■ Added dimensions for Tray and Tape and Reel shipping mediums.
7393June 2010
7007April 2010
■ Corrected base address for SRAM in architectural overview chapter.
■ Clarified system clock operation, adding content to “Clock Control” on page 168.
■ In Signal Tables chapter, added table "Connections for Unused Signals."
■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.
■ Additional minor data sheet clarifications and corrections.
■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■ Removed erroneous text about restoring the Flash Protection registers.
■ Added note about RST signal routing.
■ Clarified the function of the TnSTALL bit in the GPTMCTL register.
parameter (GPIO input leakage current) to Table 20-4 on page 587.
LKG
parameter (SSIClk rise/fall time) in Table 20-17 on page 596.
CLKRF
■ Additional minor data sheet clarifications and corrections.
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Revision History
Table 1. Revision History (continued)
DescriptionRevisionDate
6712January 2010
■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.
■ Clarified wording on Flash memory access errors.
■ Added section on Flash interrupts.
■ Clarified operation of SSI transmit FIFO.
■ Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■ Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
6462October 2009
■ Removed erroneous reference to the WRC bit in the Hibernation chapter.
■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
■ Made these changes to the Electrical Characteristics chapter:
– Removed V
SIH
and V
parameters from Operating Conditions table.
SIL
– Added table showing actual PLL frequency depending on input crystal.
– Changed the name of the t
HIB_REG_WRITE
parameter to t
HIB_REG_ACCESS
.
– Changed SSI set up and hold times to be expressed in system clocks, not ns.
Corrected ordering numbers.5920July 2009
5902July 2009
■ Clarified Power-on reset and RST pin operation; added new diagrams.
■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)
registers.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.
■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added E
IR
(Internal voltage reference error) parameter.
■ Additional minor data sheet clarifications and corrections.
5367April 2009
■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 158).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Added "GPIO Module DC Characteristics" table (see Table 20-4 on page 587).
■ Additional minor data sheet clarifications and corrections.
September 04, 201022
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Table 1. Revision History (continued)
DescriptionRevisionDate
4660January 2009
■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Additional minor data sheet clarifications and corrections.
Stellaris® LM3S1150 Microcontroller
4283November 2008
■ Revised High-Level Block Diagram.
■ Additional minor data sheet clarifications and corrections were made.
4149October 2008
■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.
■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
3447August 2008
■ Added note on clearing interrupts to Interrupts chapter.
■ Added Power Architecture diagram to System Control chapter.
■ Additional minor data sheet clarifications and corrections.
■ Additional minor data sheet clarifications and corrections.3108July 2008
2972May 2008
■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
the LDO output as the source of VDD25 input.
■ Additional minor data sheet clarifications and corrections.
2881April 2008 ■ The ΘJAvalue was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating
Characteristics chapter.
■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of
1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.
■ Values for I
DD_HIBERNATE
were added to the "Detailed Power Specifications" table in the "Electrical
Characteristics" chapter.
■ The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter.
■ The T
parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter
VDDRISE
was changed from a max of 100 to 250.
■ The maximum value on Core supply voltage (V
) in the "Maximum Ratings" table in the "Electrical
DD25
Characteristics" chapter was changed from 4 to 3.
■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data
sheets incorrectly noted it as 30 kHz ± 30%).
■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is
the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value.
■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly
noted the reset was 0x0 (MOSC).
■ Two figures on clock source were added to the "Hibernation Module":
– Clock Source Using Crystal
23September 04, 2010
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Revision History
Table 1. Revision History (continued)
DescriptionRevisionDate
– Clock Source Using Dedicated Oscillator
■ The following notes on battery management were added to the "Hibernation Module" chapter:
– Battery voltage is not measured while in Hibernate mode.
– System level factors may affect the accuracy of the low battery detect circuit. The designer
should consider battery type, discharge characteristics, and a test load during battery voltage
measurements.
■ A note on high-current applications was added to the GPIO chapter:
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
■ A note on Schmitt inputs was added to the GPIO chapter:
Pins configured as digital inputs are Schmitt-triggered.
■ The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.
■ The "Differential Sampling Range" figures in the ADC chapter were clarified.
■ The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected:
– The LQFP pin diagrams and pin tables were missing the comparator positive and negative input
pins.
– The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.
■ Additional minor data sheet clarifications and corrections.
Started tracking revision history.2550March 2008
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About This Document
This data sheet provides reference information for the LM3S1150 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following related documents are available on the Stellaris®web site at www.ti.com/stellaris:
■
Stellaris® Errata
Stellaris® LM3S1150 Microcontroller
■
ARM® Cortex™-M3 Errata
■
Cortex™-M3 Instruction Set Technical User's Manual
■
Stellaris® Graphics Library User's Guide
■
Stellaris® Peripheral Driver Library User's Guide
The following related documents are also referenced:
■
ARM® Debug Interface V5 Architecture Specification
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
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About This Document
Documentation Conventions
This document uses the conventions shown in Table 2 on page 26.
Table 2. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
reserved
yy:xx
Register Bit/Field
Types
R/W1C
R/W1S
W1C
Reset Value
Pin/Signal Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 63.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. Writing to it with any value clears the register.R/WC
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
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Table 2. Documentation Conventions (continued)
MeaningNotation
Refers to the electrical signal encoding of a pin.signal
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Stellaris® LM3S1150 Microcontroller
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Architectural Overview
1 Architectural Overview
The Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings
high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These
pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit
devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities.
The LM3S1150 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S1150 microcontroller features
a battery-backed Hibernation module to efficiently power down the LM3S1150 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S1150 microcontroller perfectly for
battery applications.
In addition, the LM3S1150 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S1150 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact
Information” on page 625 for ordering information for Stellaris®family devices.
1.1 Product Features
The LM3S1150 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
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Stellaris® LM3S1150 Microcontroller
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 34 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ ARM® Cortex™-M3 Processor Core
– Compact core.
– Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
memory size usually associated with 8- and 16-bit devices; typically in the range of a few
kilobytes of memory for microcontroller class applications.
– Rapid application execution through Harvard architecture characterized by separate buses
for instruction and data.
– Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
– Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
– Memory protection unit (MPU) to provide a privileged mode of operation for complex
applications.
– Migration from the ARM7™ processor family for better performance and power efficiency.
– Full-featured debug solution
• Serial Wire JTAG Debug Port (SWJ-DP)
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
• Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
– Optimized for single-cycle flash usage
– Three sleep modes with clock gating for low power
– Single-cycle multiply instruction and hardware divide
– Atomic operations
– ARM Thumb2 mixed 16-/32-bit instruction set
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Architectural Overview
– 1.25 DMIPS/MHz
■ JTAG
– IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
– Four-bit Instruction Register (IR) chain for storing JTAG instructions
– IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
– ARM additional instructions: APACC, DPACC and ABORT
– Integrated ARM Serial Wire Debug (SWD)
■ Hibernation
– System power control using discrete external regulator
– Dedicated pin for waking from an external signal
– Low-battery detection, signaling, and interrupt generation
– 32-bit real-time clock (RTC)
– Two 32-bit RTC match registers for timed wake-up and interrupt generation
– Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
– RTC predivider trim for making fine adjustments to the clock rate
– 64 32-bit words of non-volatile memory
– Programmable interrupts for RTC match, external wake, and low battery events
■ Internal Memory
– 64 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 16 KB single-cycle SRAM
■ GPIOs
– 7-52 GPIOs, depending on configuration
– 5-V-tolerant in input configuration
– Programmable control for GPIO interrupts
• Interrupt generation masking
• Edge-triggered on rising, falling, or both
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