Texas instruments STELLARIS LM3S1138 DATA SHEET
TEXAS INSTRUMENTS-PRODUCTION DATA
Stellaris® LM3S1138 Microcontroller
DATA SHEET
DS-LM3S1138-7393
Copyright © 2007-2010 Texas Instruments
Incorporated
Copyright
Copyright ©2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments
Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the
property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor
products and disclaimers thereto appears at the end of this data sheet.
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Austin, TX 78746
http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Table of Contents
Revision History ............................................................................................................................. 18
About This Document .................................................................................................................... 22
Audience .............................................................................................................................................. 22
About This Manual ................................................................................................................................ 22
Related Documents ............................................................................................................................... 22
Documentation Conventions .................................................................................................................. 23
1 Architectural Overview .......................................................................................... 25
1.1 Product Features .......................................................................................................... 25
1.2 Target Applications ........................................................................................................ 32
1.3 High-Level Block Diagram ............................................................................................. 32
1.4 Functional Overview ...................................................................................................... 34
1.4.1 ARM Cortex™-M3 ......................................................................................................... 34
1.4.2 Motor Control Peripherals .............................................................................................. 34
1.4.3 Analog Peripherals ........................................................................................................ 35
1.4.4 Serial Communications Peripherals ................................................................................ 36
1.4.5 System Peripherals ....................................................................................................... 37
1.4.6 Memory Peripherals ...................................................................................................... 38
1.4.7 Additional Features ....................................................................................................... 38
1.4.8 Hardware Details .......................................................................................................... 39
2 ARM Cortex-M3 Processor Core ........................................................................... 40
2.1 Block Diagram .............................................................................................................. 41
2.2 Functional Description ................................................................................................... 41
2.2.1 Serial Wire and JTAG Debug ......................................................................................... 41
2.2.2 Embedded Trace Macrocell (ETM) ................................................................................. 42
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 42
2.2.4 ROM Table ................................................................................................................... 42
2.2.5 Memory Protection Unit (MPU) ....................................................................................... 42
2.2.6 Nested Vectored Interrupt Controller (NVIC) .................................................................... 42
3 Memory Map ........................................................................................................... 46
4 Interrupts ................................................................................................................. 48
5 JTAG Interface ........................................................................................................ 51
5.1 Block Diagram .............................................................................................................. 52
5.2 Functional Description ................................................................................................... 52
5.2.1 JTAG Interface Pins ...................................................................................................... 52
5.2.2 JTAG TAP Controller ..................................................................................................... 54
5.2.3 Shift Registers .............................................................................................................. 55
5.2.4 Operational Considerations ............................................................................................ 55
5.3 Initialization and Configuration ....................................................................................... 58
5.4 Register Descriptions .................................................................................................... 58
5.4.1 Instruction Register (IR) ................................................................................................. 58
5.4.2 Data Registers .............................................................................................................. 60
6 System Control ....................................................................................................... 63
6.1 Functional Description ................................................................................................... 63
6.1.1 Device Identification ...................................................................................................... 63
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6.1.2 Reset Control ................................................................................................................ 63
6.1.3 Power Control ............................................................................................................... 66
6.1.4 Clock Control ................................................................................................................ 67
6.1.5 System Control ............................................................................................................. 72
6.2 Initialization and Configuration ....................................................................................... 73
6.3 Register Map ................................................................................................................ 74
6.4 Register Descriptions .................................................................................................... 75
7 Hibernation Module .............................................................................................. 128
7.1 Block Diagram ............................................................................................................ 129
7.2 Functional Description ................................................................................................. 129
7.2.1 Register Access Timing ............................................................................................... 129
7.2.2 Clock Source .............................................................................................................. 130
7.2.3 Battery Management ................................................................................................... 131
7.2.4 Real-Time Clock .......................................................................................................... 131
7.2.5 Non-Volatile Memory ................................................................................................... 132
7.2.6 Power Control ............................................................................................................. 132
7.2.7 Initiating Hibernate ...................................................................................................... 132
7.2.8 Interrupts and Status ................................................................................................... 133
7.3 Initialization and Configuration ..................................................................................... 133
7.3.1 Initialization ................................................................................................................. 133
7.3.2 RTC Match Functionality (No Hibernation) .................................................................... 133
7.3.3 RTC Match/Wake-Up from Hibernation ......................................................................... 134
7.3.4 External Wake-Up from Hibernation .............................................................................. 134
7.3.5 RTC/External Wake-Up from Hibernation ...................................................................... 134
7.4 Register Map .............................................................................................................. 134
7.5 Register Descriptions .................................................................................................. 135
8 Internal Memory ................................................................................................... 148
8.1 Block Diagram ............................................................................................................ 148
8.2 Functional Description ................................................................................................. 148
8.2.1 SRAM Memory ............................................................................................................ 148
8.2.2 Flash Memory ............................................................................................................. 149
8.3 Flash Memory Initialization and Configuration ............................................................... 150
8.3.1 Flash Programming ..................................................................................................... 150
8.3.2 Nonvolatile Register Programming ............................................................................... 151
8.4 Register Map .............................................................................................................. 152
8.5 Flash Register Descriptions (Flash Control Offset) ......................................................... 152
8.6 Flash Register Descriptions (System Control Offset) ...................................................... 160
9 General-Purpose Input/Outputs (GPIOs) ........................................................... 173
9.1 Functional Description ................................................................................................. 173
9.1.1 Data Control ............................................................................................................... 174
9.1.2 Interrupt Control .......................................................................................................... 175
9.1.3 Mode Control .............................................................................................................. 176
9.1.4 Commit Control ........................................................................................................... 176
9.1.5 Pad Control ................................................................................................................. 176
9.1.6 Identification ............................................................................................................... 177
9.2 Initialization and Configuration ..................................................................................... 177
9.3 Register Map .............................................................................................................. 178
9.4 Register Descriptions .................................................................................................. 180
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10 General-Purpose Timers ...................................................................................... 215
10.1 Block Diagram ............................................................................................................ 216
10.2 Functional Description ................................................................................................. 217
10.2.1 GPTM Reset Conditions .............................................................................................. 217
10.2.2 32-Bit Timer Operating Modes ...................................................................................... 217
10.2.3 16-Bit Timer Operating Modes ...................................................................................... 218
10.3 Initialization and Configuration ..................................................................................... 222
10.3.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 222
10.3.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 223
10.3.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 223
10.3.4 16-Bit Input Edge Count Mode ..................................................................................... 224
10.3.5 16-Bit Input Edge Timing Mode .................................................................................... 224
10.3.6 16-Bit PWM Mode ....................................................................................................... 225
10.4 Register Map .............................................................................................................. 225
10.5 Register Descriptions .................................................................................................. 226
11 Watchdog Timer ................................................................................................... 251
11.1 Block Diagram ............................................................................................................ 252
11.2 Functional Description ................................................................................................. 252
11.3 Initialization and Configuration ..................................................................................... 253
11.4 Register Map .............................................................................................................. 253
11.5 Register Descriptions .................................................................................................. 254
12 Analog-to-Digital Converter (ADC) ..................................................................... 275
12.1 Block Diagram ............................................................................................................ 275
12.2 Functional Description ................................................................................................. 276
12.2.1 Sample Sequencers .................................................................................................... 276
12.2.2 Module Control ............................................................................................................ 277
12.2.3 Hardware Sample Averaging Circuit ............................................................................. 278
12.2.4 Analog-to-Digital Converter .......................................................................................... 278
12.2.5 Differential Sampling ................................................................................................... 278
12.2.6 Test Modes ................................................................................................................. 280
12.2.7 Internal Temperature Sensor ........................................................................................ 281
12.3 Initialization and Configuration ..................................................................................... 281
12.3.1 Module Initialization ..................................................................................................... 281
12.3.2 Sample Sequencer Configuration ................................................................................. 282
12.4 Register Map .............................................................................................................. 282
12.5 Register Descriptions .................................................................................................. 283
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 311
13.1 Block Diagram ............................................................................................................ 312
13.2 Functional Description ................................................................................................. 312
13.2.1 Transmit/Receive Logic ............................................................................................... 312
13.2.2 Baud-Rate Generation ................................................................................................. 313
13.2.3 Data Transmission ...................................................................................................... 314
13.2.4 Serial IR (SIR) ............................................................................................................. 314
13.2.5 FIFO Operation ........................................................................................................... 315
13.2.6 Interrupts .................................................................................................................... 315
13.2.7 Loopback Operation .................................................................................................... 316
13.2.8 IrDA SIR block ............................................................................................................ 316
13.3 Initialization and Configuration ..................................................................................... 316
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13.4 Register Map .............................................................................................................. 317
13.5 Register Descriptions .................................................................................................. 318
14 Synchronous Serial Interface (SSI) .................................................................... 352
14.1 Block Diagram ............................................................................................................ 352
14.2 Functional Description ................................................................................................. 353
14.2.1 Bit Rate Generation ..................................................................................................... 353
14.2.2 FIFO Operation ........................................................................................................... 353
14.2.3 Interrupts .................................................................................................................... 353
14.2.4 Frame Formats ........................................................................................................... 354
14.3 Initialization and Configuration ..................................................................................... 361
14.4 Register Map .............................................................................................................. 362
14.5 Register Descriptions .................................................................................................. 363
15 Inter-Integrated Circuit (I2C) Interface ................................................................ 389
15.1 Block Diagram ............................................................................................................ 390
15.2 Functional Description ................................................................................................. 390
15.2.1 I2C Bus Functional Overview ........................................................................................ 390
15.2.2 Available Speed Modes ............................................................................................... 392
15.2.3 Interrupts .................................................................................................................... 393
15.2.4 Loopback Operation .................................................................................................... 394
15.2.5 Command Sequence Flow Charts ................................................................................ 394
15.3 Initialization and Configuration ..................................................................................... 401
15.4 Register Map .............................................................................................................. 402
15.5 Register Descriptions (I2C Master) ............................................................................... 403
15.6 Register Descriptions (I2C Slave) ................................................................................. 416
16 Analog Comparators ............................................................................................ 425
16.1 Block Diagram ............................................................................................................ 426
16.2 Functional Description ................................................................................................. 426
16.2.1 Internal Reference Programming .................................................................................. 427
16.3 Initialization and Configuration ..................................................................................... 428
16.4 Register Map .............................................................................................................. 428
16.5 Register Descriptions .................................................................................................. 429
17 Pin Diagram .......................................................................................................... 437
18 Signal Tables ........................................................................................................ 439
18.1 100-Pin LQFP Package Pin Tables ............................................................................... 439
18.2 108-Pin BGA Package Pin Tables ................................................................................ 451
18.3 Connections for Unused Signals ................................................................................... 464
19 Operating Characteristics ................................................................................... 467
20 Electrical Characteristics .................................................................................... 468
20.1 DC Characteristics ...................................................................................................... 468
20.1.1 Maximum Ratings ....................................................................................................... 468
20.1.2 Recommended DC Operating Conditions ...................................................................... 468
20.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 469
20.1.4 GPIO Module Characteristics ....................................................................................... 469
20.1.5 Power Specifications ................................................................................................... 469
20.1.6 Flash Memory Characteristics ...................................................................................... 471
20.1.7 Hibernation ................................................................................................................. 471
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20.2 AC Characteristics ....................................................................................................... 471
20.2.1 Load Conditions .......................................................................................................... 471
20.2.2 Clocks ........................................................................................................................ 472
20.2.3 JTAG and Boundary Scan ............................................................................................ 473
20.2.4 Reset ......................................................................................................................... 475
20.2.5 Sleep Modes ............................................................................................................... 477
20.2.6 Hibernation Module ..................................................................................................... 477
20.2.7 General-Purpose I/O (GPIO) ........................................................................................ 478
20.2.8 Analog-to-Digital Converter .......................................................................................... 478
20.2.9 Synchronous Serial Interface (SSI) ............................................................................... 479
20.2.10 Inter-Integrated Circuit (I2C) Interface ........................................................................... 481
20.2.11 Analog Comparator ..................................................................................................... 482
A Serial Flash Loader .............................................................................................. 483
A.1 Serial Flash Loader ..................................................................................................... 483
A.2 Interfaces ................................................................................................................... 483
A.2.1 UART ......................................................................................................................... 483
A.2.2 SSI ............................................................................................................................. 483
A.3 Packet Handling .......................................................................................................... 484
A.3.1 Packet Format ............................................................................................................ 484
A.3.2 Sending Packets ......................................................................................................... 484
A.3.3 Receiving Packets ....................................................................................................... 484
A.4 Commands ................................................................................................................. 485
A.4.1 COMMAND_PING (0X20) ............................................................................................ 485
A.4.2 COMMAND_GET_STATUS (0x23) ............................................................................... 485
A.4.3 COMMAND_DOWNLOAD (0x21) ................................................................................. 485
A.4.4 COMMAND_SEND_DATA (0x24) ................................................................................. 486
A.4.5 COMMAND_RUN (0x22) ............................................................................................. 486
A.4.6 COMMAND_RESET (0x25) ......................................................................................... 486
B Register Quick Reference ................................................................................... 488
C Ordering and Contact Information ..................................................................... 503
C.1 Ordering Information .................................................................................................... 503
C.2 Part Markings .............................................................................................................. 503
C.3 Kits ............................................................................................................................. 504
C.4 Support Information ..................................................................................................... 504
D Package Information ............................................................................................ 505
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Table of Contents
List of Figures
Figure 1-1. Stellaris®LM3S1138 Microcontroller High-Level Block Diagram ............................. 33
Figure 2-1. CPU Block Diagram ............................................................................................. 41
Figure 2-2. TPIU Block Diagram ............................................................................................ 42
Figure 5-1. JTAG Module Block Diagram ................................................................................ 52
Figure 5-2. Test Access Port State Machine ........................................................................... 55
Figure 5-3. IDCODE Register Format ..................................................................................... 61
Figure 5-4. BYPASS Register Format .................................................................................... 61
Figure 5-5. Boundary Scan Register Format ........................................................................... 62
Figure 6-1. Basic RST Configuration ...................................................................................... 64
Figure 6-2. External Circuitry to Extend Power-On Reset ........................................................ 65
Figure 6-3. Reset Circuit Controlled by Switch ........................................................................ 65
Figure 6-4. Power Architecture .............................................................................................. 67
Figure 6-5. Main Clock Tree .................................................................................................. 69
Figure 7-1. Hibernation Module Block Diagram ..................................................................... 129
Figure 7-2. Clock Source Using Crystal ................................................................................ 130
Figure 7-3. Clock Source Using Dedicated Oscillator ............................................................. 131
Figure 8-1. Flash Block Diagram .......................................................................................... 148
Figure 9-1. GPIO Port Block Diagram ................................................................................... 174
Figure 9-2. GPIODATA Write Example ................................................................................. 175
Figure 9-3. GPIODATA Read Example ................................................................................. 175
Figure 10-1. GPTM Module Block Diagram ............................................................................ 216
Figure 10-2. 16-Bit Input Edge Count Mode Example .............................................................. 220
Figure 10-3. 16-Bit Input Edge Time Mode Example ............................................................... 221
Figure 10-4. 16-Bit PWM Mode Example ................................................................................ 222
Figure 11-1. WDT Module Block Diagram .............................................................................. 252
Figure 12-1. ADC Module Block Diagram ............................................................................... 276
Figure 12-2. Differential Sampling Range, V
Figure 12-3. Differential Sampling Range, V
Figure 12-4. Differential Sampling Range, V
Figure 12-5. Internal Temperature Sensor Characteristic ......................................................... 281
Figure 13-1. UART Module Block Diagram ............................................................................. 312
Figure 13-2. UART Character Frame ..................................................................................... 313
Figure 13-3. IrDA Data Modulation ......................................................................................... 315
Figure 14-1. SSI Module Block Diagram ................................................................................. 352
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 355
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 355
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 356
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 356
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 357
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 358
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 358
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 359
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 360
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 361
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 361
IN_ODD
IN_ODD
IN_ODD
= 1.5 V ...................................................... 279
= 0.75 V .................................................... 280
= 2.25 V .................................................... 280
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Figure 15-1. I2C Block Diagram ............................................................................................. 390
Figure 15-2. I2C Bus Configuration ........................................................................................ 390
Figure 15-3. START and STOP Conditions ............................................................................. 391
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 391
Figure 15-5. R/S Bit in First Byte ............................................................................................ 391
Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 392
Figure 15-7. Master Single SEND .......................................................................................... 395
Figure 15-8. Master Single RECEIVE ..................................................................................... 396
Figure 15-9. Master Burst SEND ........................................................................................... 397
Figure 15-10. Master Burst RECEIVE ...................................................................................... 398
Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 399
Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 400
Figure 15-13. Slave Command Sequence ................................................................................ 401
Figure 16-1. Analog Comparator Module Block Diagram ......................................................... 426
Figure 16-2. Structure of Comparator Unit .............................................................................. 427
Figure 16-3. Comparator Internal Reference Structure ............................................................ 427
Figure 17-1. 100-Pin LQFP Package Pin Diagram .................................................................. 437
Figure 17-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 438
Figure 20-1. Load Conditions ................................................................................................ 472
Figure 20-2. JTAG Test Clock Input Timing ............................................................................. 474
Figure 20-3. JTAG Test Access Port (TAP) Timing .................................................................. 475
Figure 20-4. JTAG TRST Timing ............................................................................................ 475
Figure 20-5. External Reset Timing (RST) .............................................................................. 476
Figure 20-6. Power-On Reset Timing ..................................................................................... 476
Figure 20-7. Brown-Out Reset Timing .................................................................................... 476
Figure 20-8. Software Reset Timing ....................................................................................... 476
Figure 20-9. Watchdog Reset Timing ..................................................................................... 477
Figure 20-10. Hibernation Module Timing ................................................................................. 478
Figure 20-11. ADC Input Equivalency Diagram ......................................................................... 479
Figure 20-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 480
Figure 20-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 480
Figure 20-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 481
Figure 20-15. I2C Timing ......................................................................................................... 482
Figure D-1. 100-Pin LQFP Package ...................................................................................... 505
Figure D-2. 108-Ball BGA Package ...................................................................................... 507
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Table of Contents
List of Tables
Table 1. Revision History .................................................................................................. 18
Table 2. Documentation Conventions ................................................................................ 23
Table 3-1. Memory Map ....................................................................................................... 46
Table 4-1. Exception Types .................................................................................................. 48
Table 4-2. Interrupts ............................................................................................................ 49
Table 5-1. JTAG Port Pins Reset State ................................................................................. 53
Table 5-2. JTAG Instruction Register Commands ................................................................... 58
Table 6-1. Clock Source Options .......................................................................................... 68
Table 6-2. Possible System Clock Frequencies Using the SYSDIV Field ................................. 70
Table 6-3. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field ............ 70
Table 6-4. System Control Register Map ............................................................................... 74
Table 6-5. RCC2 Fields that Override RCC fields .................................................................. 89
Table 7-1. Hibernation Module Register Map ....................................................................... 134
Table 8-1. Flash Protection Policy Combinations ................................................................. 149
Table 8-2. User-Programmable Flash Memory Resident Registers ....................................... 151
Table 8-3. Flash Register Map ............................................................................................ 152
Table 9-1. GPIO Pad Configuration Examples ..................................................................... 177
Table 9-2. GPIO Interrupt Configuration Example ................................................................ 177
Table 9-3. GPIO Register Map ........................................................................................... 179
Table 10-1. Available CCP Pins ............................................................................................ 216
Table 10-2. 16-Bit Timer With Prescaler Configurations ......................................................... 219
Table 10-3. Timers Register Map .......................................................................................... 225
Table 11-1. Watchdog Timer Register Map ............................................................................ 253
Table 12-1. Samples and FIFO Depth of Sequencers ............................................................ 276
Table 12-2. Differential Sampling Pairs ................................................................................. 278
Table 12-3. ADC Register Map ............................................................................................. 282
Table 13-1. UART Register Map ........................................................................................... 317
Table 14-1. SSI Register Map .............................................................................................. 362
Table 15-1. Examples of I2C Master Timer Period versus Speed Mode ................................... 393
Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 402
Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) .................................... 407
Table 16-1. Internal Reference Voltage and ACREFCTL Field Values ..................................... 427
Table 16-2. Analog Comparators Register Map ..................................................................... 429
Table 18-1. Signals by Pin Number ....................................................................................... 439
Table 18-2. Signals by Signal Name ..................................................................................... 443
Table 18-3. Signals by Function, Except for GPIO ................................................................. 447
Table 18-4. GPIO Pins and Alternate Functions ..................................................................... 450
Table 18-5. Signals by Pin Number ....................................................................................... 451
Table 18-6. Signals by Signal Name ..................................................................................... 456
Table 18-7. Signals by Function, Except for GPIO ................................................................. 460
Table 18-8. GPIO Pins and Alternate Functions ..................................................................... 463
Table 18-9. Connections for Unused Signals (100-pin LQFP) ................................................. 465
Table 18-10. Connections for Unused Signals, 108-pin BGA .................................................... 465
Table 19-1. Temperature Characteristics ............................................................................... 467
Table 19-2. Thermal Characteristics ..................................................................................... 467
Table 19-3. ESD Absolute Maximum Ratings ........................................................................ 467
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Table 20-1. Maximum Ratings .............................................................................................. 468
Table 20-2. Recommended DC Operating Conditions ............................................................ 468
Table 20-3. LDO Regulator Characteristics ........................................................................... 469
Table 20-4. GPIO Module DC Characteristics ........................................................................ 469
Table 20-5. Detailed Power Specifications ............................................................................ 470
Table 20-6. Flash Memory Characteristics ............................................................................ 471
Table 20-7. Hibernation Module DC Characteristics ............................................................... 471
Table 20-8. Phase Locked Loop (PLL) Characteristics ........................................................... 472
Table 20-9. Actual PLL Frequency ........................................................................................ 472
Table 20-10. Clock Characteristics ......................................................................................... 472
Table 20-11. Crystal Characteristics ....................................................................................... 473
Table 20-12. System Clock Characteristics with ADC Operation ............................................... 473
Table 20-13. JTAG Characteristics ......................................................................................... 473
Table 20-14. Reset Characteristics ......................................................................................... 475
Table 20-15. Sleep Modes AC Characteristics ......................................................................... 477
Table 20-16. Hibernation Module AC Characteristics ............................................................... 477
Table 20-17. GPIO Characteristics ......................................................................................... 478
Table 20-18. ADC Characteristics ........................................................................................... 478
Table 20-19. ADC Module Internal Reference Characteristics .................................................. 479
Table 20-20. SSI Characteristics ............................................................................................ 479
Table 20-21. I2C Characteristics ............................................................................................. 481
Table 20-22. Analog Comparator Characteristics ..................................................................... 482
Table 20-23. Analog Comparator Voltage Reference Characteristics ........................................ 482
Table C-1. Part Ordering Information ................................................................................... 503
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Table of Contents
List of Registers
System Control .............................................................................................................................. 63
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 76
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 78
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 79
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 80
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 81
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 82
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 83
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 84
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 88
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 89
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 91
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 92
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 94
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 95
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 97
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 99
Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 102
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 103
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 105
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 107
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 109
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 112
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 115
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 118
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 120
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 122
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 124
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 125
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 127
Hibernation Module ..................................................................................................................... 128
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 136
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 137
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 138
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 139
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 140
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 142
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 143
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 144
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 145
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 146
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 147
Internal Memory ........................................................................................................................... 148
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 153
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 154
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Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 155
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 157
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 158
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 159
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 161
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 162
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 163
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 164
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 165
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 166
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 167
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 168
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 169
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 170
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 171
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 172
General-Purpose Input/Outputs (GPIOs) ................................................................................... 173
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 181
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 182
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 183
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 184
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 185
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 186
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 187
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 188
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 189
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 190
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 192
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 193
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 194
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 195
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 196
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 197
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 198
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 199
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 200
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 201
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 203
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 204
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 205
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 206
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 207
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 208
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 209
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 210
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 211
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 212
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 213
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Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 214
General-Purpose Timers ............................................................................................................. 215
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 227
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 228
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 230
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 232
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 235
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 237
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 238
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 239
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 241
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 242
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 243
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 244
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 245
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 246
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 247
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 248
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 249
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 250
Watchdog Timer ........................................................................................................................... 251
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 255
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 256
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 257
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 258
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 259
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 260
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 261
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 262
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 263
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 264
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 265
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 266
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 267
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 268
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 269
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 270
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 271
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 272
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 273
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 274
Analog-to-Digital Converter (ADC) ............................................................................................. 275
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 284
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 285
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 286
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 287
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 289
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 290
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Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 293
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 294
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 296
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 297
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 298
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 300
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 303
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 303
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 303
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 303
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 304
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 304
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 304
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 304
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 305
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 305
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 306
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 306
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 308
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 309
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 310
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 311
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 319
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 321
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 323
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 325
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 326
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 327
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 328
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 330
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 332
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 334
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 336
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 337
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 338
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 340
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 341
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 342
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 343
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 344
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 345
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 346
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 347
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 348
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 349
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 350
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 351
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Table of Contents
Synchronous Serial Interface (SSI) ............................................................................................ 352
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 364
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 366
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 368
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 369
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 371
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 372
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 374
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 375
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 376
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 377
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 378
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 379
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 380
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 381
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 382
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 383
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 384
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 385
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 386
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 387
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 388
Inter-Integrated Circuit (I2C) Interface ........................................................................................ 389
Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 404
Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 405
Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 409
Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 410
Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 411
Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 412
Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 413
Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 414
Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 415
Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 417
Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 418
Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 420
Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 421
Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 422
Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 423
Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 424
Analog Comparators ................................................................................................................... 425
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 430
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 431
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 432
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 433
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 434
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 434
Register 7: Analog Comparator Status 2 (ACSTAT2), offset 0x060 ..................................................... 434
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Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 435
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 435
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 .................................................... 435
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Revision History
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S1138
data sheet.
Table 1. Revision History
DescriptionRevisionDate
7393June 2010
■ Corrected base address for SRAM in architectural overview chapter.
■ Clarified system clock operation, adding content to “Clock Control” on page 67.
■ In Signal Tables chapter, added table "Connections for Unused Signals."
■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.
■ Additional minor data sheet clarifications and corrections.
7007April 2010
6712January 2010
■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■ Removed erroneous text about restoring the Flash Protection registers.
■ Added note about RST signal routing.
■ Clarified the function of the TnSTALL bit in the GPTMCTL register.
■ Additional minor data sheet clarifications and corrections.
■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.
■ Clarified wording on Flash memory access errors.
■ Added section on Flash interrupts.
■ Changed the reset value of the ADC Sample Sequence Result FIFO n (ADCSSFIFOn) registers
to be indeterminate.
■ Clarified operation of SSI transmit FIFO.
■ Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■ Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
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Table 1. Revision History (continued)
DescriptionRevisionDate
6462October 2009
■ Deleted MAXADCSPD bit field from DCGC0 register as it is not applicable in Deep-Sleep mode.
■ Removed erroneous reference to the WRC bit in the Hibernation chapter.
■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
■ Clarified PWM source for ADC triggering.
■ Made these changes to the Electrical Characteristics chapter:
Stellaris® LM3S1138 Microcontroller
– Removed V
SIH
and V
parameters from Operating Conditions table.
SIL
– Added table showing actual PLL frequency depending on input crystal.
– Changed the name of the t
HIB_REG_WRITE
parameter to t
HIB_REG_ACCESS
.
– Revised ADC electrical specifications to clarify, including reorganizing and adding new data.
– Changed SSI set up and hold times to be expressed in system clocks, not ns.
Corrected ordering numbers.5920July 2009
5902July 2009
■ Clarified Power-on reset and RST pin operation; added new diagrams.
■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)
registers.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.
■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added E
IR
(Internal voltage reference error) parameter.
■ Additional minor data sheet clarifications and corrections.
5367April 2009
■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 57).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Added "GPIO Module DC Characteristics" table (see Table 20-4 on page 469).
■ Additional minor data sheet clarifications and corrections.
4660January 2009
■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Additional minor data sheet clarifications and corrections.
4283November 2008
■ Revised High-Level Block Diagram.
■ Additional minor data sheet clarifications and corrections were made.
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Revision History
Table 1. Revision History (continued)
DescriptionRevisionDate
4149October 2008
■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.
■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
3447August 2008
■ Added note on clearing interrupts to Interrupts chapter.
■ Added Power Architecture diagram to System Control chapter.
■ Additional minor data sheet clarifications and corrections.
■ Additional minor data sheet clarifications and corrections.3108July 2008
2972May 2008
■ The 108-Ball BGA pin diagram and pin tables had an error. The following signals were erroneously
indicated as available and have now been changed to a No Connect (NC):
– Ball C1: Changed PE7 to NC
– Ball C2: Changed PE6 to NC
– Ball D2: Changed PE5 to NC
– Ball D1: Changed PE4 to NC
– Ball F1: Changed PD7 to NC
– Ball F2: Changed PD6 to NC
– Ball E2: Changed PD5 to NC
– Ball E1: Changed PD4 to NC
■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
the LDO output as the source of VDD25 input.
■ Additional minor data sheet clarifications and corrections.
2881April 2008 ■ The ΘJAvalue was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating
Characteristics chapter.
■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of
1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.
■ Values for I
DD_HIBERNATE
were added to the "Detailed Power Specifications" table in the "Electrical
Characteristics" chapter.
■ The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter.
■ The T
parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter
VDDRISE
was changed from a max of 100 to 250.
■ The maximum value on Core supply voltage (V
) in the "Maximum Ratings" table in the "Electrical
DD25
Characteristics" chapter was changed from 4 to 3.
■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data
sheets incorrectly noted it as 30 kHz ± 30%).
■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is
the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value.
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Table 1. Revision History (continued)
DescriptionRevisionDate
■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly
noted the reset was 0x0 (MOSC).
■ Two figures on clock source were added to the "Hibernation Module":
– Clock Source Using Crystal
– Clock Source Using Dedicated Oscillator
■ The following notes on battery management were added to the "Hibernation Module" chapter:
– Battery voltage is not measured while in Hibernate mode.
– System level factors may affect the accuracy of the low battery detect circuit. The designer
should consider battery type, discharge characteristics, and a test load during battery voltage
measurements.
■ A note on high-current applications was added to the GPIO chapter:
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
Stellaris® LM3S1138 Microcontroller
■ A note on Schmitt inputs was added to the GPIO chapter:
Pins configured as digital inputs are Schmitt-triggered.
■ The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.
■ The "Differential Sampling Range" figures in the ADC chapter were clarified.
■ The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected:
– The LQFP pin diagrams and pin tables were missing the comparator positive and negative input
pins.
– The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.
■ Additional minor data sheet clarifications and corrections.
Started tracking revision history.2550March 2008
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About This Document
About This Document
This data sheet provides reference information for the LM3S1138 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following related documents are available on the documentation CD or from the Stellaris®web
site at www.ti.com/stellaris:
■
ARM® CoreSight Technical Reference Manual
■
ARM® Cortex™-M3 Errata
■
ARM® Cortex™-M3 Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
■
Stellaris® Graphics Library User's Guide
■
Stellaris® Peripheral Driver Library User's Guide
■
Stellaris® Errata
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
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Documentation Conventions
This document uses the conventions shown in Table 2 on page 23.
Table 2. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
reserved
yy:xx
Register Bit/Field
Types
R/W1C
R/W1S
W1C
Reset Value
Pin/Signal Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 46.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Stellaris® LM3S1138 Microcontroller
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About This Document
Table 2. Documentation Conventions (continued)
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
MeaningNotation
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
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1 Architectural Overview
The Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings
high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These
pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit
devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities.
The LM3S1138 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S1138 microcontroller features
a battery-backed Hibernation module to efficiently power down the LM3S1138 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S1138 microcontroller perfectly for
battery applications.
Stellaris® LM3S1138 Microcontroller
In addition, the LM3S1138 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S1138 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact
Information” on page 503 for ordering information for Stellaris®family devices.
1.1 Product Features
The LM3S1138 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
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Architectural Overview
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 34 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ ARM® Cortex™-M3 Processor Core
– Compact core.
– Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
memory size usually associated with 8- and 16-bit devices; typically in the range of a few
kilobytes of memory for microcontroller class applications.
– Rapid application execution through Harvard architecture characterized by separate buses
for instruction and data.
– Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
– Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
– Memory protection unit (MPU) to provide a privileged mode of operation for complex
applications.
– Migration from the ARM7™ processor family for better performance and power efficiency.
– Full-featured debug solution
• Serial Wire JTAG Debug Port (SWJ-DP)
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
• Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
– Optimized for single-cycle flash usage
– Three sleep modes with clock gating for low power
– Single-cycle multiply instruction and hardware divide
– Atomic operations
– ARM Thumb2 mixed 16-/32-bit instruction set
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Stellaris® LM3S1138 Microcontroller
– 1.25 DMIPS/MHz
■ JTAG
– IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
– Four-bit Instruction Register (IR) chain for storing JTAG instructions
– IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
– ARM additional instructions: APACC, DPACC and ABORT
– Integrated ARM Serial Wire Debug (SWD)
■ Hibernation
– System power control using discrete external regulator
– Dedicated pin for waking from an external signal
– Low-battery detection, signaling, and interrupt generation
– 32-bit real-time clock (RTC)
– Two 32-bit RTC match registers for timed wake-up and interrupt generation
– Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
– RTC predivider trim for making fine adjustments to the clock rate
– 64 32-bit words of non-volatile memory
– Programmable interrupts for RTC match, external wake, and low battery events
■ Internal Memory
– 64 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 16 KB single-cycle SRAM
■ GPIOs
– 9-46 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable control for GPIO interrupts
• Interrupt generation masking
• Edge-triggered on rising, falling, or both
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Architectural Overview
• Level-sensitive on High or Low values
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Pins configured as digital inputs are Schmitt-triggered.
– Programmable control for GPIO pad configuration
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ General-Purpose Timers
configured with an 18-mA pad drive for high-current applications
– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timers/counters. Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes
only)
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
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Stellaris® LM3S1138 Microcontroller
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ ADC
– Eight analog input channels
– Single-ended and differential-input configurations
– On-chip internal temperature sensor
– Sample rate of one million samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Flexible trigger control
• Controller (software)
• Timers
• Analog Comparators
• GPIO
– Hardware averaging of up to 64 samples for improved accuracy
– Converter uses an internal 3-V reference
– Power and ground for the analog circuitry is separate from the digital power and ground
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Architectural Overview
■ UART
– Three fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
– Programmable baud-rate generator allowing speeds up to 3.125 Mbps
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start bit detection
– Line-break generation and detection
– Fully programmable serial interface characteristics
• 5, 6, 7, or 8 data bits
• Even, odd, stick, or no-parity bit generation/detection
• 1 or 2 stop bit generation
– IrDA serial-IR (SIR) encoder/decoder providing
• Programmable use of IrDA Serial Infrared (SIR) or UART input/output
• Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
• Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
• Programmable internal clock generator enabling division of reference clock by 1 to 256
for low-power mode bit duration
■ Synchronous Serial Interface (SSI)
– Two SSI modules, each with the following features:
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ I2C
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