TEXAS INSTRUMENTS-PRODUCTION DATA
Stellaris® LM3S1110 Microcontroller
DATA SHEET
DS-LM3S1110-7787
Copyright © 2007-2010 Texas Instruments
Incorporated
Copyright
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property of others.
PRODUCTION DATA information is current as of publication date. Products conform to specications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
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products and disclaimers thereto appears at the end of this data sheet.
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http://www.ti.com/stellaris
http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm
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Table of Contents
Revision History ............................................................................................................................. 19
About This Document .................................................................................................................... 23
Audience .............................................................................................................................................. 23
About This Manual ................................................................................................................................ 23
Related Documents ............................................................................................................................... 23
Documentation Conventions .................................................................................................................. 24
1 Architectural Overview .......................................................................................... 26
1.1 Product Features .......................................................................................................... 26
1.2 Target Applications ........................................................................................................ 32
1.3 High-Level Block Diagram ............................................................................................. 32
1.4 Functional Overview ...................................................................................................... 34
1.4.1 ARM Cortex™-M3 ......................................................................................................... 34
1.4.2 Motor Control Peripherals .............................................................................................. 35
1.4.3 Analog Peripherals ........................................................................................................ 35
1.4.4 Serial Communications Peripherals ................................................................................ 35
1.4.5 System Peripherals ....................................................................................................... 36
1.4.6 Memory Peripherals ...................................................................................................... 37
1.4.7 Additional Features ....................................................................................................... 37
1.4.8 Hardware Details .......................................................................................................... 38
2 The Cortex-M3 Processor ...................................................................................... 39
2.1 Block Diagram .............................................................................................................. 40
2.2 Overview ...................................................................................................................... 41
2.2.1 System-Level Interface .................................................................................................. 41
2.2.2 Integrated Configurable Debug ...................................................................................... 41
2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 42
2.2.4 Cortex-M3 System Component Details ........................................................................... 42
2.3 Programming Model ...................................................................................................... 43
2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 43
2.3.2 Stacks .......................................................................................................................... 43
2.3.3 Register Map ................................................................................................................ 44
2.3.4 Register Descriptions .................................................................................................... 45
2.3.5 Exceptions and Interrupts .............................................................................................. 58
2.3.6 Data Types ................................................................................................................... 58
2.4 Memory Model .............................................................................................................. 58
2.4.1 Memory Regions, Types and Attributes ........................................................................... 59
2.4.2 Memory System Ordering of Memory Accesses .............................................................. 60
2.4.3 Behavior of Memory Accesses ....................................................................................... 60
2.4.4 Software Ordering of Memory Accesses ......................................................................... 61
2.4.5 Bit-Banding ................................................................................................................... 62
2.4.6 Data Storage ................................................................................................................ 64
2.4.7 Synchronization Primitives ............................................................................................. 65
2.5 Exception Model ........................................................................................................... 66
2.5.1 Exception States ........................................................................................................... 66
2.5.2 Exception Types ............................................................................................................ 67
2.5.3 Exception Handlers ....................................................................................................... 70
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2.5.4 Vector Table .................................................................................................................. 70
2.5.5 Exception Priorities ....................................................................................................... 71
2.5.6 Interrupt Priority Grouping .............................................................................................. 71
2.5.7 Exception Entry and Return ........................................................................................... 71
2.6 Fault Handling .............................................................................................................. 74
2.6.1 Fault Types ................................................................................................................... 74
2.6.2 Fault Escalation and Hard Faults .................................................................................... 75
2.6.3 Fault Status Registers and Fault Address Registers ........................................................ 75
2.6.4 Lockup ......................................................................................................................... 76
2.7 Power Management ...................................................................................................... 76
2.7.1 Entering Sleep Modes ................................................................................................... 76
2.7.2 Wake Up from Sleep Mode ............................................................................................ 77
2.8 Instruction Set Summary ............................................................................................... 77
3 Cortex-M3 Peripherals ........................................................................................... 81
3.1 Functional Description ................................................................................................... 81
3.1.1 System Timer (SysTick) ................................................................................................. 81
3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 82
3.1.3 System Control Block (SCB) .......................................................................................... 84
3.1.4 Memory Protection Unit (MPU) ....................................................................................... 84
3.2 Register Map ................................................................................................................ 89
3.3 System Timer (SysTick) Register Descriptions ................................................................ 91
3.4 NVIC Register Descriptions ........................................................................................... 95
3.5 System Control Block (SCB) Register Descriptions ........................................................ 108
3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 137
4 JTAG Interface ...................................................................................................... 147
4.1 Block Diagram ............................................................................................................ 148
4.2 Functional Description ................................................................................................. 148
4.2.1 JTAG Interface Pins ..................................................................................................... 148
4.2.2 JTAG TAP Controller ................................................................................................... 150
4.2.3 Shift Registers ............................................................................................................ 151
4.2.4 Operational Considerations .......................................................................................... 151
4.3 Initialization and Configuration ..................................................................................... 154
4.4 Register Descriptions .................................................................................................. 154
4.4.1 Instruction Register (IR) ............................................................................................... 154
4.4.2 Data Registers ............................................................................................................ 156
5 System Control ..................................................................................................... 159
5.1 Functional Description ................................................................................................. 159
5.1.1 Device Identification .................................................................................................... 159
5.1.2 Reset Control .............................................................................................................. 159
5.1.3 Power Control ............................................................................................................. 162
5.1.4 Clock Control .............................................................................................................. 163
5.1.5 System Control ........................................................................................................... 169
5.2 Initialization and Configuration ..................................................................................... 170
5.3 Register Map .............................................................................................................. 170
5.4 Register Descriptions .................................................................................................. 172
6 Hibernation Module .............................................................................................. 217
6.1 Block Diagram ............................................................................................................ 218
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6.2 Functional Description ................................................................................................. 218
6.2.1 Register Access Timing ............................................................................................... 218
6.2.2 Clock Source .............................................................................................................. 219
6.2.3 Battery Management ................................................................................................... 220
6.2.4 Real-Time Clock .......................................................................................................... 221
6.2.5 Non-Volatile Memory ................................................................................................... 221
6.2.6 Power Control ............................................................................................................. 221
6.2.7 Initiating Hibernate ...................................................................................................... 222
6.2.8 Interrupts and Status ................................................................................................... 222
6.3 Initialization and Configuration ..................................................................................... 222
6.3.1 Initialization ................................................................................................................. 223
6.3.2 RTC Match Functionality (No Hibernation) .................................................................... 223
6.3.3 RTC Match/Wake-Up from Hibernation ......................................................................... 223
6.3.4 External Wake-Up from Hibernation .............................................................................. 223
6.3.5 RTC/External Wake-Up from Hibernation ...................................................................... 224
6.4 Register Map .............................................................................................................. 224
6.5 Register Descriptions .................................................................................................. 224
7 Internal Memory ................................................................................................... 237
7.1 Block Diagram ............................................................................................................ 237
7.2 Functional Description ................................................................................................. 237
7.2.1 SRAM Memory ............................................................................................................ 237
7.2.2 Flash Memory ............................................................................................................. 238
7.3 Flash Memory Initialization and Configuration ............................................................... 239
7.3.1 Flash Programming ..................................................................................................... 239
7.3.2 Nonvolatile Register Programming ............................................................................... 240
7.4 Register Map .............................................................................................................. 241
7.5 Flash Register Descriptions (Flash Control Offset) ......................................................... 242
7.6 Flash Register Descriptions (System Control Offset) ...................................................... 250
8 General-Purpose Input/Outputs (GPIOs) ........................................................... 263
8.1 Functional Description ................................................................................................. 263
8.1.1 Data Control ............................................................................................................... 264
8.1.2 Interrupt Control .......................................................................................................... 265
8.1.3 Mode Control .............................................................................................................. 266
8.1.4 Commit Control ........................................................................................................... 266
8.1.5 Pad Control ................................................................................................................. 266
8.1.6 Identification ............................................................................................................... 266
8.2 Initialization and Configuration ..................................................................................... 266
8.3 Register Map .............................................................................................................. 267
8.4 Register Descriptions .................................................................................................. 269
9 General-Purpose Timers ...................................................................................... 304
9.1 Block Diagram ............................................................................................................ 304
9.2 Functional Description ................................................................................................. 305
9.2.1 GPTM Reset Conditions .............................................................................................. 306
9.2.2 32-Bit Timer Operating Modes ...................................................................................... 306
9.2.3 16-Bit Timer Operating Modes ...................................................................................... 307
9.3 Initialization and Configuration ..................................................................................... 311
9.3.1 32-Bit One-Shot/Periodic Timer Mode ........................................................................... 311
9.3.2 32-Bit Real-Time Clock (RTC) Mode ............................................................................. 312
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9.3.3 16-Bit One-Shot/Periodic Timer Mode ........................................................................... 312
9.3.4 16-Bit Input Edge Count Mode ..................................................................................... 313
9.3.5 16-Bit Input Edge Timing Mode .................................................................................... 313
9.3.6 16-Bit PWM Mode ....................................................................................................... 314
9.4 Register Map .............................................................................................................. 314
9.5 Register Descriptions .................................................................................................. 315
10 Watchdog Timer ................................................................................................... 340
10.1 Block Diagram ............................................................................................................ 341
10.2 Functional Description ................................................................................................. 341
10.3 Initialization and Configuration ..................................................................................... 342
10.4 Register Map .............................................................................................................. 342
10.5 Register Descriptions .................................................................................................. 343
11 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 364
11.1 Block Diagram ............................................................................................................ 365
11.2 Functional Description ................................................................................................. 365
11.2.1 Transmit/Receive Logic ............................................................................................... 365
11.2.2 Baud-Rate Generation ................................................................................................. 366
11.2.3 Data Transmission ...................................................................................................... 367
11.2.4 Serial IR (SIR) ............................................................................................................. 367
11.2.5 FIFO Operation ........................................................................................................... 368
11.2.6 Interrupts .................................................................................................................... 368
11.2.7 Loopback Operation .................................................................................................... 369
11.2.8 IrDA SIR block ............................................................................................................ 369
11.3 Initialization and Configuration ..................................................................................... 369
11.4 Register Map .............................................................................................................. 370
11.5 Register Descriptions .................................................................................................. 371
12 Synchronous Serial Interface (SSI) .................................................................... 405
12.1 Block Diagram ............................................................................................................ 405
12.2 Functional Description ................................................................................................. 405
12.2.1 Bit Rate Generation ..................................................................................................... 406
12.2.2 FIFO Operation ........................................................................................................... 406
12.2.3 Interrupts .................................................................................................................... 406
12.2.4 Frame Formats ........................................................................................................... 407
12.3 Initialization and Configuration ..................................................................................... 414
12.4 Register Map .............................................................................................................. 415
12.5 Register Descriptions .................................................................................................. 416
13 Analog Comparators ............................................................................................ 442
13.1 Block Diagram ............................................................................................................ 442
13.2 Functional Description ................................................................................................. 443
13.2.1 Internal Reference Programming .................................................................................. 443
13.3 Initialization and Configuration ..................................................................................... 444
13.4 Register Map .............................................................................................................. 445
13.5 Register Descriptions .................................................................................................. 445
14 Pin Diagram .......................................................................................................... 453
15 Signal Tables ........................................................................................................ 455
15.1 100-Pin LQFP Package Pin Tables ............................................................................... 455
15.2 108-Pin BGA Package Pin Tables ................................................................................ 466
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15.3 Connections for Unused Signals ................................................................................... 477
16 Operating Characteristics ................................................................................... 479
17 Electrical Characteristics .................................................................................... 480
17.1 DC Characteristics ...................................................................................................... 480
17.1.1 Maximum Ratings ....................................................................................................... 480
17.1.2 Recommended DC Operating Conditions ...................................................................... 480
17.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ................................................ 481
17.1.4 GPIO Module Characteristics ....................................................................................... 481
17.1.5 Power Specifications ................................................................................................... 481
17.1.6 Flash Memory Characteristics ...................................................................................... 483
17.1.7 Hibernation ................................................................................................................. 483
17.2 AC Characteristics ....................................................................................................... 483
17.2.1 Load Conditions .......................................................................................................... 483
17.2.2 Clocks ........................................................................................................................ 484
17.2.3 JTAG and Boundary Scan ............................................................................................ 485
17.2.4 Reset ......................................................................................................................... 487
17.2.5 Sleep Modes ............................................................................................................... 489
17.2.6 Hibernation Module ..................................................................................................... 489
17.2.7 General-Purpose I/O (GPIO) ........................................................................................ 489
17.2.8 Synchronous Serial Interface (SSI) ............................................................................... 490
17.2.9 Analog Comparator ..................................................................................................... 491
A Serial Flash Loader .............................................................................................. 493
A.1 Serial Flash Loader ..................................................................................................... 493
A.2 Interfaces ................................................................................................................... 493
A.2.1 UART ......................................................................................................................... 493
A.2.2 SSI ............................................................................................................................. 493
A.3 Packet Handling .......................................................................................................... 494
A.3.1 Packet Format ............................................................................................................ 494
A.3.2 Sending Packets ......................................................................................................... 494
A.3.3 Receiving Packets ....................................................................................................... 494
A.4 Commands ................................................................................................................. 495
A.4.1 COMMAND_PING (0X20) ............................................................................................ 495
A.4.2 COMMAND_GET_STATUS (0x23) ............................................................................... 495
A.4.3 COMMAND_DOWNLOAD (0x21) ................................................................................. 495
A.4.4 COMMAND_SEND_DATA (0x24) ................................................................................. 496
A.4.5 COMMAND_RUN (0x22) ............................................................................................. 496
A.4.6 COMMAND_RESET (0x25) ......................................................................................... 496
B Register Quick Reference ................................................................................... 498
C Ordering and Contact Information ..................................................................... 514
C.1 Ordering Information .................................................................................................... 514
C.2 Part Markings .............................................................................................................. 514
C.3 Kits ............................................................................................................................. 515
C.4 Support Information ..................................................................................................... 515
D Package Information ............................................................................................ 516
D.1 108-Ball BGA Package ................................................................................................ 516
D.1.1 Package Dimensions ................................................................................................... 516
D.1.2 Tray Dimensions ......................................................................................................... 518
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D.1.3 Tape and Reel Dimensions .......................................................................................... 519
D.2 100-Pin LQFP Package ............................................................................................... 520
D.2.1 Package Dimensions ................................................................................................... 520
D.2.2 Tray Dimensions ......................................................................................................... 522
D.2.3 Tape and Reel Dimensions .......................................................................................... 523
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List of Figures
Figure 1-1. Stellaris®LM3S1110 Microcontroller High-Level Block Diagram ............................. 33
Figure 2-1. CPU Block Diagram ............................................................................................. 41
Figure 2-2. TPIU Block Diagram ............................................................................................ 42
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 44
Figure 2-4. Bit-Band Mapping ................................................................................................ 64
Figure 2-5. Data Storage ....................................................................................................... 65
Figure 2-6. Vector table ......................................................................................................... 70
Figure 2-7. Exception Stack Frame ........................................................................................ 72
Figure 3-1. SRD Use Example ............................................................................................... 87
Figure 4-1. JTAG Module Block Diagram .............................................................................. 148
Figure 4-2. Test Access Port State Machine ......................................................................... 151
Figure 4-3. IDCODE Register Format ................................................................................... 157
Figure 4-4. BYPASS Register Format ................................................................................... 157
Figure 4-5. Boundary Scan Register Format ......................................................................... 158
Figure 5-1. Basic RST Configuration .................................................................................... 160
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 161
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 161
Figure 5-4. Power Architecture ............................................................................................ 163
Figure 5-5. Main Clock Tree ................................................................................................ 166
Figure 6-1. Hibernation Module Block Diagram ..................................................................... 218
Figure 6-2. Clock Source Using Crystal ................................................................................ 220
Figure 6-3. Clock Source Using Dedicated Oscillator ............................................................. 220
Figure 7-1. Flash Block Diagram .......................................................................................... 237
Figure 8-1. GPIO Port Block Diagram ................................................................................... 264
Figure 8-2. GPIODATA Write Example ................................................................................. 265
Figure 8-3. GPIODATA Read Example ................................................................................. 265
Figure 9-1. GPTM Module Block Diagram ............................................................................ 305
Figure 9-2. 16-Bit Input Edge Count Mode Example .............................................................. 309
Figure 9-3. 16-Bit Input Edge Time Mode Example ............................................................... 310
Figure 9-4. 16-Bit PWM Mode Example ................................................................................ 311
Figure 10-1. WDT Module Block Diagram .............................................................................. 341
Figure 11-1. UART Module Block Diagram ............................................................................. 365
Figure 11-2. UART Character Frame ..................................................................................... 366
Figure 11-3. IrDA Data Modulation ......................................................................................... 368
Figure 12-1. SSI Module Block Diagram ................................................................................. 405
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 408
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 408
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 409
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 409
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 410
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 411
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 411
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 412
Figure 12-10. MICROWIRE Frame Format (Single Frame) ........................................................ 413
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 414
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 414
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Figure 13-1. Analog Comparator Module Block Diagram ......................................................... 442
Figure 13-2. Structure of Comparator Unit .............................................................................. 443
Figure 13-3. Comparator Internal Reference Structure ............................................................ 444
Figure 14-1. 100-Pin LQFP Package Pin Diagram .................................................................. 453
Figure 14-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 454
Figure 17-1. Load Conditions ................................................................................................ 484
Figure 17-2. JTAG Test Clock Input Timing ............................................................................. 486
Figure 17-3. JTAG Test Access Port (TAP) Timing .................................................................. 486
Figure 17-4. JTAG TRST Timing ............................................................................................ 487
Figure 17-5. External Reset Timing (RST) .............................................................................. 487
Figure 17-6. Power-On Reset Timing ..................................................................................... 488
Figure 17-7. Brown-Out Reset Timing .................................................................................... 488
Figure 17-8. Software Reset Timing ....................................................................................... 488
Figure 17-9. Watchdog Reset Timing ..................................................................................... 488
Figure 17-10. Hibernation Module Timing ................................................................................. 489
Figure 17-11. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Figure 17-12. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 491
Figure 17-13. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 491
Figure D-1. 108-Ball BGA Package Dimensions .................................................................... 516
Figure D-2. 108-Ball BGA Tray Dimensions ........................................................................... 518
Figure D-3. 108-Ball BGA Tape and Reel Dimensions ............................................................ 519
Figure D-4. 100-Pin LQFP Package Dimensions ................................................................... 520
Figure D-5. 100-Pin LQFP Tray Dimensions .......................................................................... 522
Figure D-6. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 523
Measurement .................................................................................................... 490
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List of Tables
Table 1. Revision History .................................................................................................. 19
Table 2. Documentation Conventions ................................................................................ 24
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 44
Table 2-2. Processor Register Map ....................................................................................... 45
Table 2-3. PSR Register Combinations ................................................................................. 50
Table 2-4. Memory Map ....................................................................................................... 58
Table 2-5. Memory Access Behavior ..................................................................................... 60
Table 2-6. SRAM Memory Bit-Banding Regions .................................................................... 62
Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................... 62
Table 2-8. Exception Types .................................................................................................. 68
Table 2-9. Interrupts ............................................................................................................ 69
Table 2-10. Exception Return Behavior ................................................................................... 73
Table 2-11. Faults ................................................................................................................. 74
Table 2-12. Fault Status and Fault Address Registers .............................................................. 75
Table 2-13. Cortex-M3 Instruction Summary ........................................................................... 77
Table 3-1. Core Peripheral Register Regions ......................................................................... 81
Table 3-2. Memory Attributes Summary ................................................................................ 84
Table 3-3. TEX, S, C, and B Bit Field Encoding ..................................................................... 87
Table 3-4. Cache Policy for Memory Attribute Encoding ......................................................... 88
Table 3-5. AP Bit Field Encoding .......................................................................................... 88
Table 3-6. Memory Region Attributes for Stellaris®Microcontrollers ........................................ 88
Table 3-7. Peripherals Register Map ..................................................................................... 89
Table 3-8. Interrupt Priority Levels ...................................................................................... 115
Table 3-9. Example SIZE Field Values ................................................................................ 144
Table 4-1. JTAG Port Pins Reset State ............................................................................... 149
Table 4-2. JTAG Instruction Register Commands ................................................................. 154
Table 5-1. Clock Source Options ........................................................................................ 164
Table 5-2. Possible System Clock Frequencies Using the SYSDIV Field ............................... 167
Table 5-3. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 167
Table 5-4. System Control Register Map ............................................................................. 171
Table 5-5. RCC2 Fields that Override RCC fields ................................................................. 185
Table 6-1. Hibernation Module Register Map ....................................................................... 224
Table 7-1. Flash Protection Policy Combinations ................................................................. 238
Table 7-2. User-Programmable Flash Memory Resident Registers ....................................... 240
Table 7-3. Flash Register Map ............................................................................................ 241
Table 8-1. GPIO Pad Configuration Examples ..................................................................... 267
Table 8-2. GPIO Interrupt Configuration Example ................................................................ 267
Table 8-3. GPIO Register Map ........................................................................................... 268
Table 9-1. Available CCP Pins ............................................................................................ 305
Table 9-2. 16-Bit Timer With Prescaler Configurations ......................................................... 308
Table 9-3. Timers Register Map .......................................................................................... 314
Table 10-1. Watchdog Timer Register Map ............................................................................ 342
Table 11-1. UART Register Map ........................................................................................... 370
Table 12-1. SSI Register Map .............................................................................................. 415
Table 13-1. Internal Reference Voltage and ACREFCTL Field Values ..................................... 444
Table 13-2. Analog Comparators Register Map ..................................................................... 445
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Table 15-1. Signals by Pin Number ....................................................................................... 455
Table 15-2. Signals by Signal Name ..................................................................................... 459
Table 15-3. Signals by Function, Except for GPIO ................................................................. 462
Table 15-4. GPIO Pins and Alternate Functions ..................................................................... 465
Table 15-5. Signals by Pin Number ....................................................................................... 466
Table 15-6. Signals by Signal Name ..................................................................................... 470
Table 15-7. Signals by Function, Except for GPIO ................................................................. 473
Table 15-8. GPIO Pins and Alternate Functions ..................................................................... 476
Table 15-9. Connections for Unused Signals (100-pin LQFP) ................................................. 477
Table 15-10. Connections for Unused Signals, 108-pin BGA .................................................... 478
Table 16-1. Temperature Characteristics ............................................................................... 479
Table 16-2. Thermal Characteristics ..................................................................................... 479
Table 16-3. ESD Absolute Maximum Ratings ........................................................................ 479
Table 17-1. Maximum Ratings .............................................................................................. 480
Table 17-2. Recommended DC Operating Conditions ............................................................ 480
Table 17-3. LDO Regulator Characteristics ........................................................................... 481
Table 17-4. GPIO Module DC Characteristics ........................................................................ 481
Table 17-5. Detailed Power Specifications ............................................................................ 482
Table 17-6. Flash Memory Characteristics ............................................................................ 483
Table 17-7. Hibernation Module DC Characteristics ............................................................... 483
Table 17-8. Phase Locked Loop (PLL) Characteristics ........................................................... 484
Table 17-9. Actual PLL Frequency ........................................................................................ 484
Table 17-10. Clock Characteristics ......................................................................................... 484
Table 17-11. Crystal Characteristics ....................................................................................... 485
Table 17-12. JTAG Characteristics ......................................................................................... 485
Table 17-13. Reset Characteristics ......................................................................................... 487
Table 17-14. Sleep Modes AC Characteristics ......................................................................... 489
Table 17-15. Hibernation Module AC Characteristics ............................................................... 489
Table 17-16. GPIO Characteristics ......................................................................................... 490
Table 17-17. SSI Characteristics ............................................................................................ 490
Table 17-18. Analog Comparator Characteristics ..................................................................... 491
Table 17-19. Analog Comparator Voltage Reference Characteristics ........................................ 492
Table C-1. Part Ordering Information ................................................................................... 514
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List of Registers
The Cortex-M3 Processor ............................................................................................................. 39
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 46
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 46
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 46
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 46
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 46
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 46
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 46
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 46
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 46
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 46
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 46
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 46
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 46
Register 14: Stack Pointer (SP) ........................................................................................................... 47
Register 15: Link Register (LR) ............................................................................................................ 48
Register 16: Program Counter (PC) ..................................................................................................... 49
Register 17: Program Status Register (PSR) ........................................................................................ 50
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 54
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 55
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 56
Register 21: Control Register (CONTROL) ........................................................................................... 57
Cortex-M3 Peripherals ................................................................................................................... 81
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ............................................. 92
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 ................................................ 94
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ............................................. 95
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................... 96
Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104 .................................................................. 97
Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 ................................................................ 98
Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184 .............................................................. 99
Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 100
Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204 ......................................................... 101
Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 102
Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 .................................................. 103
Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 104
Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 ........................................................... 105
Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 106
Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 106
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 106
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 106
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 106
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 106
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 106
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 106
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 106
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Register 23: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 106
Register 24: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 106
Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 108
Register 26: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 109
Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 110
Register 28: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 114
Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 115
Register 30: System Control (SYSCTRL), offset 0xD10 ....................................................................... 117
Register 31: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 119
Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 121
Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 122
Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 123
Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 124
Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 128
Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 134
Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 136
Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 137
Register 40: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 138
Register 41: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 139
Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 141
Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 142
Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 142
Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 142
Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 142
Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 144
Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 144
Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 144
Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 144
System Control ............................................................................................................................ 159
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 173
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 175
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 176
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 177
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 178
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 179
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 180
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 181
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 184
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 185
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 187
Register 12: Device Identification 1 (DID1), offset 0x004 ..................................................................... 188
Register 13: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 190
Register 14: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 191
Register 15: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 193
Register 16: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 195
Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 197
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 198
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 199
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Stellaris® LM3S1110 Microcontroller
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 200
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 201
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 203
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 205
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 207
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 209
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 211
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 213
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 214
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 216
Hibernation Module ..................................................................................................................... 217
Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 225
Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 226
Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 227
Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 228
Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 229
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 231
Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 232
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 233
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 234
Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 235
Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 236
Internal Memory ........................................................................................................................... 237
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 243
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 244
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 245
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 247
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 248
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 249
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 251
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 252
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 253
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 254
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 255
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 256
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 257
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 258
Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 259
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 260
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 261
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 262
General-Purpose Input/Outputs (GPIOs) ................................................................................... 263
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 270
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 271
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 272
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 273
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 274
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 275
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Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 276
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 277
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 278
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 279
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 281
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 282
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 283
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 284
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 285
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 286
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 287
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 288
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 289
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 290
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 292
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 293
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 294
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 295
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 296
Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 297
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 298
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 299
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 300
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 301
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 302
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 303
General-Purpose Timers ............................................................................................................. 304
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 316
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 317
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 319
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 321
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 324
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 326
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 327
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 328
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 330
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 331
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 332
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 333
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 334
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 335
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 336
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 337
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 338
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 339
Watchdog Timer ........................................................................................................................... 340
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 344
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 345
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Stellaris® LM3S1110 Microcontroller
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 346
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 347
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 348
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 349
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 350
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 351
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 352
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 353
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 354
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 355
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 356
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 357
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 358
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 359
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 360
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 361
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 362
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 363
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 364
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 372
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 374
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 376
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 378
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 379
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 380
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 381
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 383
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 385
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 387
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 389
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 390
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 391
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 393
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 394
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 395
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 396
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 397
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 398
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 399
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 400
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 401
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 402
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 403
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 404
Synchronous Serial Interface (SSI) ............................................................................................ 405
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 417
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 419
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 421
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Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 422
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 424
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 425
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 427
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 428
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 429
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 430
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 431
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 432
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 433
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 434
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 435
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 436
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 437
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 438
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 439
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 440
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 441
Analog Comparators ................................................................................................................... 442
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 446
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 447
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 448
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 449
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 450
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 450
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 451
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 451
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Revision History
The revision history table notes changes made between the indicated revisions of the LM3S1110
data sheet.
Table 1. Revision History
DescriptionRevisionDate
7787September 2010
■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
■ Changed register names to be consistent with StellarisWare®names: the Cortex-M3 Interrupt
■ Added clarification of instruction execution during Flash operations.
■ Modified Figure 8-1 on page 264 to clarify operation of the GPIO inputs when used as an alternate
■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits
Stellaris® LM3S1110 Microcontroller
new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
added, including all the Cortex-M3 registers.
Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and
the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0)
register.
function.
wide, bits[7:0].
■ Added caution not to apply a Low value to PB7 when debugging; a Low value on the pin causes
the JTAG controller to be reset, resulting in a loss of JTAG communication.
■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
■ In Electrical Characteristics chapter:
– Added I
– Corrected values for t
■ Added dimensions for Tray and Tape and Reel shipping mediums.
7393June 2010
7007April 2010
■ Corrected base address for SRAM in architectural overview chapter.
■ Clarified system clock operation, adding content to “Clock Control” on page 163.
■ In Signal Tables chapter, added table "Connections for Unused Signals."
■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
■ In "Reset Characteristics" table, corrected value for supply voltage (VDD) rise time.
■ Additional minor data sheet clarifications and corrections.
■ Added caution note to the I2C Master Timer Period (I2CMTPR) register description and changed
field width to 7 bits.
■ Removed erroneous text about restoring the Flash Protection registers.
■ Added note about RST signal routing.
■ Clarified the function of the TnSTALL bit in the GPTMCTL register.
parameter (GPIO input leakage current) to Table 17-4 on page 481.
LKG
parameter (SSIClk rise/fall time) in Table 17-17 on page 490.
CLKRF
■ Additional minor data sheet clarifications and corrections.
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19September 04, 2010
Revision History
Table 1. Revision History (continued)
DescriptionRevisionDate
6712January 2010
■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.
■ Clarified wording on Flash memory access errors.
■ Added section on Flash interrupts.
■ Clarified operation of SSI transmit FIFO.
■ Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■ Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
6462October 2009
■ Removed erroneous reference to the WRC bit in the Hibernation chapter.
■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
■ Made these changes to the Electrical Characteristics chapter:
– Removed V
SIH
and V
parameters from Operating Conditions table.
SIL
– Added table showing actual PLL frequency depending on input crystal.
– Changed the name of the t
HIB_REG_WRITE
parameter to t
HIB_REG_ACCESS
.
– Changed SSI set up and hold times to be expressed in system clocks, not ns.
Corrected ordering numbers.5920July 2009
5902July 2009
■ Clarified Power-on reset and RST pin operation; added new diagrams.
■ Corrected the reset value of the Hibernation Data (HIBDATA) and Hibernation Control (HIBCTL)
registers.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.
■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added E
IR
(Internal voltage reference error) parameter.
■ Additional minor data sheet clarifications and corrections.
5367April 2009
■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 153).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Added "GPIO Module DC Characteristics" table (see Table 17-4 on page 481).
■ Additional minor data sheet clarifications and corrections.
September 04, 201020
Texas Instruments-Production Data
Table 1. Revision History (continued)
DescriptionRevisionDate
4660January 2009
■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
■ Additional minor data sheet clarifications and corrections.
Stellaris® LM3S1110 Microcontroller
4283November 2008
■ Revised High-Level Block Diagram.
■ Additional minor data sheet clarifications and corrections were made.
4149October 2008
■ Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.
■ The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
■ Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
3447August 2008
■ Added note on clearing interrupts to Interrupts chapter.
■ Added Power Architecture diagram to System Control chapter.
■ Additional minor data sheet clarifications and corrections.
■ Additional minor data sheet clarifications and corrections.3108July 2008
2972May 2008
■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
the LDO output as the source of VDD25 input.
■ Additional minor data sheet clarifications and corrections.
2881April 2008 ■ The ΘJAvalue was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating
Characteristics chapter.
■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of
1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.
■ Values for I
DD_HIBERNATE
were added to the "Detailed Power Specifications" table in the "Electrical
Characteristics" chapter.
■ The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter.
■ The T
parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapter
VDDRISE
was changed from a max of 100 to 250.
■ The maximum value on Core supply voltage (V
) in the "Maximum Ratings" table in the "Electrical
DD25
Characteristics" chapter was changed from 4 to 3.
■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior data
sheets incorrectly noted it as 30 kHz ± 30%).
■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is
the input source for the oscillator. Prior data sheets incorrectly noted 0x3 as a reserved value.
■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior data sheets incorrectly
noted the reset was 0x0 (MOSC).
■ Two figures on clock source were added to the "Hibernation Module":
– Clock Source Using Crystal
21September 04, 2010
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Revision History
Table 1. Revision History (continued)
DescriptionRevisionDate
– Clock Source Using Dedicated Oscillator
■ The following notes on battery management were added to the "Hibernation Module" chapter:
– Battery voltage is not measured while in Hibernate mode.
– System level factors may affect the accuracy of the low battery detect circuit. The designer
should consider battery type, discharge characteristics, and a test load during battery voltage
measurements.
■ A note on high-current applications was added to the GPIO chapter:
For special high-current applications, the GPIO output buffers may be used with the following
restrictions. With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may
be used to sink current loads up to 18 mA each. At 18-mA sink current loading, the VOL value is
specified as 1.2 V. The high-current GPIO package pins must be selected such that there are only
a maximum of two per side of the physical package or BGA pin group with the total number of
high-current GPIO outputs not exceeding four for the entire package.
■ A note on Schmitt inputs was added to the GPIO chapter:
Pins configured as digital inputs are Schmitt-triggered.
■ The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.
■ The "Differential Sampling Range" figures in the ADC chapter were clarified.
■ The last revision of the data sheet (revision 2550) introduced two errors that have now been corrected:
– The LQFP pin diagrams and pin tables were missing the comparator positive and negative input
pins.
– The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.
■ Additional minor data sheet clarifications and corrections.
Started tracking revision history.2550March 2008
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September 04, 201022
About This Document
This data sheet provides reference information for the LM3S1110 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following related documents are available on the Stellaris®web site at www.ti.com/stellaris:
■
Stellaris® Errata
Stellaris® LM3S1110 Microcontroller
■
ARM® Cortex™-M3 Errata
■
Cortex™-M3 Instruction Set Technical User's Manual
■
Stellaris® Graphics Library User's Guide
■
Stellaris® Peripheral Driver Library User's Guide
The following related documents are also referenced:
■
ARM® Debug Interface V5 Architecture Specification
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the web site for additional
documentation, including application notes and white papers.
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About This Document
Documentation Conventions
This document uses the conventions shown in Table 2 on page 24.
Table 2. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
reserved
yy:xx
Register Bit/Field
Types
R/W1C
R/W1S
W1C
Reset Value
Pin/Signal Notation
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in Table 2-4 on page 58.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. Writing to it with any value clears the register.R/WC
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bit
value in the register.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
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Table 2. Documentation Conventions (continued)
MeaningNotation
Refers to the electrical signal encoding of a pin.signal
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Stellaris® LM3S1110 Microcontroller
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Architectural Overview
1 Architectural Overview
The Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings
high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These
pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit
devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S1000 series extends the Stellaris®family with larger on-chip
memories, enhanced power management, and expanded I/O and control capabilities.
The LM3S1110 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
For applications requiring extreme conservation of power, the LM3S1110 microcontroller features
a battery-backed Hibernation module to efficiently power down the LM3S1110 to a low-power state
during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time
counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated
non-volatile memory, the Hibernation module positions the LM3S1110 microcontroller perfectly for
battery applications.
In addition, the LM3S1110 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S1110 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Texas Instruments offers a complete solution to get to market quickly, with evaluation and
development boards, white papers and application notes, an easy-to-use peripheral driver library,
and a strong support, sales, and distributor network. See “Ordering and Contact
Information” on page 514 for ordering information for Stellaris®family devices.
1.1 Product Features
The LM3S1110 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 25-MHz operation
– Hardware-division and single-cycle-multiplication
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Stellaris® LM3S1110 Microcontroller
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 23 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ ARM® Cortex™-M3 Processor Core
– Compact core.
– Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the
memory size usually associated with 8- and 16-bit devices; typically in the range of a few
kilobytes of memory for microcontroller class applications.
– Rapid application execution through Harvard architecture characterized by separate buses
for instruction and data.
– Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
– Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
– Memory protection unit (MPU) to provide a privileged mode of operation for complex
applications.
– Migration from the ARM7™ processor family for better performance and power efficiency.
– Full-featured debug solution
• Serial Wire JTAG Debug Port (SWJ-DP)
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
• Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
– Optimized for single-cycle flash usage
– Three sleep modes with clock gating for low power
– Single-cycle multiply instruction and hardware divide
– Atomic operations
– ARM Thumb2 mixed 16-/32-bit instruction set
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Architectural Overview
– 1.25 DMIPS/MHz
■ JTAG
– IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
– Four-bit Instruction Register (IR) chain for storing JTAG instructions
– IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
– ARM additional instructions: APACC, DPACC and ABORT
– Integrated ARM Serial Wire Debug (SWD)
■ Hibernation
– System power control using discrete external regulator
– Dedicated pin for waking from an external signal
– Low-battery detection, signaling, and interrupt generation
– 32-bit real-time clock (RTC)
– Two 32-bit RTC match registers for timed wake-up and interrupt generation
– Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal
– RTC predivider trim for making fine adjustments to the clock rate
– 64 32-bit words of non-volatile memory
– Programmable interrupts for RTC match, external wake, and low battery events
■ Internal Memory
– 64 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 16 KB single-cycle SRAM
■ GPIOs
– 20-41 GPIOs, depending on configuration
– 5-V-tolerant in input configuration
– Programmable control for GPIO interrupts
• Interrupt generation masking
• Edge-triggered on rising, falling, or both
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Stellaris® LM3S1110 Microcontroller
• Level-sensitive on High or Low values
– Bit masking in both read and write operations through address lines
– Pins configured as digital inputs are Schmitt-triggered.
– Programmable control for GPIO pad configuration
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
configured with an 18-mA pad drive for high-current applications
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timers/counters. Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling when the controller asserts CPU Halt flag during debug
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes
only)
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
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Architectural Overview
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ UART
– Two fully programmable 16C550-type UARTs with IrDA support
– Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
– Programmable baud-rate generator allowing speeds up to 1.5625 Mbps
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start bit detection
– Line-break generation and detection
– Fully programmable serial interface characteristics
• 5, 6, 7, or 8 data bits
• Even, odd, stick, or no-parity bit generation/detection
• 1 or 2 stop bit generation
– IrDA serial-IR (SIR) encoder/decoder providing
• Programmable use of IrDA Serial Infrared (SIR) or UART input/output
• Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
• Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
• Programmable internal clock generator enabling division of reference clock by 1 to 256
for low-power mode bit duration
■ Synchronous Serial Interface (SSI)
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Stellaris® LM3S1110 Microcontroller
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ Analog Comparators
– Two independent integrated analog comparators
– Configurable for output to drive an output pin or generate an interrupt
– Compare external pin input to external pin input or to internal programmable voltage reference
– Compare a test voltage against any one of these voltages
• An individual external reference voltage
• A shared single external reference voltage
• A shared internal reference voltage
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core
digital logic and analog circuits
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
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Architectural Overview
■ Industrial and extended temperature 100-pin RoHS-compliant LQFP package
■ Industrial-range 108-ball RoHS-compliant BGA package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 33 depicts the features on the Stellaris®LM3S1110 microcontroller.
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LM3S1110
ARM®
Cortex™-M3
(25 MHz)
NVIC MPU
Flash
(64 KB)
DCode bus
ICode bus
JTAG/SWD
System
Control and
Clocks
Bus Matrix
System Bus
SRAM
(16 KB)
SYSTEM PERIPHERALS
Watchdog
Timer
(1)
Hibernation
Module
General-
Purpose
Timers (3)
GPIOs
(20-41)
SERIAL PERIPHERALS
UARTs
(2)
SSI
(1)
ANALOG PERIPHERALS
Analog
Comparators
(2)
Advanced Peripheral Bus (APB)
Stellaris® LM3S1110 Microcontroller
Figure 1-1. Stellaris®LM3S1110 Microcontroller High-Level Block Diagram
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Architectural Overview
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S1110 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 514.
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 39)
All members of the Stellaris®product family, including the LM3S1110 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
1.4.1.2 Memory Map (see page 58)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S1110 controller can be found in Table 2-4 on page 58. Register addresses are given as a
hexadecimal increment, relative to the module's base address as shown in the memory map.
1.4.1.3 System Timer (SysTick) (see page 81)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.4 Nested Vectored Interrupt Controller (NVIC) (see page 82)
The LM3S1110 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM® Cortex™-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 23 interrupts.
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1.4.1.5 System Control Block (SCB) (see page 84)
The SCB provides system implementation information and system control, including configuration,
control, and reporting of system exceptions.
1.4.1.6 Memory Protection Unit (MPU) (see page 84)
The MPU supports the standard ARMv7 Protected Memory System Architecture (PMSA) model.
The MPU provides full support for protection regions, overlapping protection regions, access
permissions, and exporting memory attributes to the system.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S1110 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S1110, PWM motion control functionality can be achieved through:
Stellaris® LM3S1110 Microcontroller
■ The motion control features of the general-purpose timers using the CCP pins
CCP Pins (see page 310)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Analog Peripherals
For support of analog signals, the LM3S1110 microcontroller offers two analog comparators.
1.4.3.1 Analog Comparators (see page 442)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
The LM3S1110 microcontroller provides two independent integrated analog comparators that can
be configured to drive an output or generate an interrupt .
A comparator can compare a test voltage against any one of these voltages:
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts to cause it to start
capturing a sample sequence.
1.4.4 Serial Communications Peripherals
The LM3S1110 controller supports both asynchronous and synchronous serial communications
with:
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Architectural Overview
■ Two fully programmable 16C550-type UARTs
■ One SSI module
1.4.4.1 UART (see page 364)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S1110 controller includes two fully programmable 16C550-type UARTs that support data
transfer speeds up to 1.5625 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and receive (RX) FIFOs reduce CPU interrupt service loading. The
UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 405)
Synchronous Serial Interface (SSI) is a four-wire bi-directional full and low-speed communications
interface.
The LM3S1110 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 263)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris®GPIO module is comprised of eight physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 20-41 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal
Tables” on page 455 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines. Pins configured as digital inputs are
Schmitt-triggered.
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1.4.5.2 Three Programmable Timers (see page 304)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris®General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 340)
A watchdog timer can generate an interrupt or a reset when a time-out value is reached. The
watchdog timer is used to regain control when a system has failed due to a software error or to the
failure of an external device to respond in the expected way.
The Stellaris®Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
Stellaris® LM3S1110 Microcontroller
1.4.6 Memory Peripherals
The LM3S1110 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 237)
The LM3S1110 static random access memory (SRAM) controller supports 16 KB SRAM. The internal
SRAM of the Stellaris®devices starts at base address 0x2000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.6.2 Flash (see page 238)
The LM3S1110 Flash controller supports 64 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.7 Additional Features
1.4.7.1 JTAG TAP Controller (see page 147)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
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Architectural Overview
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Stellaris®JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core.
This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Stellaris®JTAG instructions select the Stellaris®TDO
outputs. The multiplexer is controlled by the Stellaris®JTAG controller, which has comprehensive
programming for the ARM, Stellaris®, and unimplemented JTAG instructions.
1.4.7.2 System Control and Clocks (see page 159)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
1.4.7.3 Hibernation Module (see page 217)
The Hibernation module provides logic to switch power off to the main processor and peripherals,
and to wake on external or time-based events. The Hibernation module includes power-sequencing
logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt
signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used
for saving state during hibernation.
1.4.8 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 453
■ “Signal Tables” on page 455
■ “Operating Characteristics” on page 479
■ “Electrical Characteristics” on page 480
■ “Package Information” on page 516
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2 The Cortex-M3 Processor
The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the
system requirements of minimal memory implementation, reduced pin count, and low power
consumption, while delivering outstanding computational performance and exceptional system
response to interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Rapid application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
Stellaris® LM3S1110 Microcontroller
■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
■ Optimized for single-cycle flash usage
■ Three sleep modes with clock gating for low power
■ Single-cycle multiply instruction and hardware divide
■ Atomic operations
■ ARM Thumb2 mixed 16-/32-bit instruction set
■ 1.25 DMIPS/MHz
The Stellaris®family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motor control.
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The Cortex-M3 Processor
This chapter provides information on the Stellaris®implementation of the Cortex-M3 processor,
including the programming model, the memory model, the exception model, fault handling, and
power management.
For technical details on the instruction set, see the Cortex™-M3 Instruction Set Technical User's
Manual.
2.1 Block Diagram
The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor delivers
exceptional power efficiency through an efficient instruction set and extensively optimized design,
providing high-end processing hardware including single-cycle 32x32 multiplication and dedicated
hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M3 processor implements tightly coupled
system components that reduce processor area while significantly improving interrupt handling and
system debug capabilities. The Cortex-M3 processor implements a version of the Thumb® instruction
set, ensuring high code density and reduced program memory requirements. The Cortex-M3
instruction set provides the exceptional performance expected of a modern 32-bit architecture, with
the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M3 processor closely integrates a nested interrupt controller (NVIC), to deliver
industry-leading interrupt performance. The Stellaris®NVIC includes a non-maskable interrupt (NMI)
and provides eight interrupt priority levels. The tight integration of the processor core and NVIC
provides fast execution of interrupt service routines (ISRs), dramatically reducing interrupt latency.
The hardware stacking of registers and the ability to suspend load-multiple and store-multiple
operations further reduce interrupt latency. Interrupt handlers do not require any assembler stubs
which removes code overhead from the ISRs. Tail-chaining optimization also significantly reduces
the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC
integrates with the sleep modes, including Deep-sleep mode, which enables the entire device to be
rapidly powered down.
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Figure 2-1. CPU Block Diagram
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Debug
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
Stellaris® LM3S1110 Microcontroller
2.2 Overview
2.2.1 System-Level Interface
The Cortex-M3 processor provides multiple interfaces using AMBA® technology to provide
high-speed, low-latency memory accesses. The core supports unaligned data accesses and
implements atomic bit manipulation that enables faster peripheral controls, system spinlocks, and
thread-safe Boolean data handling.
The Cortex-M3 processor has a memory protection unit (MPU) that provides fine-grain memory
control, enabling applications to implement security privilege levels and separate code, data and
stack on a task-by-task basis.
2.2.2 Integrated Configurable Debug
The Cortex-M3 processor implements a complete hardware debug solution, providing high system
visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire
Debug (SWD) port that is ideal for microcontrollers and other small package devices. The Stellaris
implementation replaces the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. The SWJ-DP interface combines the SWD and
JTAG debug ports into one module. See the ARM® Debug Interface V5 Architecture Specification
for details on SWJ-DP.
For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace
events, a Serial Wire Viewer (SWV) can export a stream of software-generated messages, data
trace, and profiling information through a single pin.
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ATB
Interface
Asynchronous FIFO
APB
Interface
Trace Out
(serializer)
Debug
ATB
Slave
Port
APB
Slave
Port
Serial Wire
Trace Port
(SWO)
The Cortex-M3 Processor
The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators
that debuggers can use. The comparators in the FPB also provide remap functions of up to eight
words in the program code in the CODE memory region. This enables applications stored in a
read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5
Architecture Specification.
2.2.3 Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 42.
Figure 2-2. TPIU Block Diagram
2.2.4 Cortex-M3 System Component Details
The Cortex-M3 includes the following system components:
■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 81).
■ Nested Vectored Interrupt Controller (NVIC)
An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 82).
■ System Control Block (SCB)
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The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system
exceptions( see “System Control Block (SCB)” on page 84).
■ Memory Protection Unit (MPU)
Improves system reliability by defining the memory attributes for different memory regions. The
MPU provides up to eight different regions and an optional predefined background region (see
“Memory Protection Unit (MPU)” on page 84).
2.3 Programming Model
This section describes the Cortex-M3 programming model. In addition to the individual core register
descriptions, information about the processor modes and privilege levels for software execution and
stacks is included.
2.3.1 Processor Mode and Privilege Levels for Software Execution
The Cortex-M3 has two modes of operation:
■ Thread mode
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
■ Handler mode
Used to handle exceptions. When the processor has finished exception processing, it returns to
Thread mode.
In addition, the Cortex-M3 has two privilege levels:
■ Unprivileged
In this mode, software has the following restrictions:
– Limited access to the MSR and MRS instructions and no use of the CPS instruction
– No access to the system timer, NVIC, or system control block
– Possibly restricted access to memory or peripherals
■ Privileged
In this mode, software can use all the instructions and has access to all resources.
In Thread mode, the CONTROL register (see page 57) controls whether software execution is
privileged or unprivileged. In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software
execution in Thread mode. Unprivileged software can use the SVC instruction to make a supervisor
call to transfer control to privileged software.
2.3.2 Stacks
The processor uses a full descending stack, meaning that the stack pointer indicates the last stacked
item on the stack memory. When the processor pushes a new item onto the stack, it decrements
the stack pointer and then writes the item to the new memory location. The processor implements
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SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP
‡
PSP
‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡
Banked version of SP
The Cortex-M3 Processor
two stacks: the main stack and the process stack, with independent copies of the stack pointer (see
the SP register on page 47).
In Thread mode, the CONTROL register (see page 57) controls whether the processor uses the
main stack or the process stack. In Handler mode, the processor always uses the main stack. The
options for processor operations are shown in Table 2-1 on page 44.
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
a. See page 57.
2.3.3 Register Map
Figure 2-3 on page 44 shows the Cortex-M3 register set. Table 2-2 on page 45 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
Figure 2-3. Cortex-M3 Register Set
Stack UsedPrivilege LevelUseProcessor Mode
ApplicationsThread
Privileged or unprivileged
a
Main stack or process stack
Main stackAlways privilegedException handlersHandler
a
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Table 2-2. Processor Register Map
Stellaris® LM3S1110 Microcontroller
DescriptionResetTypeNameOffset
See
page
46Cortex General-Purpose Register 0-R/WR0-
46Cortex General-Purpose Register 1-R/WR1-
46Cortex General-Purpose Register 2-R/WR2-
46Cortex General-Purpose Register 3-R/WR3-
46Cortex General-Purpose Register 4-R/WR4-
46Cortex General-Purpose Register 5-R/WR5-
46Cortex General-Purpose Register 6-R/WR6-
46Cortex General-Purpose Register 7-R/WR7-
46Cortex General-Purpose Register 8-R/WR8-
46Cortex General-Purpose Register 9-R/WR9-
46Cortex General-Purpose Register 10-R/WR10-
46Cortex General-Purpose Register 11-R/WR11-
46Cortex General-Purpose Register 12-R/WR12-
47Stack Pointer-R/WSP-
48Link Register0xFFFF.FFFFR/WLR-
2.3.4 Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 44.
The core registers are not memory mapped and are accessed by register name rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
49Program Counter-R/WPC-
50Program Status Register0x0100.0000R/WPSR-
54Priority Mask Register0x0000.0000R/WPRIMASK-
55Fault Mask Register0x0000.0000R/WFAULTMASK-
56Base Priority Mask Register0x0000.0000R/WBASEPRI-
57Control Register0x0000.0000R/WCONTROL-
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The Cortex-M3 Processor
Register 1: Cortex General-Purpose Register 0 (R0)
Register 2: Cortex General-Purpose Register 1 (R1)
Register 3: Cortex General-Purpose Register 2 (R2)
Register 4: Cortex General-Purpose Register 3 (R3)
Register 5: Cortex General-Purpose Register 4 (R4)
Register 6: Cortex General-Purpose Register 5 (R5)
Register 7: Cortex General-Purpose Register 6 (R6)
Register 8: Cortex General-Purpose Register 7 (R7)
Register 9: Cortex General-Purpose Register 8 (R8)
Register 10: Cortex General-Purpose Register 9 (R9)
Register 11: Cortex General-Purpose Register 10 (R10)
Register 12: Cortex General-Purpose Register 11 (R11)
Register 13: Cortex General-Purpose Register 12 (R12)
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed
from either privileged or unprivileged mode.
Cortex General-Purpose Register 0 (R0)
Type R/W, reset -
16171819202122232425262728293031
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
0123456789101112131415
DATA
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
DescriptionResetTypeNameBit/Field
Register data.-R/WDATA31:0
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Register 14: Stack Pointer (SP)
The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear,
this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be
accessed in either privileged or unprivileged mode.
Stack Pointer (SP)
Type R/W, reset -
SP
SP
Stellaris® LM3S1110 Microcontroller
16171819202122232425262728293031
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
0123456789101112131415
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
DescriptionResetTypeNameBit/Field
This field is the address of the stack pointer.-R/WSP31:0
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The Cortex-M3 Processor
Register 15: Link Register (LR)
The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. LR can be accessed from either privileged or unprivileged mode.
EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 73 for the values and
description.
Link Register (LR)
Type R/W, reset 0xFFFF.FFFF
16171819202122232425262728293031
LINK
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
0123456789101112131415
LINK
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
1111111111111111Reset
DescriptionResetTypeNameBit/Field
This field is the return address.0xFFFF.FFFFR/WLINK31:0
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Register 16: Program Counter (PC)
The Program Counter (PC) is register R15, and it contains the current program address. On reset,
the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit
0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register
can be accessed in either privileged or unprivileged mode.
Program Counter (PC)
Type R/W, reset -
Stellaris® LM3S1110 Microcontroller
16171819202122232425262728293031
PC
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
0123456789101112131415
PC
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
----------------Reset
DescriptionResetTypeNameBit/Field
This field is the current program address.-R/WPC31:0
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The Cortex-M3 Processor
Register 17: Program Status Register (PSR)
Note: This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:
■ Application Program Status Register (APSR), bits 31:27,
■ Execution Program Status Register (EPSR), bits 26:24, 15:10
■ Interrupt Program Status Register (IPSR), bits 5:0
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register
can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or
the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple
instruction. Attempts to read the EPSR directly through application software using the MSR instruction
always return zero. Attempts to write the EPSR using the MSR instruction in application software
are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine
the operation that faulted (see “Exception Entry and Return” on page 71).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example, all of the
registers can be read using PSR with the MRS instruction, or APSR only can be written to using
APSR with the MSR instruction. page 50 shows the possible register combinations for the PSR. See
the MRS and MSR instruction descriptions in the Cortex™-M3 Instruction Set Technical User's Manual
for more information about how to access the program status registers.
Table 2-3. PSR Register Combinations
PSR
IAPSR
EAPSR
a. The processor ignores writes to the IPSR bits.
b. Reads of the EPSR bits return zero, and the processor ignores writes to these bits.
Program Status Register (PSR)
Type R/W, reset 0x0100.0000
a,b
a
b
CombinationTypeRegister
APSR, EPSR, and IPSRR/W
EPSR and IPSRROIEPSR
APSR and IPSRR/W
APSR and EPSRR/W
16171819202122232425262728293031
reservedTHUMBICI / ITQVCZN
ROROROROROROROROROROROR/WR/WR/WR/WR/WType
0000000010000000Reset
0123456789101112131415
ISRNUMreservedICI / IT
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
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Stellaris® LM3S1110 Microcontroller
DescriptionResetTypeNameBit/Field
0R/WN31
0R/WZ30
0R/WC29
APSR Negative or Less Flag
DescriptionValue
The previous operation result was negative or less than.1
The previous operation result was positive, zero, greater than,
0
or equal.
The value of this bit is only meaningful when accessing PSR or APSR.
APSR Zero Flag
DescriptionValue
The previous operation result was zero.1
The previous operation result was non-zero.0
The value of this bit is only meaningful when accessing PSR or APSR.
APSR Carry or Borrow Flag
DescriptionValue
The previous add operation resulted in a carry bit or the previous
1
subtract operation did not result in a borrow bit.
The previous add operation did not result in a carry bit or the
0
previous subtract operation resulted in a borrow bit.
The value of this bit is only meaningful when accessing PSR or APSR.
0R/WV28
0R/WQ27
APSR Overflow Flag
DescriptionValue
The previous operation resulted in an overflow.1
The previous operation did not result in an overflow.0
The value of this bit is only meaningful when accessing PSR or APSR.
APSR DSP Overflow and Saturation Flag
DescriptionValue
DSP Overflow or saturation has occurred.1
DSP overflow or saturation has not occurred since reset or since
0
the bit was last cleared.
The value of this bit is only meaningful when accessing PSR or APSR.
This bit is cleared by software using an MRS instruction.
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The Cortex-M3 Processor
DescriptionResetTypeNameBit/Field
0x0ROICI / IT26:25
1ROTHUMB24
EPSR ICI / IT status
These bits, along with bits 15:10, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When EPSR holds the ICI execution state, bits 26:25 are zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3 Instruction Set Technical User's Manual
for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
EPSR Thumb State
This bit indicates the Thumb state and should always be set.
The following can clear the THUMB bit:
■ The BLX, BX and POP{PC} instructions
■ Restoration from the stacked xPSR value on an exception return
■ Bit 0 of the vector value on an exception entry
Attempting to execute instructions when this bit is clear results in a fault
or lockup. See “Lockup” on page 76 for more information.
The value of this bit is only meaningful when accessing PSR or EPSR.
0x00ROreserved23:16
0x0ROICI / IT15:10
0x0ROreserved9:6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
EPSR ICI / IT status
These bits, along with bits 26:25, contain the Interruptible-Continuable
Instruction (ICI) field for an interrupted load multiple or store multiple
instruction or the execution state bits of the IT instruction.
When an interrupt occurs during the execution of an LDM, STM, PUSH
or POP instruction, the processor stops the load multiple or store multiple
instruction operation temporarily and stores the next register operand
in the multiple operation to bits 15:12. After servicing the interrupt, the
processor returns to the register pointed to by bits 15:12 and resumes
execution of the multiple load or store instruction. When EPSR holds
the ICI execution state, bits 11:10 are zero.
The If-Then block contains up to four instructions following a 16-bit IT
instruction. Each instruction in the block is conditional. The conditions
for the instructions are either all the same, or some can be the inverse
of others. See the Cortex™-M3 Instruction Set Technical User's Manual
for more information.
The value of this field is only meaningful when accessing PSR or EPSR.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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DescriptionResetTypeNameBit/Field
0x00ROISRNUM5:0
IPSR ISR Number
This field contains the exception type number of the current Interrupt
Service Routine (ISR).
DescriptionValue
Thread mode0x00
Reserved0x01
NMI0x02
Hard fault0x03
Memory management fault0x04
Bus fault0x05
Usage fault0x06
Reserved0x07-0x0A
SVCall0x0B
Reserved for Debug0x0C
Reserved0x0D
PendSV0x0E
SysTick0x0F
Interrupt Vector 00x10
Interrupt Vector 10x11
......
Interrupt Vector 430x3B
Reserved0x3C-0x3F
See “Exception Types” on page 67 for more information.
The value of this field is only meaningful when accessing PSR or IPSR.
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The Cortex-M3 Processor
Register 18: Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions
should be disabled when they might impact the timing of critical tasks. This register is only accessible
in privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and
the CPS instruction may be used to change the value of the PRIMASK register. See the Cortex™-M3
Instruction Set Technical User's Manual for more information on these instructions. For more
information on exception priority levels, see “Exception Types” on page 67.
Priority Mask Register (PRIMASK)
Type R/W, reset 0x0000.0000
reserved
16171819202122232425262728293031
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
PRIMASKreserved
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
0x0000.000ROreserved31:1
0R/WPRIMASK0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Priority Mask
DescriptionValue
Prevents the activation of all exceptions with configurable
1
priority.
No effect.0
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Register 19: Fault Mask Register (FAULTMASK)
The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt
(NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register
is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register. See the Cortex™-M3 Instruction Set Technical User's Manual for more information on
these instructions. For more information on exception priority levels, see “Exception
Types” on page 67.
Fault Mask Register (FAULTMASK)
Type R/W, reset 0x0000.0000
reserved
reserved
Stellaris® LM3S1110 Microcontroller
16171819202122232425262728293031
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
FAULTMASK
R/WROROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
0x0000.000ROreserved31:1
0R/WFAULTMASK0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Mask
DescriptionValue
Prevents the activation of all exceptions except for NMI.1
No effect.0
The processor clears the FAULTMASK bit on exit from any exception
handler except the NMI handler.
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The Cortex-M3 Processor
Register 20: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority
level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of
critical tasks. This register is only accessible in privileged mode. For more information on exception
priority levels, see “Exception Types” on page 67.
Base Priority Mask Register (BASEPRI)
Type R/W, reset 0x0000.0000
reserved
DescriptionResetTypeNameBit/Field
16171819202122232425262728293031
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reservedBASEPRIreserved
ROROROROROR/WR/WR/WROROROROROROROROType
0000000000000000Reset
0x0000.00ROreserved31:8
0x0R/WBASEPRI7:5
0x0ROreserved4:0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Base Priority
Any exception that has a programmable priority level with the same or
lower priority as the value of this field is masked. The PRIMASK register
can be used to mask all exceptions with programmable priority levels.
Higher priority exceptions have lower priority levels.
DescriptionValue
All exceptions are unmasked.0x0
All exceptions with priority level 1-7 are masked.0x1
All exceptions with priority level 2-7 are masked.0x2
All exceptions with priority level 3-7 are masked.0x3
All exceptions with priority level 4-7 are masked.0x4
All exceptions with priority level 5-7 are masked.0x5
All exceptions with priority level 6-7 are masked.0x6
All exceptions with priority level 7 are masked.0x7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
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Register 21: Control Register (CONTROL)
The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode. This register is only accessible in privileged mode.
Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the
CONTROL register when in Handler mode. The exception entry and return mechanisms automatically
update the CONTROL register based on the EXC_RETURN value (see Table 2-10 on page 73).
In an OS environment, threads running in Thread mode should use the process stack and the kernel
and exception handlers should use the main stack. By default, Thread mode uses MSP. To switch
the stack pointer used in Thread mode to PSP, either use the MSR instruction to set the ASP bit, as
detailed in the Cortex™-M3 Instruction Set Technical User's Manual, or perform an exception return
to Thread mode with the appropriate EXC_RETURN value, as shown in Table 2-10 on page 73.
Note: When changing the stack pointer, software must use an ISB instruction immediately after
the MSR instruction, ensuring that instructions after the ISB execute use the new stack
pointer. See the Cortex™-M3 Instruction Set Technical User's Manual.
Control Register (CONTROL)
Type R/W, reset 0x0000.0000
reserved
Stellaris® LM3S1110 Microcontroller
16171819202122232425262728293031
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TMPLASPreserved
R/WR/WROROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
0x0000.000ROreserved31:2
0R/WASP1
0R/WTMPL0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Active Stack Pointer
DescriptionValue
PSP is the current stack pointer.1
MSP is the current stack pointer0
In Handler mode, this bit reads as zero and ignores writes. The
Cortex-M3 updates this bit automatically on exception return.
Thread Mode Privilege Level
DescriptionValue
Unprivileged software can be executed in Thread mode.1
Only privileged software can be executed in Thread mode.0
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2.3.5 Exceptions and Interrupts
The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested
Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the
normal flow of software control. The processor uses Handler mode to handle all exceptions except
for reset. See “Exception Entry and Return” on page 71 for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller
(NVIC)” on page 82 for more information.
2.3.6 Data Types
The Cortex-M3 supports 32-bit words, 16-bit halfwords, and 8-bit bytes. The processor also supports
64-bit data transfer instructions. All instruction and data memory accesses are little endian. See
“Memory Regions, Types and Attributes” on page 59 for more information.
2.4 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the
bit-banding features. The processor has a fixed memory map that provides up to 4 GB of addressable
memory.
The memory map for the LM3S1110 controller is provided in Table 2-4 on page 58. In this manual,
register addresses are given as a hexadecimal increment, relative to the module’s base address
as shown in the memory map.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic
operations to bit data (see “Bit-Banding” on page 62).
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see “Cortex-M3 Peripherals” on page 81).
Note: Within the memory map, all reserved space returns a bus fault when read or written.
Table 2-4. Memory Map
Memory
FiRM Peripherals
DescriptionEndStart
Reserved0x3FFF.FFFF0x2208.0000
For details,
see page ...
238On-chip Flash0x0000.FFFF0x0000.0000
-Reserved0x1FFF.FFFF0x0001.0000
237Bit-banded on-chip SRAM0x2000.3FFF0x2000.0000
-Reserved0x21FF.FFFF0x2000.4000
237Bit-band alias of 0x2000.0000 through 0x200F.FFFF0x2207.FFFF0x2200.0000
-
343Watchdog timer 00x4000.0FFF0x4000.0000
-Reserved0x4000.3FFF0x4000.1000
269GPIO Port A0x4000.4FFF0x4000.4000
269GPIO Port B0x4000.5FFF0x4000.5000
269GPIO Port C0x4000.6FFF0x4000.6000
269GPIO Port D0x4000.7FFF0x4000.7000
416SSI00x4000.8FFF0x4000.8000
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Table 2-4. Memory Map (continued)
Stellaris® LM3S1110 Microcontroller
Peripherals
Private Peripheral Bus
DescriptionEndStart
Reserved0x4001.FFFF0x4000.E000
Reserved0xDFFF.FFFF0x4400.0000
Reserved0xFFFF.FFFF0xE004.1000
For details,
see page ...
-Reserved0x4000.BFFF0x4000.9000
371UART00x4000.CFFF0x4000.C000
371UART10x4000.DFFF0x4000.D000
-
-Reserved0x4002.3FFF0x4002.0000
269GPIO Port E0x4002.4FFF0x4002.4000
269GPIO Port F0x4002.5FFF0x4002.5000
269GPIO Port G0x4002.6FFF0x4002.6000
269GPIO Port H0x4002.7FFF0x4002.7000
-Reserved0x4002.FFFF0x4002.8000
315Timer 00x4003.0FFF0x4003.0000
315Timer 10x4003.1FFF0x4003.1000
315Timer 20x4003.2FFF0x4003.2000
-Reserved0x4003.BFFF0x4003.3000
442Analog Comparators0x4003.CFFF0x4003.C000
-Reserved0x400F.BFFF0x4003.D000
224Hibernation Module0x400F.CFFF0x400F.C000
242Flash memory control0x400F.DFFF0x400F.D000
172System control0x400F.EFFF0x400F.E000
-Reserved0x41FF.FFFF0x400F.F000
-Bit-banded alias of 0x4000.0000 through 0x400F.FFFF0x43FF.FFFF0x4200.0000
-
41Instrumentation Trace Macrocell (ITM)0xE000.0FFF0xE000.0000
41Data Watchpoint and Trace (DWT)0xE000.1FFF0xE000.1000
41Flash Patch and Breakpoint (FPB)0xE000.2FFF0xE000.2000
-Reserved0xE000.DFFF0xE000.3000
66Cortex-M3 Peripherals (SysTick, NVIC, SCB and MPU)0xE000.EFFF0xE000.E000
-Reserved0xE003.FFFF0xE000.F000
42Trace Port Interface Unit (TPIU)0xE004.0FFF0xE004.0000
-
2.4.1 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region
has a defined memory type, and some regions have additional memory attributes. The memory
type and attributes determine the behavior of accesses to the region.
The memory types are:
■ Normal: The processor can re-order transactions for efficiency and perform speculative reads.
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■ Device: The processor preserves transaction order relative to other transactions to Device or
Strongly Ordered memory.
■ Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents
instruction accesses. A fault exception is generated only on execution of an instruction executed
from an XN region.
2.4.2 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system
does not guarantee that the order in which the accesses complete matches the program order of
the instructions, providing the order does not affect the behavior of the instruction sequence. Normally,
if correct program execution depends on two memory accesses completing in program order,
software must insert a memory barrier instruction between the memory access instructions (see
“Software Ordering of Memory Accesses” on page 61).
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either
Device or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always
observed before A2.
2.4.3 Behavior of Memory Accesses
Table 2-5 on page 60 shows the behavior of accesses to each region in the memory map. See
“Memory Regions, Types and Attributes” on page 59 for more information on memory types and
the XN attribute. Stellaris®devices may have reserved memory areas within the address ranges
shown below (refer to Table 2-4 on page 58 for more information).
Table 2-5. Memory Access Behavior
0xE000.0000- 0xE00F.FFFF
Private peripheral
bus
Memory TypeMemory RegionAddress Range
Ordered
Never
(XN)
-NormalCode0x0000.0000 - 0x1FFF.FFFF
-NormalSRAM0x2000.0000 - 0x3FFF.FFFF
XNDevicePeripheral0x4000.0000 - 0x5FFF.FFFF
XNStrongly
DescriptionExecute
This executable region is for program code.
Data can also be stored here.
This executable region is for data. Code
can also be stored here. This region
includes bit band and bit band alias areas
(see Table 2-6 on page 62).
This region includes bit band and bit band
alias areas (see Table 2-7 on page 62).
This executable region is for data.-NormalExternal RAM0x6000.0000 - 0x9FFF.FFFF
This region is for external device memory.XNDeviceExternal device0xA000.0000 - 0xDFFF.FFFF
This region includes the NVIC, system
timer, and system control block.
---Reserved0xE010.0000- 0xFFFF.FFFF
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M3 has separate buses that can perform
instruction fetches and data accesses simultaneously.
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The MPU can override the default memory access behavior described in this section. For more
information, see “Memory Protection Unit (MPU)” on page 84.
The Cortex-M3 prefetches instructions ahead of execution and speculatively prefetches from branch
target addresses.
2.4.4 Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions for the following reasons:
■ The processor can reorder some memory accesses to improve efficiency, providing this does
not affect the behavior of the instruction sequence.
■ The processor has multiple bus interfaces.
■ Memory or devices in the memory map have different wait states.
■ Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” on page 60 describes the cases where the memory
system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is
critical, software must include memory barrier instructions to force that ordering. The Cortex-M3
has the following memory barrier instructions:
Stellaris® LM3S1110 Microcontroller
■ The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions
complete before subsequent memory transactions.
■ The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
■ The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
■ MPU programming
– If the MPU settings are changed and the change must be effective on the very next instruction,
use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of
context switching.
– Use an ISB instruction to ensure the new MPU setting takes effect immediately after
programming the MPU region or regions, if the MPU configuration code was accessed using
a branch or call. If the MPU configuration code is entered using exception mechanisms, then
an ISB instruction is not required.
■ Vector table
If the program changes an entry in the vector table and then enables the corresponding exception,
use a DMB instruction between the operations. The DMB instruction ensures that if the exception
is taken immediately after being enabled, the processor uses the new exception vector.
■ Self-modifying code
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The Cortex-M3 Processor
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses
the updated program.
■ Memory map switching
If the system contains a memory map switching mechanism, use a DSB instruction after switching
the memory map in the program. The DSB instruction ensures subsequent instruction execution
uses the updated memory map.
■ Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require
the use of DMB instructions.
For more information on the memory barrier instructions, see the Cortex™-M3 Instruction Set
Technical User's Manual.
2.4.5 Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. Accesses
to the 32-MB SRAM alias region map to the 1-MB SRAM bit-band region, as shown in Table
2-6 on page 62. Accesses to the 32-MB peripheral alias region map to the 1-MB peripheral bit-band
region, as shown in Table 2-7 on page 62. For the specific address range of the bit-band regions,
see Table 2-4 on page 58.
Note: A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory,
and similarly for halfword and byte accesses. This allows bit band accesses to match the
access requirements of the underlying peripheral.
Table 2-6. SRAM Memory Bit-Banding Regions
Instruction and Data AccessesMemory RegionAddress Range
SRAM bit-band region0x2000.0000 - 0x200F.FFFF
SRAM bit-band alias0x2200.0000 - 0x23FF.FFFF
Direct accesses to this memory range behave as SRAM memory
accesses, but this region is also bit addressable through bit-band
alias.
Data accesses to this region are remapped to bit band region.
A write operation is performed as read-modify-write. Instruction
accesses are not remapped.
Table 2-7. Peripheral Memory Bit-Banding Regions
Instruction and Data AccessesMemory RegionAddress Range
Peripheral bit-band region0x4000.0000 - 0x400F.FFFF
Peripheral bit-band alias0x4200.0000 - 0x43FF.FFFF
Direct accesses to this memory range behave as peripheral
memory accesses, but this region is also bit addressable through
bit-band alias.
Data accesses to this region are remapped to bit band region.
A write operation is performed as read-modify-write. Instruction
accesses are not permitted.
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The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
bit_word_offset
The position of the target bit in the bit-band memory region.
bit_word_addr
The address of the word in the alias memory region that maps to the targeted bit.
bit_band_base
The starting address of the alias region.
byte_offset
The number of the byte in the bit-band region that contains the targeted bit.
bit_number
The bit position, 0-7, of the targeted bit.
Figure 2-4 on page 64 shows examples of bit-band mapping between the SRAM bit-band alias
region and the SRAM bit-band region:
■ The alias word at 0x23FF.FFE0 maps to bit 0 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFE0 = 0x2200.0000 + (0x000F.FFFF*32) + (0*4)
■ The alias word at 0x23FF.FFFC maps to bit 7 of the bit-band byte at 0x200F.FFFF:
0x23FF.FFFC = 0x2200.0000 + (0x000F.FFFF*32) + (7*4)
■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000:
0x2200.0000 = 0x2200.0000 + (0*32) + (0*4)
■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000:
0x2200.001C = 0x2200.0000+ (0*32) + (7*4)
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0x23FF.FFE4
0x2200.0004
0x23FF.FFE00x23FF.FFE80x23FF.FFEC0x23FF.FFF00x23FF.FFF40x23FF.FFF80x23FF.FFFC
0x2200.00000x2200.00140x2200.00180x2200.001C 0x2200.00080x2200.0010 0x2200.000C
32-MB Alias Region
0
7 0
07
0x2000.00000x2000.00010x2000.00020x2000.0003
6 5 4 3 2 1 07 6 5 4 3 2 1 7 6 5 4 3 2 1 07 6 5 4 3 2 1
07 6 5 4 3 2 1 6 5 4 3 2 107 6 5 4 3 2 1 07 6 5 4 3 2 1
0x200F.FFFC0x200F.FFFD0x200F.FFFE0x200F.FFFF
1-MB SRAM Bit-Band Region
The Cortex-M3 Processor
Figure 2-4. Bit-Band Mapping
2.4.5.1 Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit 0 of the value written to a word in the alias region determines the value written to the targeted
bit in the bit-band region. Writing a value with bit 0 set writes a 1 to the bit-band bit, and writing a
value with bit 0 clear writes a 0 to the bit-band bit.
Bits 31:1 of the alias word have no effect on the bit-band bit. Writing 0x01 has the same effect as
writing 0xFF. Writing 0x00 has the same effect as writing 0x0E.
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.
2.4.5.2 Directly Accessing a Bit-Band Region
“Behavior of Memory Accesses” on page 60 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.
2.4.6 Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 65 illustrates how data is stored.
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Figure 2-5. Data Storage
Memory Register
Address A
A+1
lsbyte
msbyte
A+2
A+3
07
B0B1B3 B2
31 24 23 16 15 8 7 0
B0
B1
B2
B3
2.4.7 Synchronization Primitives
The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
Stellaris® LM3S1110 Microcontroller
■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write is performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
■ The word instructions LDREX and STREX
■ The halfword instructions LDREXH and STREXH
■ The byte instructions LDREXB and STREXB
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform a guaranteed read-modify-write of a memory location, software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Update the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location,
and test the returned status bit. If the status bit is clear, the read-modify-write completed
successfully; if the status bit is set, no write was performed, which indicates that the value
returned at step 1 might be out of date. The software must retry the read-modify-write sequence.
Software can use the synchronization primitives to implement a semaphore as follows:
1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the
semaphore is free.
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2. If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive succeeded, then the
software has claimed the semaphore. However, if the Store-Exclusive failed, another process
might have claimed the semaphore after the software performed step 1.
The Cortex-M3 includes an exclusive access monitor that tags the fact that the processor has
executed a Load-Exclusive instruction. The processor removes its exclusive access tag if:
■ It executes a CLREX instruction.
■ It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
■ An exception occurs, which means the processor can resolve semaphore conflicts between
different threads.
For more information about the synchronization primitive instructions, see the Cortex™-M3 Instruction
Set Technical User's Manual.
2.5 Exception Model
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 2-8 on page 68 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 23 interrupts (listed in Table 2-9 on page 69).
Priorities on the system handlers are set with the NVIC System Handler Priority n (SYSPRIn)
registers. Interrupts are enabled through the NVIC Interrupt Set Enable n (ENn) register and
prioritized with the NVIC Interrupt Priority n (PRIn) registers. Priorities can be grouped by splitting
priority levels into preemption priorities and subpriorities. All the interrupt registers are described in
“Nested Vectored Interrupt Controller (NVIC)” on page 82.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
Important: After a write to clear an interrupt source, it may take several processor cycles for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See “Nested Vectored Interrupt Controller (NVIC)” on page 82 for more information on exceptions
and interrupts.
2.5.1 Exception States
Each exception is in one of the following states:
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■ Inactive. The exception is not active and not pending.
■ Pending. The exception is waiting to be serviced by the processor. An interrupt request from a
peripheral or from software can change the state of the corresponding interrupt to pending.
■ Active. An exception that is being serviced by the processor but has not completed.
Note: An exception handler can interrupt the execution of another exception handler. In this
case, both exceptions are in the active state.
■ Active and Pending. The exception is being serviced by the processor, and there is a pending
exception from the same source.
2.5.2 Exception Types
The exception types are:
■ Reset. Reset is invoked on power up or a warm reset. The exception model treats reset as a
special form of exception. When reset is asserted, the operation of the processor stops, potentially
at any point in an instruction. When reset is deasserted, execution restarts from the address
provided by the reset entry in the vector table. Execution restarts as privileged execution in
Thread mode.
Stellaris® LM3S1110 Microcontroller
■ NMI. A non-maskable Interrupt (NMI) can be signaled using the NMI signal or triggered by
software using the Interrupt Control and State (INTCTRL) register. This exception has the
highest priority other than reset. NMI is permanently enabled and has a fixed priority of -2. NMIs
cannot be masked or prevented from activation by any other exception or preempted by any
exception other than reset.
■ Hard Fault. A hard fault is an exception that occurs because of an error during exception
processing, or because an exception cannot be managed by any other exception mechanism.
Hard faults have a fixed priority of -1, meaning they have higher priority than any exception with
configurable priority.
■ Memory Management Fault. A memory management fault is an exception that occurs because
of a memory protection related fault, including access violation and no match. The MPU or the
fixed memory protection constraints determine this fault, for both instruction and data memory
transactions. This fault is used to abort instruction accesses to Execute Never (XN) memory
regions, even if the MPU is disabled.
■ Bus Fault. A bus fault is an exception that occurs because of a memory-related fault for an
instruction or data memory transaction such as a prefetch fault or a memory access fault. This
fault can be enabled or disabled.
■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
– An undefined instruction
– An illegal unaligned access
– Invalid state on instruction execution
– An error on exception return
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The Cortex-M3 Processor
An unaligned address on a word or halfword memory access or division by zero can cause a
usage fault when the core is properly configured.
■ SVCall. A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an
OS environment, applications can use SVC instructions to access OS kernel functions and device
drivers.
■ Debug Monitor. This exception is caused by the debug monitor (when not halting). This exception
is only active when enabled. This exception does not activate if it is a lower priority than the
current activation.
■ PendSV. PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is
triggered using the Interrupt Control and State (INTCTRL) register.
■ SysTick. A SysTick exception is an exception that the system timer generates when it reaches
zero when it is enabled to generate an interrupt. Software can also generate a SysTick exception
using the Interrupt Control and State (INTCTRL) register. In an OS environment, the processor
can use this exception as system tick.
■ Interrupt (IRQ). An interrupt, or IRQ, is an exception signaled by a peripheral or generated by
a software request and fed through the NVIC (prioritized). All interrupts are asynchronous to
instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Table 2-9 on page 69 lists the interrupts on the LM3S1110 controller.
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-8 on page 68 shows as having
configurable priority (see the SYSHNDCTRL register on page 124 and the DIS0 register on page 98).
For more information about hard faults, memory management faults, bus faults, and usage faults,
see “Fault Handling” on page 74.
Table 2-8. Exception Types
Exception Type
(NMI)
Vector
Number
4Memory Management
5Bus Fault
6Usage Fault
11SVCall
12Debug Monitor
14PendSV
Priority
a
b
Offset
0x0000.0000-0-
c
c
c
c
c
c
0x0000.0014programmable
ActivationVector Address or
Stack top is loaded from the first
entry of the vector table on reset.
Asynchronous0x0000.0004-3 (highest)1Reset
Asynchronous0x0000.0008-22Non-Maskable Interrupt
-0x0000.000C-13Hard Fault
Synchronous0x0000.0010programmable
Synchronous when precise and
asynchronous when imprecise
Synchronous0x0000.0018programmable
Reserved--7-10-
Synchronous0x0000.002Cprogrammable
Synchronous0x0000.0030programmable
Reserved--13-
Asynchronous0x0000.0038programmable
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Table 2-8. Exception Types (continued)
a
Exception Type
Vector
Priority
Number
15SysTick
16 and aboveInterrupts
a. 0 is the default priority for all the programmable priorities.
b. See “Vector Table” on page 70.
c. See page 121.
d. See page 121.
e. See page 106.
Table 2-9. Interrupts
Stellaris® LM3S1110 Microcontroller
b
Offset
d
e
ActivationVector Address or
Asynchronous0x0000.003Cprogrammable
Asynchronous0x0000.0040 and aboveprogrammable
Vector Number
Interrupt Number (Bit
in Interrupt Registers)
-0-15
DescriptionVector Address or
Offset
Processor exceptions0x0000.0000 -
0x0000.003C
GPIO Port A0x0000.0040016
GPIO Port B0x0000.0044117
GPIO Port C0x0000.0048218
GPIO Port D0x0000.004C319
GPIO Port E0x0000.0050420
UART00x0000.0054521
UART10x0000.0058622
SSI00x0000.005C723
Reserved8-1724-33
Watchdog Timer 00x0000.00881834
Timer 0A0x0000.008C1935
Timer 0B0x0000.00902036
Timer 1A0x0000.00942137
Timer 1B0x0000.00982238
Timer 2A0x0000.009C2339
Timer 2B0x0000.00A02440
Analog Comparator 00x0000.00A42541
Analog Comparator 10x0000.00A82642
Reserved2743
System Control0x0000.00B02844
Flash Memory Control0x0000.00B42945
GPIO Port F0x0000.00B83046
GPIO Port G0x0000.00BC3147
GPIO Port H0x0000.00C03248
Reserved33-4249-58
Hibernation Module0x0000.00EC4359
Reserved44-5460-70
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Initial SP value
Reset
Hard fault
NMI
Memory management fault
Usage fault
Bus fault
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
Reserved
SVCall
PendSV
Reserved for Debug
Systick
IRQ0
Reserved
0x002C
0x0038
0x003C
0x0040
OffsetException number
2
3
4
5
6
11
12
14
15
16
18
13
7
10
1
Vector
.
.
.
8
9
IRQ1
IRQ2
0x0044
IRQ43
17
0x0048
0x004C
59
.
.
.
.
.
.
0x00EC
IRQ number
-14
-13
-12
-11
-10
-5
-2
-1
0
2
1
43
The Cortex-M3 Processor
2.5.3 Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
■ Fault Handlers. Hard fault, memory management fault, usage fault, and bus fault are fault
exceptions handled by the fault handlers.
■ System Handlers. NMI, PendSV, SVCall, SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.5.4 Vector Table
The vector table contains the reset value of the stack pointer and the start addresses, also called
exception vectors, for all exception handlers. The vector table is constructed using the vector address
or offset shown in Table 2-8 on page 68. Figure 2-6 on page 70 shows the order of the exception
vectors in the vector table. The least-significant bit of each vector must be 1, indicating that the
exception handler is Thumb code
Figure 2-6. Vector table
On system reset, the vector table is fixed at address 0x0000.0000. Privileged software can write to
the Vector Table Offset (VTABLE) register to relocate the vector table start address to a different
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memory location, in the range 0x0000.0100 to 0x3FFF.FF00 (see “Vector Table” on page 70). Note
that when configuring the VTABLE register, the offset must be aligned on a 256-byte boundary.
2.5.5 Exception Priorities
As Table 2-8 on page 68 shows, all exceptions have an associated priority, with a lower priority
value indicating a higher priority and configurable priorities for all exceptions except Reset, Hard
fault, and NMI. If software does not configure any priorities, then all exceptions with a configurable
priority have a priority of 0. For information about configuring exception priorities, see page 121 and
page 106.
Note: Configurable priority values for the Stellaris®implementation are in the range 0-7. This
means that the Reset, Hard fault, and NMI exceptions, with fixed negative priority values,
always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means
that IRQ[1] has higher priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed
before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest exception
number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same
priority, then IRQ[0] is processed before IRQ[1].
Stellaris® LM3S1110 Microcontroller
When the processor is executing an exception handler, the exception handler is preempted if a
higher priority exception occurs. If an exception occurs with the same priority as the exception being
handled, the handler is not preempted, irrespective of the exception number. However, the status
of the new interrupt changes to pending.
2.5.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This
grouping divides each interrupt priority register entry into two fields:
■ An upper field that defines the group priority
■ A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is
executing an interrupt exception handler, another interrupt with the same group priority as the
interrupt being handled does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order
in which they are processed. If multiple pending interrupts have the same group priority and
subpriority, the interrupt with the lowest IRQ number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see
page 115.
2.5.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
■ Preemption. When the processor is executing an exception handler, an exception can preempt
the exception handler if its priority is higher than the priority of the exception being handled. See
“Interrupt Priority Grouping” on page 71 for more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See
“Exception Entry” on page 72 more information.
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Pre-IRQ top of stack
xPSR
PC
LR
R12
R3
R2
R1
R0
{aligner}
IRQ top of stack
...
The Cortex-M3 Processor
■ Return. Return occurs when the exception handler is completed, and there is no pending
exception with sufficient priority to be serviced and the completed exception handler was not
handling a late-arriving exception. The processor pops the stack and restores the processor
state to the state it had before the interrupt occurred. See “Exception Return” on page 73 for
more information.
■ Tail-Chaining. This mechanism speeds up exception servicing. On completion of an exception
handler, if there is a pending exception that meets the requirements for exception entry, the
stack pop is skipped and control transfers to the new exception handler.
■ Late-Arriving. This mechanism speeds up preemption. If a higher priority exception occurs
during state saving for a previous exception, the processor switches to handle the higher priority
exception and initiates the vector fetch for that exception. State saving is not affected by late
arrival because the state saved is the same for both exceptions. Therefore, the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction
of the exception handler of the original exception enters the execute stage of the processor. On
return from the exception handler of the late-arriving exception, the normal tail-chaining rules
apply.
2.5.7.1 Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the
processor is in Thread mode or the new exception is of higher priority than the exception being
handled, in which case the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers
(see PRIMASK on page 54, FAULTMASK on page 55, and BASEPRI on page 56). An exception
with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred to as
stacking and the structure of eight data words is referred to as stack frame.
Figure 2-7. Exception Stack Frame
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. Unless
stack alignment is disabled, the stack frame is aligned to a double-word address. If the STKALIGN
bit of the Configuration Control (CCR) register is set, stack align adjustment is performed during
stacking.
The stack frame includes the return address, which is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
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In parallel to the stacking operation, the processor performs a vector fetch that reads the exception
handler start address from the vector table. When stacking is complete, the processor starts executing
the exception handler. At the same time, the processor writes an EXC_RETURN value to the LR,
indicating which stack pointer corresponds to the stack frame and what operation mode the processor
was in before the entry occurred.
If no higher-priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt to
active.
If another higher-priority exception occurs during exception entry, known as late arrival, the processor
starts executing the exception handler for this exception and does not change the pending status
of the earlier exception.
2.5.7.2 Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
■ An LDM or POP instruction that loads the PC
■ A BX instruction using any register
Stellaris® LM3S1110 Microcontroller
■ An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest four
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 73
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
DescriptionEXC_RETURN[31:0]
Reserved0xFFFF.FFF0
0xFFFF.FFF1
0xFFFF.FFF9
0xFFFF.FFFD
Return to Handler mode.
Exception return uses state from MSP.
Execution uses MSP after return.
Reserved0xFFFF.FFF2 - 0xFFFF.FFF8
Return to Thread mode.
Exception return uses state from MSP.
Execution uses MSP after return.
Reserved0xFFFF.FFFA - 0xFFFF.FFFC
Return to Thread mode.
Exception return uses state from PSP.
Execution uses PSP after return.
Reserved0xFFFF.FFFE - 0xFFFF.FFFF
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2.6 Fault Handling
Faults are a subset of the exceptions (see “Exception Model” on page 66). The following conditions
generate a fault:
■ A bus error on an instruction fetch or vector table load or a data access.
■ An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.
■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
■ An MPU fault because of a privilege violation or an attempt to access an unmanaged region.
2.6.1 Fault Types
Table 2-11 on page 74 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 128 for more
information about the fault status registers.
Table 2-11. Faults
Bit NameFault Status RegisterHandlerFault
VECTHard Fault Status (HFAULTSTAT)Hard faultBus error on a vector read
FORCEDHard Fault Status (HFAULTSTAT)Hard faultFault escalated to a hard fault
a
MPU or default memory mismatch on
instruction access
MPU or default memory mismatch on
data access
MPU or default memory mismatch on
exception stacking
MPU or default memory mismatch on
exception unstacking
set state
a. Occurs on an access to an XN region even if the MPU is disabled.
b. Attempting to use an instruction set other than the Thumb instruction set, or returning to a non load-store-multiple instruction
b
with ICI continuation.
Memory management
fault
Memory management
fault
Memory management
fault
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
(MFAULTSTAT)
(MFAULTSTAT)
(MFAULTSTAT)
IERR
DERRMemory Management Fault Status
MSTKEMemory Management Fault Status
MUSTKEMemory Management Fault Status
BSTKEBus Fault Status (BFAULTSTAT)Bus faultBus error during exception stacking
BUSTKEBus Fault Status (BFAULTSTAT)Bus faultBus error during exception unstacking
IBUSBus Fault Status (BFAULTSTAT)Bus faultBus error during instruction prefetch
PRECISEBus Fault Status (BFAULTSTAT)Bus faultPrecise data bus error
IMPREBus Fault Status (BFAULTSTAT)Bus faultImprecise data bus error
NOCPUsage Fault Status (UFAULTSTAT)Usage faultAttempt to access a coprocessor
UNDEFUsage Fault Status (UFAULTSTAT)Usage faultUndefined instruction
INVSTATUsage Fault Status (UFAULTSTAT)Usage faultAttempt to enter an invalid instruction
INVPCUsage Fault Status (UFAULTSTAT)Usage faultInvalid EXC_RETURN value
UNALIGNUsage Fault Status (UFAULTSTAT)Usage faultIllegal unaligned load or store
DIV0Usage Fault Status (UFAULTSTAT)Usage faultDivide by 0
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2.6.2 Fault Escalation and Hard Faults
All fault exceptions except for hard fault have configurable exception priority (see SYSPRI1 on
page 121). Software can disable execution of the handlers for these faults (see SYSHNDCTRL on
page 124).
Usually, the exception priority, together with the values of the exception mask registers, determines
whether the processor enters the fault handler, and whether a fault handler can preempt another
fault handler as described in “Exception Model” on page 66.
In some situations, a fault with configurable priority is treated as a hard fault. This process is called
priority escalation, and the fault is described as escalated to hard fault. Escalation to hard fault
occurs when:
■ A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard
fault occurs because a fault handler cannot preempt itself because it must have the same priority
as the current priority level.
■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This
situation happens because the handler for the new fault cannot preempt the currently executing
fault handler.
Stellaris® LM3S1110 Microcontroller
■ An exception handler causes a fault for which the priority is the same as or lower than the currently
executing exception.
■ A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not
escalate to a hard fault. Thus if a corrupted stack causes a fault, the fault handler executes even
though the stack push for the handler failed. The fault handler operates but the stack contents are
corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any
exception other than Reset, NMI, or another hard fault.
2.6.3 Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management
faults, the fault address register indicates the address accessed by the operation that caused the
fault, as shown in Table 2-12 on page 75.
Table 2-12. Fault Status and Fault Address Registers
Memory management
fault
Memory Management Fault Status
(MFAULTSTAT)
Bus Fault Status (BFAULTSTAT)Bus fault
Memory Management Fault
Address (MMADDR)
Bus Fault Address
(FAULTADDR)
Register DescriptionAddress Register NameStatus Register NameHandler
page 134-Hard Fault Status (HFAULTSTAT)Hard fault
page 128
page 136
page 128
page 137
page 128-Usage Fault Status (UFAULTSTAT)Usage fault
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The Cortex-M3 Processor
2.6.4 Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault
handlers. When the processor is in the lockup state, it does not execute any instructions. The
processor remains in lockup state until it is reset or an NMI occurs.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the
processor to leave the lockup state.
2.7 Power Management
The Cortex-M3 processor sleep modes reduce power consumption:
■ Sleep mode stops the processor clock.
■ Deep-sleep mode stops the system clock and switches off the PLL and Flash memory.
The SLEEPDEEP bit of the System Control (SYSCTRL) register selects which sleep mode is used
(see page 117). For more information about the behavior of the sleep modes, see “System
Control” on page 169.
This section describes the mechanisms for entering sleep mode and the conditions for waking up
from sleep mode, both of which apply to Sleep mode and Deep-sleep mode.
2.7.1 Entering Sleep Modes
This section describes the mechanisms software can use to put the processor into one of the sleep
modes.
The system can generate spurious wake-up events, for example a debug operation wakes up the
processor. Therefore, software must be able to put the processor back into sleep mode after such
an event. A program might have an idle loop to put the processor back to sleep mode.
2.7.1.1 Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode unless the wake-up
condition is true (see “Wake Up from WFI or Sleep-on-Exit” on page 77). When the processor
executes a WFI instruction, it stops executing instructions and enters sleep mode. See the
Cortex™-M3 Instruction Set Technical User's Manual for more information.
2.7.1.2 Wait for Event
The wait for event instruction, WFE, causes entry to sleep mode conditional on the value of a one-bit
event register. When the processor executes a WFE instruction, it checks the event register. If the
register is 0, the processor stops executing instructions and enters sleep mode. If the register is 1,
the processor clears the register and continues executing instructions without entering sleep mode.
If the event register is 1, the processor must not enter sleep mode on execution of a WFE instruction.
Typically, this situation occurs if an SEV instruction has been executed. Software cannot access
this register directly.
See the Cortex™-M3 Instruction Set Technical User's Manual for more information.
2.7.1.3 Sleep-on-Exit
If the SLEEPEXIT bit of SYSCTRL is set, when the processor completes the execution of an
exception handler, it returns to Thread mode and immediately enters sleep mode. This mechanism
can be used in applications that only require the processor to run when an exception occurs.
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2.7.2 Wake Up from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep
mode.
2.7.2.1 Wake Up from WFI or Sleep-on-Exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause
exception entry. Some embedded systems might have to execute system restore tasks after the
processor wakes up and before executing an interrupt handler. Entry to the interrupt handler can
be delayed by setting the PRIMASK bit and clearing the FAULTMASK bit. If an interrupt arrives that
is enabled and has a higher priority than current exception priority, the processor wakes up but does
not execute the interrupt handler until the processor clears PRIMASK. For more information about
PRIMASK and FAULTMASK, see page 54 and page 55.
2.7.2.2 Wake Up from WFE
The processor wakes up if it detects an exception with sufficient priority to cause exception entry.
In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers
an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to
cause exception entry. For more information about SYSCTRL, see page 117.
Stellaris® LM3S1110 Microcontroller
2.8 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 2-13 on page 77 lists the
supported instructions.
Note: In Table 2-13 on page 77:
■ Angle brackets, <>, enclose alternative forms of the operand
■ Braces, {}, enclose optional operands
■ The Operands column is not exhaustive
■ Op2 is a flexible second operand that can be either a register or a constant
■ Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the Cortex™-M3 Instruction Set Technical User's Manual.
Table 2-13. Cortex-M3 Instruction Summary
FlagsBrief DescriptionOperandsMnemonic
N,Z,C,VAdd with carry{Rd,} Rn , Op2ADC, ADCS
N,Z,C,VAdd{Rd,} Rn , Op2ADD, ADDS
N,Z,C,VAdd{Rd,} Rn , #imm12ADD, ADDW
-Load PC-relative addressRd , labelADR
N,Z,CLogical AND{Rd ,} Rn , Op2AND, ANDS
N,Z,CArithmetic shift rightRd , Rm , <Rs|#n>ASR, ASRS
-BranchlabelB
-Bit field clearRd , #lsb , #widthBFC
-Bit field insertRd , Rn , #lsb , #widthBFI
N,Z,CBit clear{Rd ,} Rn , Op2BIC, BICS
-Breakpoint#immBKPT
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Table 2-13. Cortex-M3 Instruction Summary (continued)
FlagsBrief DescriptionOperandsMnemonic
-Branch with linklabelBL
-Branch indirect with linkRmBLX
-Branch indirectRmBX
-Compare and branch if non-zeroRn , labelCBNZ
-Compare and branch if zeroRn , labelCBZ
-Clear exclusive-CLREX
-Count leading zerosRd , RmCLZ
N,Z,C,VCompare negativeRn , Op2CMN
N,Z,C,VCompareRn , Op2CMP
iflagsCPSID
interrupts
iflagsCPSIE
interrupts
Rn{!} , reglistLDMDB, LDMEA
before
Rd , spec_regMRS
register
spec_reg , R nMSR
register
-Change processor state, disable
-Change processor state, enable
-Data memory barrier-DMB
-Data synchronization barrier-DSB
N,Z,CExclusive OR{Rd ,} Rn , Op2EOR, EORS
-Instruction synchronization barrier-ISB
-If-Then condition block-IT
-Load multiple registers, increment afterRn{!} , reglistLDM
-Load multiple registers, decrement
-Load multiple registers, increment afterRn{!} , reglistLDMFD, LDMIA
-Load register with wordRt , [ Rn {, #offset}]LDR
-Load register with byteRt , [ Rn {, #offset}]LDRB, LDRBT
-Load register with two wordsRt , Rt2 , [ Rn {, #offset}]LDRD
-Load register exclusiveRt , [ Rn , #offset ]LDREX
-Load register exclusive with byteRt, [Rn]LDREXB
-Load register exclusive with halfwordRt , [Rn]LDREXH
-Load register with halfwordRt , [ Rn{ , #offset}]LDRH, LDRHT
-Load register with signed byteRt , [ Rn{ , #offset}]LDRSB, LDRSBT
-Load register with signed halfwordRt , [ Rn {, #offset}]LDRSH, LDRSHT
-Load register with wordRt , [ Rn {, #offset}]LDRT
N,Z,CLogical shift leftRd , Rm , <Rs|#n>LSL, LSLS
N,Z,CLogical shift rightRd , Rm , <Rs|#n>LSR, LSRS
-Multiply with accumulate, 32-bit resultRd , Rn , Rm, RaMLA
-Multiply and subtract, 32-bit resultRd , Rn , Rm, RaMLS
N,Z,CMoveRd , Op2MOV, MOVS
N,Z,CMove 16-bit constantRd , #imm16MOV, MOVW
-Move topRd , #imm16MOVT
-Move from special register to general
N,Z,C,VMove from general register to special
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Table 2-13. Cortex-M3 Instruction Summary (continued)
Rd , RnREVSH
and sign extend
RdLo, RdHi, Rn, RmSMLAL
(32x32+64), 64-bit result
Rn{!} , reglistSTMDB, STMEA
before
Stellaris® LM3S1110 Microcontroller
FlagsBrief DescriptionOperandsMnemonic
N,ZMultiply, 32-bit result{Rd,} Rn , RmMUL, MULS
N,Z,CMove NOTRd , Op2MVN, MVNS
-No operation-NOP
N,Z,CLogical OR NOT{Rd,} Rn , Op2ORN, ORNS
N,Z,CLogical OR{Rd,} Rn , Op2ORR, ORRS
-Pop registers from stackreglistPOP
-Push registers onto stackreglistPUSH
-Reverse bitsRd , RnRBIT
-Reverse byte order in a wordRd , RnREV
-Reverse byte order in each halfwordRd , RnREV16
-Reverse byte order in bottom halfword
N,Z,CRotate rightRd , Rm , <Rs|#n>ROR, RORS
N,Z,CRotate right with extendRd , RmRRX, RRXS
N,Z,C,VReverse subtract{Rd,} Rn , Op2RSB, RSBS
N,Z,C,VSubtract with carry{Rd,} Rn , Op2SBC, SBCS
-Signed bit field extractRd , Rn , #lsb , #widthSBFX
-Signed divide{Rd ,} Rn , RmSDIV
-Send event-SEV
-Signed multiply with accumulate
-Signed multiply (32x32), 64-bit resultRdLo, RdHi, Rn, RmSMULL
QSigned saturateRd, #n, Rm {,shift #s}SSAT
-Store multiple registers, increment afterRn{!} , reglistSTM
-Store multiple registers, decrement
-Store multiple registers, increment afterRn{!} , reglistSTMFD, STMIA
-Store register wordRt , [ Rn {, #offset}]STR
-Store register byteRt , [ Rn {, #offset}]STRB, STRBT
-Store register two wordsRt , Rt2 , [ Rn {, #offset}]STRD
-Store register exclusiveRd , Rt , [ Rn , #offset ]STREX
-Store register exclusive byteRd , Rt , [Rn]STREXB
-Store register exclusive halfwordRd , Rt , [Rn]STREXH
-Store register halfwordRt , [ Rn {, #offset}]STRH, STRHT
-Store register signed byteRt , [ Rn {, #offset}]STRSB, STRSBT
-Store register signed halfwordRt , [ Rn {, #offset}]STRSH, STRSHT
-Store register wordRt , [ Rn {, #offset}]STRT
N,Z,C,VSubtract{Rd,} Rn , Op2SUB, SUBS
N,Z,C,VSubtract 12-bit constant{Rd,} Rn , #imm12SUB, SUBW
-Supervisor call#immSVC
-Sign extend a byte{Rd,} Rm {,ROR #n}SXTB
-Sign extend a halfword{Rd,} Rm {,ROR #n}SXTH
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Table 2-13. Cortex-M3 Instruction Summary (continued)
FlagsBrief DescriptionOperandsMnemonic
-Table branch byte[Rn, Rm]TBB
-Table branch halfword[Rn, Rm, LSL #1]TBH
N,Z,CTest equivalenceRn, Op2TEQ
N,Z,CTestRn, Op2TST
-Unsigned bit field extractRd , Rn , #lsb , #widthUBFX
-Unsigned divide{Rd,} Rn , RmUDIV
RdLo, RdHi, Rn, RmUMLAL
(32x32+64), 64-bit result
-Unsigned multiply with accumulate
-Unsigned multiply (32x 2), 64-bit resultRdLo, RdHi, Rn, RmUMULL
QUnsigned saturateRd, #n, Rm {,shift #s}USAT
-Zero extend a byte{Rd,} Rm {,ROR #n}UXTB
-Zero extend a halfword{Rd,} Rm {,ROR #n}UXTH
-Wait for event-WFE
-Wait for interrupt-WFI
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3 Cortex-M3 Peripherals
This chapter provides information on the Stellaris®implementation of the Cortex-M3 processor
peripherals, including:
■ SysTick (see 81)
Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible
control mechanism.
■ Nested Vectored Interrupt Controller (NVIC)
– Facilitates low-latency exception and interrupt handling
– Controls power management
– Implements system control registers
■ System Control Block (SCB) (see 82)
Provides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
■ Memory Protection Unit (MPU) (see 84)
Stellaris® LM3S1110 Microcontroller
Supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU
provides full support for protection regions, overlapping protection regions, access permissions,
and exporting memory attributes to the system.
Table 3-1 on page 81 shows the address map of the Private Peripheral Bus (PPB). Some peripheral
register regions are split into two address regions, as indicated by two addresses listed.
Table 3-1. Core Peripheral Register Regions
0xE000.EF00-0xE000.EF03
3.1 Functional Description
This chapter provides information on the Stellaris®implementation of the Cortex-M3 processor
peripherals: SysTick, NVIC, SCB and MPU.
3.1.1 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example as:
DescriptionCore PeripheralAddress
81System Timer0xE000.E010-0xE000.E01F
82Nested Vectored Interrupt Controller0xE000.E100-0xE000.E4EF
84System Control Block0xE000.ED00-0xE000.ED3F
84Memory Protection Unit0xE000.ED90-0xE000.EDB8
■ An RTOS tick timer that fires at a programmable rate (for example, 100 Hz) and invokes a SysTick
routine.
■ A high-speed alarm timer using the system clock.
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Cortex-M3 Peripherals
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter used to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNT bit in the
STCTRL control and status register can be used to determine if an action completed within a
set duration, as part of a dynamic clock management control loop.
The timer consists of three registers:
■ SysTick Control and Status (STCTRL): A control and status counter to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.
■ SysTick Reload Value (STRELOAD): The reload value for the counter, used to provide the
counter's wrap value.
■ SysTick Current Value (STCURRENT): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps)
to the value in the STRELOAD register on the next clock edge, then decrements on subsequent
clocks. Clearing the STRELOAD register disables the counter on the next wrap. When the counter
reaches zero, the COUNT status bit is set. The COUNT bit clears on reads.
Writing to the STCURRENT register clears the register and the COUNT status bit. The write does
not trigger the SysTick exception logic. On a read, the current value is the value of the register at
the time the register is accessed.
The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode,
the SysTick counter stops. Ensure software uses aligned word accesses to access the SysTick
registers.
Note: When the processor is halted for debugging, the counter does not decrement.
3.1.2 Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses.
The NVIC supports:
■ 23 interrupts.
■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower
priority, so level 0 is the highest interrupt priority.
■ Low-latency exception and interrupt handling.
■ Level and pulse detection of interrupt signals.
■ Dynamic reprioritization of interrupts.
■ Grouping of priority values into group priority and subpriority fields.
■ Interrupt tail-chaining.
■ An external Non-maskable interrupt (NMI).
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The processor automatically stacks its state on exception entry and unstacks this state on exception
exit, with no instruction overhead, providing low latency exception handling.
3.1.2.1 Level-Sensitive and Pulse Interrupts
The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described
as edge-triggered interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically
this happens because the ISR accesses the peripheral, causing it to clear the interrupt request. A
pulse interrupt is an interrupt signal sampled synchronously on the rising edge of the processor
clock. To ensure the NVIC detects the interrupt, the peripheral must assert the interrupt signal for
at least one clock cycle, during which the NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the interrupt
(see “Hardware and Software Control of Interrupts” on page 83 for more information). For a
level-sensitive interrupt, if the signal is not deasserted before the processor returns from the ISR,
the interrupt becomes pending again, and the processor must execute its ISR again. As a result,
the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
3.1.2.2 Hardware and Software Control of Interrupts
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following
reasons:
Stellaris® LM3S1110 Microcontroller
■ The NVIC detects that the interrupt signal is High and the interrupt is not active.
■ The NVIC detects a rising edge on the interrupt signal.
■ Software writes to the corresponding interrupt set-pending register bit, or to the Software Trigger
Interrupt (SWTRIG) register to make a Software-Generated Interrupt pending. See the INT bit
in the PEND0 register on page 100 or SWTRIG on page 108.
A pending interrupt remains pending until one of the following:
■ The processor enters the ISR for the interrupt, changing the state of the interrupt from pending
to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples
the interrupt signal. If the signal is asserted, the state of the interrupt changes to pending,
which might cause the processor to immediately re-enter the ISR. Otherwise, the state of the
interrupt changes to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed
the state of the interrupt changes to pending and active. In this case, when the processor
returns from the ISR the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the processor
returns from the ISR the state of the interrupt changes to inactive.
■ Software writes to the corresponding interrupt clear-pending register bit
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt
does not change. Otherwise, the state of the interrupt changes to inactive.
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– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending
or to active, if the state was active and pending.
3.1.3 System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
3.1.4 Memory Protection Unit (MPU)
This section describes the Memory protection unit (MPU). The MPU divides the memory map into
a number of regions and defines the location, size, access permissions, and memory attributes of
each region. The MPU supports independent attribute settings for each region, overlapping regions,
and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU
defines eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any
region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses
have the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates
a memory management fault, causing a fault exception and possibly causing termination of the
process in an OS environment. In an OS environment, the kernel can update the MPU region setting
dynamically based on the process to be executed. Typically, an embedded OS uses the MPU for
memory protection.
Configuration of MPU regions is based on memory types (see “Memory Regions, Types and
Attributes” on page 59 for more information).
Table 3-2 on page 84 shows the possible MPU region attributes. See the section called “MPU
Configuration for a Stellaris®Microcontroller” on page 88 for guidelines for programming a
microcontroller implementation.
Table 3-2. Memory Attributes Summary
DescriptionMemory Type
All accesses to Strongly Ordered memory occur in program order.Strongly Ordered
Memory-mapped peripheralsDevice
Normal memoryNormal
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that
the interrupt handlers might access.
Ensure software uses aligned accesses of the correct size to access MPU registers:
■ Except for the MPU Region Attribute and Size (MPUATTR) register, all MPU registers must
be accessed with aligned word accesses.
■ The MPUATTR register can be accessed with byte or aligned halfword or word accesses.
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The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions
to prevent any previous region settings from affecting the new MPU setup.
3.1.4.1 Updating an MPU Region
To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU
Region Base Address (MPUBASE) and MPUATTR registers must be updated. Each register can
be programmed separately or with a multiple-word write to program all of these registers. You can
use the MPUBASEx and MPUATTRx aliases to program up to four regions simultaneously using
an STM instruction.
Updating an MPU Region Using Separate Words
This example simple code configures one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address
STRH R2, [R0, #0x8] ; Region Size and Enable
STRH R3, [R0, #0xA] ; Region Attribute
Stellaris® LM3S1110 Microcontroller
Disable a region before writing new region settings to the MPU if you have previously enabled the
region being changed. For example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable
STR R4, [R0, #0x4] ; Region Base Address
STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
STRH R2, [R0, #0x8] ; Region Size and Enable
Software must use memory barrier instructions:
■ Before MPU setup, if there might be outstanding memory transfers, such as buffered writes, that
might be affected by the change in MPU settings.
■ After MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering
an exception handler, or is followed by an exception return, because the exception entry and
exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it accesses
the MPU through the Private Peripheral Bus (PPB), which is a Strongly Ordered memory region.
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For example, if all of the memory access behavior is intended to take effect immediately after the
programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is
required after changing MPU settings, such as at the end of context switch. An ISB is required if
the code that programs the MPU region or regions is entered using a branch or call. If the
programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.
Updating an MPU Region Using Multi-Word Writes
The MPU can be programmed directly using multi-word writes, depending how the information is
divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
An STM instruction can be used to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPUNUMBER ; 0xE000ED98, MPU region number register
STM R0, {R1-R3} ; Region number, address, attribute, size and enable
This operation can be done in two words for pre-packed information, meaning that the MPU Region
Base Address (MPUBASE) register (see page 142) contains the required region number and has
the VALID bit set. This method can be used when the data is statically packed, for example in a
boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPUBASE ; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and region number combined
; with VALID (bit 4) set
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
An STM instruction can be used to optimize this:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0,=MPUBASE ; 0xE000ED9C, MPU Region Base register
STM R0, {R1-R2} ; Region base address, region number and VALID bit,
; and Region Attribute, Size and Enable
Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding
bit in the SRD field of the MPU Region Attribute and Size (MPUATTR) register (see page 144) to
disable a subregion. The least-significant bit of the SRD field controls the first subregion, and the
most-significant bit controls the last subregion. Disabling a subregion means another region
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Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
Base address of both regions
Offset from
base address
0
64KB
128KB
192KB
256KB
320KB
384KB
448KB
512KB
Stellaris® LM3S1110 Microcontroller
overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD
field must be configured to 0x00, otherwise the MPU behavior is unpredictable.
Example of SRD Use
Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB.
To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for
region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 87 shows.
Figure 3-1. SRD Use Example
3.1.4.2 MPU Access Permission Attributes
The access permission bits, TEX, S, C, B, AP, and XN of the MPUATTR register, control access to
the corresponding memory region. If an access is made to an area of memory without the required
permissions, then the MPU generates a permission fault.
Table 3-3 on page 87 shows the encodings for the TEX, C, B, and S access permission bits. All
encodings are shown for completeness, however the current implementation of the Cortex-M3 does
not support the concept of cacheability or shareability. Refer to the section called “MPU Configuration
for a Stellaris®Microcontroller” on page 88 for information on programming the MPU for Stellaris
®
implementations.
Table 3-3. TEX, S, C, and B Bit Field Encoding
Other AttributesShareabilityMemory TypeBCSTEX
000b
000
001
001
a
a
a
a
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Not shareableNormal010000
ShareableNormal011000
Not shareableNormal110000
ShareableNormal111000
Not shareableNormal000001
ShareableNormal001001
Not shareableNormal110001
ShareableNormal111001
-ShareableStrongly Ordered00x
-ShareableDevice10x
Outer and inner
write-through. No write
allocate.
Outer and inner
noncacheable.
--Reserved encoding10x
--Reserved encoding01x
Outer and inner
write-back. Write and
read allocate.
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Table 3-3. TEX, S, C, and B Bit Field Encoding (continued)
010
010
010
a. The MPU ignores the value of this bit.
Table 3-4 on page 88 shows the cache policy for memory attribute encodings with a TEX value in
the range of 0x4-0x7.
Table 3-4. Cache Policy for Memory Attribute Encoding
Other AttributesShareabilityMemory TypeBCSTEX
a
a
a
1x
a
Not shareableNormalAA01BB
ShareableNormalAA11BB
Corresponding Cache PolicyEncoding, AA or BB
Non-cacheable00
Write back, write and read allocate01
Write through, no write allocate10
Write back, no write allocate11
Nonshared Device.Not shareableDevice00x
--Reserved encoding10x
--Reserved encodingx
Cached memory (BB =
outer policy, AA = inner
policy).
See Table 3-4 for the
encoding of the AA and
BB bits.
Table 3-5 on page 88 shows the AP encodings in the MPUATTR register that define the access
permissions for privileged and unprivileged software.
Table 3-5. AP Bit Field Encoding
AP Bit Field
Privileged
Permissions
Permissions
ROR/W010
DescriptionUnprivileged
All accesses generate a permission fault.No accessNo access000
Access from privileged software only.No accessR/W001
Writes by unprivileged software generate a
permission fault.
Full access.R/WR/W011
Reserved.UnpredictableUnpredictable100
Reads by privileged software only.No accessRO101
Read-only, by privileged or unprivileged software.RORO110
Read-only, by privileged or unprivileged software.RORO111
MPU Configuration for a Stellaris®Microcontroller
Stellaris®microcontrollers have only a single processor and no caches. As a result, the MPU should
be programmed as shown in Table 3-6 on page 88.
Table 3-6. Memory Region Attributes for Stellaris®Microcontrollers
Memory Type and AttributesBCSTEXMemory Region
Normal memory, non-shareable, write-through010000bFlash memory
Normal memory, shareable, write-through011000bInternal SRAM
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Table 3-6. Memory Region Attributes for Stellaris®Microcontrollers (continued)
In current Stellaris®microcontroller implementations, the shareability and cache policy attributes do
not affect the system behavior. However, using these settings for the MPU regions can make the
application code more portable. The values given are for typical situations.
3.1.4.3 MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management
fault (see “Exceptions and Interrupts” on page 58 for more information). The MFAULTSTAT register
indicates the cause of the fault. See page 128 for more information.
3.2 Register Map
Table 3-7 on page 89 lists the Cortex-M3 Peripheral SysTick, NVIC, SCB and MPU registers. The
offset listed is a hexadecimal increment to the register's address, relative to the Core Peripherals
base address of 0xE000.E000.
Stellaris® LM3S1110 Microcontroller
Memory Type and AttributesBCSTEXMemory Region
111000bExternal SRAM
Normal memory, shareable, write-back,
write-allocate
Device memory, shareable101000bPeripherals
Note: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-7. Peripherals Register Map
System Timer (SysTick) Registers
Nested Vectored Interrupt Controller (NVIC) Registers
DescriptionResetTypeNameOffset
See
page
92SysTick Control and Status Register0x0000.0000R/WSTCTRL0x010
94SysTick Reload Value Register0x0000.0000R/WSTRELOAD0x014
95SysTick Current Value Register0x0000.0000R/WCSTCURRENT0x018
96Interrupt 0-31 Set Enable0x0000.0000R/WEN00x100
97Interrupt 32-43 Set Enable0x0000.0000R/WEN10x104
98Interrupt 0-31 Clear Enable0x0000.0000R/WDIS00x180
99Interrupt 32-43 Clear Enable0x0000.0000R/WDIS10x184
100Interrupt 0-31 Set Pending0x0000.0000R/WPEND00x200
101Interrupt 32-43 Set Pending0x0000.0000R/WPEND10x204
102Interrupt 0-31 Clear Pending0x0000.0000R/WUNPEND00x280
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103Interrupt 32-43 Clear Pending0x0000.0000R/WUNPEND10x284
104Interrupt 0-31 Active Bit0x0000.0000ROACTIVE00x300
105Interrupt 32-43 Active Bit0x0000.0000ROACTIVE10x304
106Interrupt 0-3 Priority0x0000.0000R/WPRI00x400
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Table 3-7. Peripherals Register Map (continued)
System Control Block (SCB) Registers
DescriptionResetTypeNameOffset
See
page
106Interrupt 4-7 Priority0x0000.0000R/WPRI10x404
106Interrupt 8-11 Priority0x0000.0000R/WPRI20x408
106Interrupt 12-15 Priority0x0000.0000R/WPRI30x40C
106Interrupt 16-19 Priority0x0000.0000R/WPRI40x410
106Interrupt 20-23 Priority0x0000.0000R/WPRI50x414
106Interrupt 24-27 Priority0x0000.0000R/WPRI60x418
106Interrupt 28-31 Priority0x0000.0000R/WPRI70x41C
106Interrupt 32-35 Priority0x0000.0000R/WPRI80x420
106Interrupt 36-39 Priority0x0000.0000R/WPRI90x424
106Interrupt 40-43 Priority0x0000.0000R/WPRI100x428
108Software Trigger Interrupt0x0000.0000WOSWTRIG0xF00
109CPU ID Base0x411F.C231ROCPUID0xD00
110Interrupt Control and State0x0000.0000R/WINTCTRL0xD04
114Vector Table Offset0x0000.0000R/WVTABLE0xD08
Memory Protection Unit (MPU) Registers
115Application Interrupt and Reset Control0xFA05.0000R/WAPINT0xD0C
117System Control0x0000.0000R/WSYSCTRL0xD10
119Configuration and Control0x0000.0000R/WCFGCTRL0xD14
121System Handler Priority 10x0000.0000R/WSYSPRI10xD18
122System Handler Priority 20x0000.0000R/WSYSPRI20xD1C
123System Handler Priority 30x0000.0000R/WSYSPRI30xD20
124System Handler Control and State0x0000.0000R/WSYSHNDCTRL0xD24
128Configurable Fault Status0x0000.0000R/W1CFAULTSTAT0xD28
134Hard Fault Status0x0000.0000R/W1CHFAULTSTAT0xD2C
136Memory Management Fault Address-R/WMMADDR0xD34
137Bus Fault Address-R/WFAULTADDR0xD38
138MPU Type0x0000.0800ROMPUTYPE0xD90
139MPU Control0x0000.0000R/WMPUCTRL0xD94
141MPU Region Number0x0000.0000R/WMPUNUMBER0xD98
142MPU Region Base Address0x0000.0000R/WMPUBASE0xD9C
144MPU Region Attribute and Size0x0000.0000R/WMPUATTR0xDA0
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Table 3-7. Peripherals Register Map (continued)
Stellaris® LM3S1110 Microcontroller
DescriptionResetTypeNameOffset
3.3 System Timer (SysTick) Register Descriptions
This section lists and describes the System Timer registers, in numerical order by address offset.
See
page
142MPU Region Base Address Alias 10x0000.0000R/WMPUBASE10xDA4
144MPU Region Attribute and Size Alias 10x0000.0000R/WMPUATTR10xDA8
142MPU Region Base Address Alias 20x0000.0000R/WMPUBASE20xDAC
144MPU Region Attribute and Size Alias 20x0000.0000R/WMPUATTR20xDB0
142MPU Region Base Address Alias 30x0000.0000R/WMPUBASE30xDB4
144MPU Region Attribute and Size Alias 30x0000.0000R/WMPUATTR30xDB8
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Register 1: SysTick Control and Status Register (STCTRL), offset 0x010
Note: This register can only be accessed from privileged mode.
The SysTick STCTRL register enables the SysTick features.
SysTick Control and Status Register (STCTRL)
Base 0xE000.E000
Offset 0x010
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
COUNTreserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
ENABLEINTENCLK_SRCreserved
R/WR/WR/WROROROROROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
0x000ROreserved31:17
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROCOUNT16
Count Flag
DescriptionValue
0
The SysTick timer has not counted to 0 since the last time
this bit was read.
1
The SysTick timer has counted to 0 since the last time
this bit was read.
This bit is cleared by a read of the register or if the STCURRENT register
is written with any value.
If read by the debugger using the DAP, this bit is cleared only if the
MasterType bit in the AHB-AP Control Register is clear. Otherwise,
the COUNT bit is not changed by the debugger read. See the ARM®
Debug Interface V5 Architecture Specification for more information on
MasterType.
0x000ROreserved15:3
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0R/WCLK_SRC2
Clock Source
DescriptionValue
External reference clock. (Not implemented for Stellaris
0
®
microcontrollers.)
System clock1
Because an external reference clock is not implemented, this bit must
be set in order for SysTick to operate.
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DescriptionResetTypeNameBit/Field
0R/WINTEN1
0R/WENABLE0
Interrupt Enable
DescriptionValue
0
1
Enable
1
Interrupt generation is disabled. Software can use the
COUNT bit to determine if the counter has ever reached 0.
An interrupt is generated to the NVIC when SysTick counts
to 0.
DescriptionValue
The counter is disabled.0
Enables SysTick to operate in a multi-shot way. That is, the
counter loads the RELOAD value and begins counting down.
On reaching 0, the COUNT bit is set and an interrupt is
generated if enabled by INTEN. The counter then loads the
RELOAD value again and begins counting.
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Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014
Note: This register can only be accessed from privileged mode.
Note: This register can only be accessed from privileged mode.
The STRELOAD register specifies the start value to load into the SysTick Current Value
(STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and
0x00FF.FFFF. A start value of 0 is possible but has no effect because the SysTick interrupt and the
COUNT bit are activated when counting from 1 to 0.
SysTick can be configured as a multi-shot timer, repeated over and over, firing every N+1 clock
pulses, where N is any value from 1 to 0x00FF.FFFF. For example, if a tick interrupt is required
every 100 clock pulses, 99 must be written into the RELOAD field.
SysTick Reload Value Register (STRELOAD)
Base 0xE000.E000
Offset 0x014
Type R/W, reset 0x0000.0000
RELOAD
16171819202122232425262728293031
RELOADreserved
R/WR/WR/WR/WR/WR/WR/WR/WROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
0x00ROreserved31:24
0x00.0000R/WRELOAD23:0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Reload Value
Value to load into the SysTick Current Value (STCURRENT) register
when the counter reaches 0.
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Register 3: SysTick Current Value Register (STCURRENT), offset 0x018
Note: This register can only be accessed from privileged mode.
The STCURRENT register contains the current value of the SysTick counter.
SysTick Current Value Register (STCURRENT)
Base 0xE000.E000
Offset 0x018
Type R/WC, reset 0x0000.0000
CURRENT
DescriptionResetTypeNameBit/Field
Stellaris® LM3S1110 Microcontroller
16171819202122232425262728293031
CURRENTreserved
R/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCR/WCType
0000000000000000Reset
0x00ROreserved31:24
0x00.0000R/WCCURRENT23:0
3.4 NVIC Register Descriptions
This section lists and describes the NVIC registers, in numerical order by address offset.
The NVIC registers can only be fully accessed from privileged mode, but interrupts can be pended
while in unprivileged mode by enabling the Configuration and Control (CFGCTRL) register. Any
other unprivileged mode access causes a bus fault.
Ensure software uses correctly aligned register accesses. The processor does not support unaligned
accesses to NVIC registers.
An interrupt can enter the pending state even if it is disabled.
Before programming the VTABLE register to relocate the vector table, ensure the vector table
entries of the new vector table are set up for fault handlers, NMI, and all enabled exceptions such
as interrupts. For more information, see page 114.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Current Value
This field contains the current value at the time the register is accessed.
No read-modify-write protection is provided, so change with care.
This register is write-clear. Writing to it with any value clears the register.
Clearing this register also clears the COUNT bit of the STCTRL register.
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Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100
Note: This register can only be accessed from privileged mode.
The EN0 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 69 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 0-31 Set Enable (EN0)
Base 0xE000.E000
Offset 0x100
Type R/W, reset 0x0000.0000
INT
INT
16171819202122232425262728293031
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
0x0000.0000R/WINT31:0
Interrupt Enable
DescriptionValue
0
1
A bit can only be cleared by setting the corresponding INT[n] bit in
the DIS0 register.
On a read, indicates the interrupt is disabled.
On a write, no effect.
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
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Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104
Note: This register can only be accessed from privileged mode.
The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to
Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 69 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 32-43 Set Enable (EN1)
Base 0xE000.E000
Offset 0x104
Type R/W, reset 0x0000.0000
reserved
Stellaris® LM3S1110 Microcontroller
INTreserved
16171819202122232425262728293031
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
0x0000.0ROreserved31:12
0x000R/WINT11:0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt Enable
DescriptionValue
0
1
A bit can only be cleared by setting the corresponding INT[n] bit in
the DIS1 register.
On a read, indicates the interrupt is disabled.
On a write, no effect.
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
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Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180
Note: This register can only be accessed from privileged mode.
The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt
31. See Table 2-9 on page 69 for interrupt assignments.
Interrupt 0-31 Clear Enable (DIS0)
Base 0xE000.E000
Offset 0x180
Type R/W, reset 0x0000.0000
16171819202122232425262728293031
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
INT
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
0x0000.0000R/WINT31:0
Interrupt Disable
DescriptionValue
On a read, indicates the interrupt is disabled.
0
On a write, no effect.
On a read, indicates the interrupt is enabled.
1
On a write, clears the corresponding INT[n] bit in the EN0
register, disabling interrupt [n].
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Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184
Note: This register can only be accessed from privileged mode.
The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt
43. See Table 2-9 on page 69 for interrupt assignments.
Interrupt 32-43 Clear Enable (DIS1)
Base 0xE000.E000
Offset 0x184
Type R/W, reset 0x0000.0000
reserved
DescriptionResetTypeNameBit/Field
Stellaris® LM3S1110 Microcontroller
INTreserved
16171819202122232425262728293031
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WROROROROType
0000000000000000Reset
0x0000.0ROreserved31:12
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x000R/WINT11:0
Interrupt Disable
DescriptionValue
On a read, indicates the interrupt is disabled.
0
On a write, no effect.
On a read, indicates the interrupt is enabled.
1
On a write, clears the corresponding INT[n] bit in the EN1
register, disabling interrupt [n].
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Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200
Note: This register can only be accessed from privileged mode.
The PEND0 register forces interrupts into the pending state and shows which interrupts are pending.
Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 69 for
interrupt assignments.
Interrupt 0-31 Set Pending (PEND0)
Base 0xE000.E000
Offset 0x200
Type R/W, reset 0x0000.0000
INT
INT
16171819202122232425262728293031
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
0123456789101112131415
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
0x0000.0000R/WINT31:0
Interrupt Set Pending
DescriptionValue
0
On a read, indicates that the interrupt is not pending.
On a write, no effect.
1
On a read, indicates that the interrupt is pending.
On a write, the corresponding interrupt is set to pending
even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no
effect.
A bit can only be cleared by setting the corresponding INT[n] bit in
the UNPEND0 register.
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