TEXAS INSTRUMENTS SRC4382EVM-PDK, SRC4392EVM-PDK Technical data

SRC4382EVM-PDK and SRC4392EVM-PDK User's Guide

This user’s guide provides a reference document for the SRC4382EVM-PDK and SRC4392EVM-PDK product development kits. The kits include either an SRC4382EVM or an SRC4392EVM daughterboard, as well as a DAIMB motherboard. Together, the daughter and mother boards form a modular platform for evaluating the function and performance of the Texas Instruments’ SRC4382 and SRC4392 integrated circuits. Applications software is provided with the PDK for writing and reading registers and data buffers integral to the SRC4382 and SRC4392 devices. The software communicates with the device under test using the USB slave interface on the DAIMB board. The software requires a host PC running the Microsoft Windows™ 2000 or XP operating system.

Throughout this document, the acronym EVM and the phrase evaluation module are synonymous with the SRC4382EVM and SRC4392EVM. The acronym PDK refers to the daughterboard EVM and DAIMB motherboard combination. This document includes information regarding absolute operating conditions, hardware configuration, and software installation and operation. Complete electrical schematics and a bill of materials for both the EVM and the DAIMB boards are also included.

User's Guide

SBOU038 – April 2006

1 Introduction .......................................................................................... 2

2 Quick Start ........................................................................................... 3

3 Software Overview, Installation, and Operation ................................................ 9

4 Hardware Reference .............................................................................. 14

1 Illustration of the PDK Platform Utilizing a DAIMB Motherboard and a

Daughterboard EVM ............................................................................... 2

2 Power-Supply Jumper Configuration (DAIMB Motherboard) ................................. 5

3 PDK Power, Host, and Input/Output Connections ............................................. 8

4 Applications Software Window (USB Serial Commander) ................................... 10

5 Example of a Readback Display and Break Message in the USB Serial Commander

Application ......................................................................................... 12

6 Electrical Schematic: SRC4382/92EVM Daughterboard ..................................... 15

7 Electrical Schematic: DAIMB Motherboard, Page 1 .......................................... 16

8 Electrical Schematic: DAIMB Motherboard, Page 2 .......................................... 17

1 Absolute Operating Conditions ................................................................... 4

2 Jumper JMP3 Configuration (EVM Daughterboard) ........................................... 5

3 Jumper JMP4 Configuration (EVM Daughterboard) ........................................... 5

4 Jumper JMP5 Configuration (EVM Daughterboard) ........................................... 5

5 Jumper JMP1, RX4 Input Selection (EVM Daughterboard) ................................... 6

6 Audio Serial Port Slave/Master Switch Configuration (DAIMB Motherboard) .............. 6

I2C, I2S are trademarks of Koninklijke Philips Electronics N.V. Windows is a trademark of Microsoft Corporation. SPI is a trademark of Motorola, Inc. NI-VISA is a trademark of National Instruments. WinZip is a trademark of WinZip International, LLC. All trademarks are the property of their respective owners.

Contents

List of Figures

List of Tables

SBOU038 – April 2006 SRC4382EVM-PDK and SRC4392EVM-PDK User's Guide 1

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PORT C

PORT D

TX1

110W

Power

Adapter

+5V VIO EXT SPI EXT I C and DIO2USB

PORT A

PORT B

RX1

110W

RX1

75W

RX2

75W

RX3

75W

RX4

75W

OPTICALINLOGICINEXT

MCLK1

EXT

MCLK2

LOGIC

OUT

OPTICAL

OUT

TX1

75W

TX2

TX3

75W

TX4

75W

DAIMB

(Motherboard)

EVM

(Daughterboard)

J10

J17

J18

J12

J13

J14

J15

J11

J16

U13

J19

J20

J21 J22

J23

J24

JA JB

HOST I/O

PORTS A and B

PORTS

C and D

DAI IN

DAI

OUT

POWER

Introduction

7 USB SPI PortConfiguration (DAIMB Motherboard) ............................................ 6

8 MCLK1 Clock Source Selection (DAIMB Daughterboard) .................................... 7

9 MCLK2 Clock Source Selection (DAIMB Daughterboard) .................................... 7

10 SRC Output Mute Configuration (EVM Daughterboard) ....................................... 7

11 SRC4382/4392 Control Port Mode Configuration (EVM Daughterboard) ................... 7

12 I

C 7-Bit Slave Address Configuration (EVM Daughterboard) ................................ 8

13 SPI Command Syntax ............................................................................ 12

14 I

C Command Syntax ............................................................................. 13

15 Bill of Materials for the SRC4382/92EVM ..................................................... 18

16 Bill of Materials for the DAIMB .................................................................. 19

1 Introduction

The SRC4382EVM-PDK and the SRC4392EVM-PDK provide a modular solution for evaluating the function and performance of the SRC4382 and SRC4392 devices from Texas Instruments. The PDK includes a motherboard (the DAIMB) and a daughterboard (the EVM). Figure 1 depicts the modular platform concept, with the EVM plugged into the DAIMB board. Connectors are indicated and labeled for ease of identification.

Figure 1. Illustration of the PDK Platform Utilizing a DAIMB Motherboard and a Daughterboard EVM

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Quick Start

The modular design allows for common functions to be integrated onto the DAIMB motherboard, while device-specific functions are integrated onto the daughterboard EVM. The modular platform supports a variety of digital audio interface devices by simply replacing the daughterboard EVM shipped with the product specific PDK. Texas Instruments products supported by this modular platform include digital audio interface receivers, transmitters, transceivers, and combination SRC/transceiver products.

The primary features of the SRC4382EVM-PDK and SRC4392EVM-PDK include:

• A USB slave interface, implemented with a Texas Instruments TAS1020B USB controller, and supported by computers running Microsoft Windows 2000 or XP. The USB interface supports bus or self-powered operation, and communicates with the EVM daugther board via an SPI™ or I2C™ interface.

• Buffered headers support up to four audio serial port interfaces, compatible with I2S™-style or time-division multiplexed (TDM) data formats. Only two of these ports are utilized for the SRC4382EVM and SRC4392EVM.

• Six digital audio input ports support AES3 balanced inputs, S/PDIF coaxial and optical sources, and CMOS logic level inputs.

• Six digital audio output ports support AES3 balanced, S/PDIF coaxial and optical, and CMOS logic level outputs. Three of the ports are utilized for the SRC4382EVM and SRC4392EVM.

• Flexible reference and master clock generation are supported, using either onboard oscillators or external clock sources.

• Power may be provided from a wall adapter (included), or an external +5V regulated power supply. An optional external logic I/O (or VIO) supply connection is also supported.

• Onboard linear regulators derive +1.8V, +3.3V, and +5V power supplies from the supplied power adapter, external supplies, and/or the USB bus connection.

• LED indicators are provided for DIR Lock and SRC Ready output flags.

• Applications software provides functions for writing and reading the on-chip registers and data buffers.

The applications software is compatible with personal computers with at least one USB 1.x or 2.0 port running the Microsoft Windows 2000 or XP operating systems.

2 Quick Start

This section provides information regarding handling, package contents, and the absolute operating conditions for the SRC4392/82EVM.

2.1 Electrostatic Discharge Warning

Failure to observe proper ESD handling precautions may result in damage to EVM components.

Many of the components used in the assembly of the PDK are susceptible to damage by electrostatic discharge (ESD). Customers are advised to observe proper ESD handling procedure when unpacking and handling the PDK components. All handling should be performed at an approved ESD workstation or test bench, using a grounded wrist strap. Failure to observe proper handling procedure may result in damage to EVM components.

WARNING

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Quick Start

2.2 Product Development Kit (PDK) Package Contents

Either the SRC4382EVM or SRC4392EVM is included as part of a complete evaluation module package, referred to as a Product Development Kit, or PDK. Each PDK package includes:

• One SRC4382EVM or SRC4392EVM board, depending upon the PDK ordered.

• One DAIMB board.

• One printed copy of this SRC4382EVM-PDK and SRC4392EVM-PDK User’s Guide.

• One printed copy of the SRC4382 or SRC4392 datasheet, depending upon the PDK ordered.

• One power supply for powering the PDK.

• One USB cable (Type A to Type B male plugs).

• One CD-ROM containing the EVM applications software, support files, and documentation.

2.3 Absolute Operating Conditions

Exceeding the absolute operating conditions may result in improper EVM operation or damage to the evaluation module and/or the equipment connected to it.

The user should be aware of the absolute operating conditions for the PDK. Table 1 summarizes these conditions.

CAUTION

Table 1. Absolute Operating Conditions

Min Max Units

Power Supplies

Power Adapter (J19) +6.0 +10.0 VDC EXT +5V (J20) –0.3 +5.5 VDC EXT VIO –0.3 +3.6 VDC

Digital Input Voltage Range

daughterboard Connectors (JA–JD,JF) –0.3 +3.6 V PORT A through PORT D (J1–J4) –0.3 +3.6 V EXT SPI and EXT I2C & DIO (J22 and J23) –0.3 +3.6 V RX1 Balanced Input (J5), measured differentially — 7.2 V RX1 Unbalanced Input (J6) — 3.6 V RX2 through RX4 (J7–J9) — 3.6 V EXT MCLK1 and EXT MCLK2 (J17 and J18) –0.3 +3.6 V LOGIC INPUT (J10) –0.3 +5.5 V PDK Operating Temperature 0 +70 ° C

PP PP PP

2.4 Jumper Configuration

This sub-section provides an overview of the required jumper configuration for both the DAIMB motherboard and EVM daughterboard. Refer to the electrical schematics included in Section 4 of this document for connection details, as well as jumper functions that may not be discussed in this section.

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External +5V (J20)

Power Adapter (U17)

JMP1

EXT

+5V

ADAPTER

External VIO (J21)

+1.8V (U18)

JMP2

VIO

+3.3V (U19)

+5V (selected by JMP1)

+5V from USB Port (J24)

JMP3

SELF

To Input

of U20

BUS

2.4.1 Power Supply Jumpers

Power-supply configuration for the PDK is set up using jumpers JMP1 through JMP3, located on the DAIMB motherboard. Figure 2 illustrates the options for each of these jumpers.

By default, jumper JMP1 is configured for Power Adapter input at J19, jumper JMP2 is set up for a +3.3V logic I/O (or VIO) supply, and jumper JMP3 is set up for Bus power operation (+5V from connector J24). The +3.3V logic I/O supply is required in this case to maintain logic level compatibility with the USB slave interface circuitry.

Jumpers JMP6 through JMP9 on the EVM daughterboard are provided for measuring power-supply current. By default, these jumpers are shorted with bus wire, soldered during assembly of the board.

Quick Start

Figure 2. Power-Supply Jumper Configuration (DAIMB Motherboard)

2.4.2 SPI and I2C Jumpers

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Jumpers JMP3 through JMP5, located on the EVM daughterboard, are utilized to select SPI or I2C host interface connections for the SRC4382EVM or SRC4392EVM. Refer to Table 2 through Table 4 for jumper configuration.

Table 2. Jumper JMP3 Configuration (EVM Daughterboard)

JMP3 Pins 1–2 JMP3 Pins 3–4 Host Interface Selection

OPEN SHORT SPI

SHORT OPEN I2C

Table 3. Jumper JMP4 Configuration (EVM Daughterboard)

JMP4 Pins 1–2 JMP4 Pins 3–4 Host Interface Selection

OPEN SHORT SPI

SHORT OPEN I2C

Table 4. Jumper JMP5 Configuration (EVM Daughterboard)

JMP5 Pins 1-2 JMP5 Pins 3-4 Host Interface Selection

OPEN OPEN SPI

SHORT SHORT I2C

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Quick Start

2.4.3 RX4 Receiver Input Jumper

Jumper JMP1, located on the EVM daughterboard, is utilized to select the input source for the RX4 line receiver inputs. Selection options are shown in Table 5 .

Table 5. Jumper JMP1, RX4 Input Selection (EVM Daughterboard)

JMP1 Pins JMP1 Pins JMP1 Pins JMP1 Pins

1-2 3-4 5-6 7-8 RX4 Input Source

SHORT SHORT OPEN OPEN RX4 Unbalanced 75 Ω Input (DAIMB connector J9)

OPEN SHORT SHORT OPEN Optical Input Receiver (DAIMB U9) OPEN SHORT OPEN SHORT Logic Level Input (DAIMB header J10)

2.5 Switch Configuration

This sub-section provides an overview of the DIP switch configuration for both the DAIMB motherboard and EVM daughterboard.

2.5.1 Audio Serial Port Slave/Master Configuration

The audio serial ports for the SRC4382 or SRC4392 may operate in either Slave or Master mode. Switches SW1 and SW2 must be configured to match the programmed register configurations for the Port A and Port B audio serial ports on the SRC4382 or SRC4392.

Port A of the SRC4382 or SRC4392 is connected to Port D (or header J4) on the DAIMB motherboard, while Port B is connected to Port B (or header J2) on the motherboard. Switch SW1 must be set to match the Port B slave/master configuration, while switch SW2 must be set to match the Port A slave/master configuration. Switch configuration is summarized in Table 6 , where x = B for Port B, and x = D for Port A.

Table 6. Audio Serial Port Slave/Master Switch Configuration (DAIMB Motherboard)

Switch SW1 or SW2, x_S/M Port Configuration

LO Master

HI Slave

2.5.2 USB Serial Peripheral Interface (SPI) Port Configuration

When the I2C bus is utilized for host communications, the USBSPI switch must be set to HI.

For the DAIMB motherboard, the USBSPI switch on SW5 is utilized to enable or disable the tri-state buffers for the USB controller SPI port connections. Table 7 summarizes the USBSPI switch settings.

Table 7. USB SPI PortConfiguration (DAIMB Motherboard)

Switch SW5, USBSPI USB-based SPI Interface

LO Enabled; the SPI port may be utilized for SRC4382/4392 host

HI Disabled; the SPI port outputs are set to a high-impedance

CAUTION

communications.

state.

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When the USB controller SPI interface is disabled, an external SPI host may be connected via header J22. Refer to the DAIMB electrical schematics in Section 4 of this document for the header pin configuration.

2.5.3 MCLK1 and MCLK2 Clock Configuration

The DAIMB board supports both onboard and external clock generation for two clocks, referred to as MCLK1 and MCLK2. The MCLK1 clock source is buffered and routed to the RXCKI input (pin 13) of the SRC4382 or SCR4392 on the EVM daughterboard. The MCLK2 source is buffered and routed to the MCLK input (pin 25) of the SRC4382 or SRC4392 on the EVM daughterboard.

Switch SW3 selects the clock source for the MCLK1 (that is, RXCKI) clock, while SW4 selects the clock source for MCLK2 (that is, MCLK). Table 8 and Table 9 summarize the SW3 and SW4 switch settings.

Switch SW3, Switch SW3,

OSC2 OSC1 MCLK1 (or RXCKI) Source Selection

LO LO External clock source at BNC connector J17 (X1 and X2 are disabled) LO HI Oscillator X1, 24.576MHz ± 50ppm

HI LO Oscillator X2, 22.5792MHz ± 50ppm HI HI Not allowed due to Oscillator X1 and X2 output contention.

Switch SW4, Switch SW4,

OSC4 OSC3 MCLK2 (or MCLK) Source Selection

LO LO External clock source at BNC connector J18 (X3 and X4 are disabled) LO HI Oscillator X3, 24.576MHz ± 50ppm

HI LO Oscillator X4, 22.5792MHz ± 50ppm HI HI Not allowed due to Oscillator X3 and X4 output contention.

Quick Start

Table 8. MCLK1 Clock Source Selection (DAIMB Daughterboard)

Table 9. MCLK2 Clock Source Selection (DAIMB Daughterboard)

2.5.4 Host Interface and SRC Output Mute Configuration

For the EVM daughterboard, DIP switch SW1 is utilized to manually select the SRC4382 or SRC4392 control port mode via the CPM input (pin 18), and to manually control the mute input, MUTE (pin 14). Bits A0 and A1 for the SRC4382 or SRC4392 I2C slave address may also be configured using this switch.

Table 10 through Table 12 summarize the operation of the SW1 switches.

Table 10. SRC Output Mute Configuration (EVM Daughterboard)

Switch SW1, MUTE SRC Output Mute

LO Disabled; the SRC data output operates normally.

HI Enabled; the SRC data output is forced low.

Table 11. SRC4382/4392 Control Port Mode Configuration (EVM Daughterboard)

Switch SW1, CPM SPI or I2C

LO SPI

HI I2C

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