Texas Instruments SNJ54LVT18502HV Datasheet

SN54LVT18502

3.3-V ABT SCAN TEST DEVICE

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 – JUL Y 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

SCOPE



Family of Testability Products

D

Member of the Texas Instruments

Widebus

 Family

D

State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC)

D

Supports Unregulated Battery Operation
Down to 2.7 V

D

UBT

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup Resistors

D

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture

D

SCOPE

 Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation

From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes

D

Packaged in 68-Pin Ceramic Quad Flat (HV)
Packages Using 25-mil Center-to-Center
Spacings

1B4
1B5
1B6
GND
1B7
1B8
1B9
V

CC

NC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7

1A3
1A4
1A5

GND

1A6
1A7
1A8
1A9

NC

V

CC

2A1
2A2
2A3

GND

2A4
2A5
2A6

VNCTMS

1CLKBA

1A2

1A1

1OEAB

GND

1LEAB

1CLKAB

TDO

NC

TCK

2CLKBA

2LEBA

2A9

GND

2OEAB

2LEAB

2CLKAB

TDI

2A7

2A8

1LEBA

1OEBA

GND

2OEBA

2B9

2B8

GND

1B1

1B2

1B3

HV PACKAGE

(TOP VIEW)

CC

V

CC

NC – No internal connection

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

28 29 30 31 32 33 34

87 65493168672

35 36 37 38 39

66 652764 63 62 61

40 41 42 43

Copyright  1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

SN54LVT18502

3.3-V ABT SCAN TEST DEVICE
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 – JUL Y 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description

The SN54LVT18502 scan test device with 18-bit universal bus transceivers is a member of the Texas
Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Standard

1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test
circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, this device is designed specifically for low-voltage (3.3-V) V

CC

operation, but with the capability

to provide a TTL interface to a 5-V system environment.
In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type

flip-flops to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the T AP
in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.
Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB

is low, the
B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is
similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the T AP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54L VT18502 is characterized for operation over the full military temperature range of –55°C to 125°C.

FUNCTION TABLE

†

(normal mode, each register)

INPUTS

OUTPUT

OEAB LEAB CLKAB A

B

L L L X B

0

‡

L L ↑ LL
L L ↑ HH
L HXLL
L HXHH

H X X X Z

†

A-to-B data flow is shown. B-to-A data flow is similar
but uses OEBA

, LEBA, and CLKBA.

‡

Output level before the indicated steady-state input
conditions were established

SN54LVT18502

3.3-V ABT SCAN TEST DEVICE

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 – JUL Y 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

2A1

1D

C1

1D

C1

1D

C1

1D

C1

Boundary-Control

Register

Bypass Register

Identification

Register

Boundary-Scan Register

Instruction

Register

TAP

Controller

2LEBA

2CLKBA

2OEBA

TDI

TMS
TCK

2B1

TDO

2OEAB

2LEAB

2CLKAB

1A1

1D

C1

1D

C1

1D

C1

1D

C1

1LEBA

1CLKBA

1OEBA

1B1

1OEAB

1LEAB

1CLKAB

V

CC

V

CC

One of Nine Channels

One of Nine Channels

5

4

7
66

67

65

8

32

33

31
39

38

41

20

34

68

37

63

51

3

V

CC

V

CC

V

CC

V

CC

SN54LVT18502

3.3-V ABT SCAN TEST DEVICE
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 – JUL Y 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL NAME DESCRIPTION

1A1–1A9,

2A1–2A9

Normal-function A-bus I/O ports. See function table for normal-mode logic.

1B1–1B9,

2B1–2B9

Normal-function B-bus I/O ports. See function table for normal-mode logic.

1CLKAB, 1CLKBA,
2CLKAB, 2CLKBA

Normal-function clock inputs. See function table for normal-mode logic.

GND Ground

1LEAB, 1LEBA,

2LEAB, 2LEBA

Normal-function latch enables. See function table for normal-mode logic.

1OEAB, 1OEBA,

2OEAB

, 2OEBA

Normal-function output enables. See function table for normal-mode logic. An internal pullup at each terminal forces the
terminal to a high level if left unconnected.

TCK

T est clock. One of four terminals required by IEEE Standard 1149.1-1990. T est operations of the device are synchronous
to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data
through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

TDO

T est data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.

TMS

T est mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its T AP
controller states. An internal pullup forces TMS to a high level if left unconnected.

V

CC

Supply voltage

SN54LVT18502

3.3-V ABT SCAN TEST DEVICE

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 – JUL Y 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard
1 149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. The device
contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit
boundary-control register, a 1-bit bypass register, and a 32-bit device identification register.

Test-Logic-Reset

Run-Test/Idle Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

TMS = L

TMS = L

TMS = H

TMS = L

TMS = H

TMS = H

TMS = LTMS = H

TMS = L

TMS = L

TMS = H

TMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

TMS = L

TMS = L

TMS = H

TMS = L

TMS = H

TMS = H

TMS = LTMS = H

TMS = L

Exit2-IR

TMS = L

TMS = H TMS = H

TMS = H

TMS = L

TMS = H

TMS = L

TMS = HTMS = H

TMS = H

TMS = L

Figure 1. TAP-Controller State Diagram

SN54LVT18502

3.3-V ABT SCAN TEST DEVICE
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 – JUL Y 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

state diagram description

The TAP controller is a synchronous finite state machine that provides test-control signals throughout the
device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP
controller proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the T AP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data
registers can also be reset to their power-up values.

The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected
or if a board defect causes it to be open circuited.

For the SN54LVT18502, the instruction register is reset to the binary value 10000001, which selects the
IDCODE instruction. Bits 47–44 in the boundary-scan register are reset to logic 1, ensuring that these cells that
control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked the outputs would
be at the high-impedance state). Reset value of other bits in the boundary-scan register should be considered
indeterminate. The boundary-control register is reset to the binary value 010, which selects the PSA
test operation.

Run-T est/Idle

The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test
operations. The Run-Test /Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.

SN54LVT18502

3.3-V ABT SCAN TEST DEVICE

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 – JUL Y 1996

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO. On the first
falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level
present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, such update occurs
on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the T AP controller exits the Capture-IR state. For the SN54LVT18502,
the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO. On
the first falling edge of TCK, TDO goes from the high-impedance state to the active state. TDO enables to the
logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the
first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss
of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.

SN54LVT18502

3.3-V ABT SCAN TEST DEVICE
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 – JUL Y 1996

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

register overview

With the exception of the bypass and device-identification registers, any test register can be thought of as a
serial shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that
they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

T able 3 lists the instructions supported by the SN54L VT18502. The even-parity feature specified for SCOPE
devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are
defined for SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the T est-Logic-Reset state, the IR is reset to the
binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

TDOTDI

Bit 7
Parity
(MSB)

Bit 0

(LSB)

Figure 2. Instruction Register Order of Scan

SN54LVT18502

3.3-V ABT SCAN TEST DEVICE

WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

SCBS669 – JUL Y 1996

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

data register description

boundary-scan register

The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and
output data). The BSR is used 1) to store test data that is to be applied externally to the device output pins,
and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at
the device input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle, as determined by the current instruction. At power up
or in Test-Logic-Reset, BSCs 47–44 are reset to logic 1, ensuring that these cells, which control A-port and
B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at the
high-impedance state). Reset values of other BSCs should be considered indeterminate.

The BSR order of scan is from TDI through bits 47–0 to TDO. T able 1 shows the BSR bits and their associated
device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

DEVICE
SIGNAL

BSR BIT

NUMBER

DEVICE
SIGNAL

BSR BIT

NUMBER

DEVICE
SIGNAL

47 2OEAB 35 2A9-I/O 17 2B9-I/O
46 1OEAB 34 2A8-I/O 16 2B8-I/O
45 2OEBA 33 2A7-I/O 15 2B7-I/O
44 1OEBA 32 2A6-I/O 14 2B6-I/O
43 2CLKAB 31 2A5-I/O 13 2B5-I/O
42 1CLKAB 30 2A4-I/O 12 2B4-I/O
41 2CLKBA 29 2A3-I/O 11 2B3-I/O
40 1CLKBA 28 2A2-I/O 10 2B2-I/O
39 2LEAB 27 2A1-I/O 9 2B1-I/O

38 1LEAB 26 1A9-I/O 8 1B9-I/O
37 2LEBA 25 1A8-I/O 7 1B8-I/O
36 1LEBA 24 1A7-I/O 6 1B7-I/O
–– –– 23 1A6-I/O 5 1B6-I/O
–– –– 22 1A5-I/O 4 1B5-I/O
–– –– 21 1A4-I/O 3 1B4-I/O
–– –– 20 1A3-I/O 2 1B3-I/O
–– –– 19 1A2-I/O 1 1B2-I/O
–– –– 18 1A1-I/O 0 1B1-I/O