Datasheet SN54HC373J, SN74HC373DBLE, SN74HC373DBR, SN74HC373DW, SN74HC373DWR Datasheet (Texas Instruments)
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SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MA Y 1997
D
Eight High-Current Latches in a Single
Package
D
High-Current 3-State True Outputs Can
Drive up to 15 LSTTL Loads
D
Full Parallel Access for Loading
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches of the ’HC373 are transparent
D-type latches. While the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the levels that were set up at the D inputs.
SN54HC373 ...J OR W PACKAGE
SN74HC373 . . . DB, DW, N, OR PW PACKAGE
SN54HC373 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
(TOP VIEW)
OE
1
1Q
2
1D
3
2D
4
2Q
5
3Q
6
3D
7
4D
8
4Q
9
GND
10
(TOP VIEW)
1D1QOE
3212019
4
5
6
7
8
910111213
20
19
18
17
16
15
14
13
12
11
V
CC
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
8Q
18
17
16
15
14
CC
8D
7D
7Q
6Q
6D
An output-enable (OE
outputs in either a normal logic state (high or low
) input places the eight
4Q
GND
LE
5Q
5D
logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE
does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The SN54HC373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MA Y 1997
FUNCTION TABLE
INPUTS
OE LE D
L H H H
L HL L
L LX Q
H X X Z
(each latch)
OUTPUT
Q
0
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
LE
1D
2D
3D
4D
5D
6D
7D
8D
1
11
3
4
7
8
13
14
17
18
EN
C1
1D
logic diagram (positive logic)
1
OE
11
LE
C1
1D
1D
3
12
15
16
19
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
2
1Q
To Seven Other Channels
2
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UNIT
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MA Y 1997
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54HC373 SN74HC373
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
Supply voltage 2 5 6 2 5 6 V
CC
VCC = 2 V 1.5 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 –40 85 °C
A
VCC = 4.5 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8 0 1.8
VCC = 2 V 0 1000 0 1000
VCC = 4.5 V
VCC = 6 V 0 400 0 400
3.15 3.15
0 1.35 0 1.35
CC
CC
0 500 0 500
0 V
0 V
CC
CC
V
V
V
V
ns
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3
SN54HC373, SN74HC373
PARAMETER
TEST CONDITIONS
V
UNIT
V
UNIT
↓
↓
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54HC373 SN74HC373
MIN TYP MAX MIN MAX MIN MAX
V
V
V
V
I
I
I
C
OH
OL
I
OZ
CC
CC
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA
VI = VIH or V
VI = VIH or V
VI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5 µA
VI = VCC or 0, IO = 0 6 V 8 160 80 µA
i
IL
IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –7.8 mA 6 V 5.48 5.8 5.2 5.34
IOL = 20 µA
IL
IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
2 V to 6 V 3 10 10 10 pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HC373 SN74HC373
CC
MIN MAX MIN MAX MIN MAX
2 V 80 120 100
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE
Hold time, data after LE
4.5 V
6 V 14 20 17
2 V 50 75 63
4.5 V 10 15 13
6 V 9 13 11
2 V 20 26 24
4.5 V 10 13 12
6 V 10 13 12
16 24 20
ns
ns
ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
V
UNIT
t
ns
PARAMETER
V
UNIT
t
ns
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
D Q
pd
LE Any Q
t
en
t
dis
t
t
OE Any Q
OE Any Q
Any Q
CC
2 V 58 150 225 190
4.5 V 15 30 45 38
6 V 13 26 38 32
2 V 73 175 265 220
4.5 V 18 35 53 44
6 V 15 30 45 38
2 V 65 150 225 190
4.5 V 17 30 45 38
6 V 14 26 38 32
2 V 50 150 225 190
4.5 V 15 30 45 38
6 V 13 26 38 32
2 V 28 60 90 75
4.5 V 8 12 18 15
6 V 6 10 15 13
TA = 25°C SN54HC373 SN74HC373
MIN TYP MAX MIN MAX MIN MAX
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
D Q
pd
LE Any Q
t
en
t
t
OE Any Q
Any Q
CC
2 V 82 200 300 250
4.5 V 22 40 60 50
6 V 19 34 51 43
2 V 100 225 335 285
4.5 V 24 45 67 57
6 V 20 38 57 48
2 V 90 200 300 250
4.5 V 23 40 60 50
6 V 19 34 51 43
2 V 45 210 315 265
4.5 V 17 42 63 53
6 V 13 36 53 45
TA = 25°C SN54HC373 SN74HC373
MIN TYP MAX MIN MAX MIN MAX
ns
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per latch No load 100 pF
pd
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5
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
50%
50%
S1
S2
V
0 V
V
0 V
CC
CC
From Output
Under Test
(see Note A)
High-Level
Pulse
Low-Level
Pulse
Test
Point
C
L
LOAD CIRCUIT
50%
50%
VOLTAGE WAVEFORMS
PULSE DURATIONS
R
L
t
w
PARAMETER C
t
Data
t
PZH
t
PZL
t
PHZ
t
PLZ
t
en
t
dis
tpd or t
Reference
Input
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
R
L
1 kΩ
1 kΩ
t
su
90% 90%
VOLTAGE WAVEFORMS
t
r
L
50 pF
or
150 pF
50 pF
50 pF
or
150 pF
50%
S1
Open Closed
Closed Open
Open Closed
Closed Open
Open Open––
t
h
50%50%
S2
V
CC
0 V
V
CC
10%10%
0 V
t
f
Input
In-Phase
Output
Out-of-
Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
50%
t
PLH
90% 90%
t
PHL
50% 50%
10% 10%
VOLTAGE WAVEFORMS
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
50%
t
PHL
50%50%
t
r
t
PLH
t
f
.
dis
Figure 1. Load Circuit and Voltage Waveforms
V
CC
0 V
V
OH
10%10%
V
OL
t
f
V
OH
90%90%
V
OL
t
r
Output
Control
(Low-Level
Enabling)
t
PZL
Output
Waveform 1
(See Note B)
t
PZH
Output
Waveform 2
(See Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
50%
≈ V
CC
50%
50%
VOLTAGE WAVEFORMS
50%
t
PLZ
10%
90%
t
PHZ
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
6
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