Texas Instruments SN74BCT652DW, SN74BCT652DWR, SN74BCT652NT, SNJ54BCT652W, SNJ54BCT652FK Datasheet

SN54BCT652, SN74BCT652

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993

• State-of-the-Art BiCMOS Design

Significantly Reduces I

CCZ

• ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)

• Independent Registers and Enables for

A and B Buses

• Multiplexed Real-Time and Stored Data

• Power-Up High-Impedance Mode

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK) and Flatpacks (W), and
Standard Plastic and Ceramic 300-mil DIPs
(JT, NT)

description

These devices consist of bus transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.

Output-enable (OEAB and OEBA
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-management functions that can be performed
with the ′BCT652.

) inputs are

SN54BCT652 ...JT OR W PACKAGE

SN74BCT652 ... DW OR NT PACKAGE

CLKAB

OEAB

SN54BCT652 . . . FK PACKAGE

A1
A2
A3

NC

A4
A5
A6

NC – No internal connection

SAB

A1
A2
A3
A4
A5
A6
A7
A8

GND

4

5
6
7
8
9
10
11

12

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12

(TOP VIEW)

SAB

CLKAB

OEAB

321

13 14

15 16 17 18

A8

A7

GND

24
23
22
21
20
19
18
17
16
15
14
13

CC

NC

V

28 27 26

B8B7B6

NC

V

CC

CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8

CLKBA

SBA

25
24
23
22
21
20
19

OEBA
B1
B2
NC
B3
B4
B5

Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by
simultaneously enabling OEAB and OEBA. In this configuration each output reinforces its input. Therefore,
when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remain at
its last state.

The SN54BCT652 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74BCT652 is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1993, Texas Instruments Incorporated

2–1

SN54BCT652, SN74BCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993

3

OEAB

L

BUS A

21

OEBA

L

BUS A

1

CLKAB

REAL-TIME TRANSFER

BUS B TO BUS A

CLKBA

X

23

BUS B

2

22

SAB

X

SBA

X

L

BUS B

OEAB OEBA

BUS A

3

21

H

H

BUS A

1

CLKAB

X

REAL-TIME TRANSFER

BUS A TO BUS B

23

CLKBA

X

2

SAB

L

BUS B

22

SBA

X

BUS B

3

OEAB

X
L
L

21

OEBA

H
X
H

1

CLKAB23CLKBA

X

↑

XX

STORAGE FROM

A, B, OR A AND B

2

SAB

X

↑

X

↑↑

22

SBA

X
X
X

Figure 1. Bus-Management Functions

Pin numbers shown are for the DW, JT, NT, and W packages.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

321

OEAB OEBA

HL L HH

LL X XHL

HH L HXX

1

CLKAB23CLKBA2SAB22SBA

L

TRANSFER STORED DA TA

TO A AND/OR B

SN54BCT652, SN74BCT652

OPERATION OR FUNCTION

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS038A – AUGUST 1989 – REVISED NOVEMBER 1993

FUNCTION TABLE

INPUTS

OEAB OEBA CLKAB CLKBA SAB SBA A1 THRU A8 B1 THRU B8

L H H or L H or L X X Input Input Isolation

L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified
H H ↑↑X
L X H or L ↑ X X Unspecified
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus

H L H or L H or L H H Output Output

†

The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are
always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs.

‡

Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered in order to load both registers.

‡

X Input Output Store A in both registers

DATA I/O

‡

†

‡

Input Hold A, store B

Store A, hold B

Stored A data to B bus and

stored B data to A bus

logic symbol

§

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, JT, NT, and W packages.

§

SBA

SAB

A1

A2
A3
A4
A5
A6
A7
A8

21
3
23
22

1
2

4

5
6
7
8
9
10
11

EN1 [BA]
EN2 [AB]

C4

G5

C6

G7

5

≥1

1

6D ≥1

5
7
7

1

4D

1

2

OEBA

OEAB

CLKBA

CLKAB

20

19
18
17
16
15
14
13

B1

B2
B3
B4
B5
B6
B7
B8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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