Texas Instruments SN74ALS996-1NT, SN74ALS996DW, SN74ALS996DWR, SN74ALS996NT, SN74ALS996NT3 Datasheet
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SN54ALS996 . . . JT PACKAGE
SN74ALS996 . . . DW OR NT PACKAGE
(TOP VIEW)
SN54ALS996 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
1D
2D
3D
4D
5D
6D
7D
8D
EN
RD
CLK
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
OE
T/C
CLR
NC – No internal connection
3212827
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
3Q
4Q
5Q
NC
6Q
7Q
8Q
4D
5D
6D
NC
7D
8D
EN
426
14 15 16 17 18
RD
CLK
GND
NC
CLR
T/C
OE
3D2D1D
NC
1Q
2Q
V
CC
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• 3-State I/O-Type Read-Back Inputs
• Bus-Structured Pinout
• T/C Determines True or Complementary
Data at Q Outputs
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
description
These 8-bit latches are designed specifically for
storing the contents of the input data bus and
providing the capability of reading back the stored
data onto the input data bus. The Q outputs are
designed with bus-driving capability.
The edge-triggered flip-flops enter the data on the
low-to-high transition of the clock (CLK) input
when the enable (EN
) input is low. Data can be
read back onto the data inputs by taking the read
(RD
) input low, in addition to having EN low . When
EN
is high, both the read-back and write modes
are disabled. Transitions on EN
should only be
made with CLK high to prevent false clocking.
The polarity of the Q outputs can be controlled by
the polarity (T/C
) input. When T/C is high, Q is the
same as is stored in the flip-flops. When T/C
is low,
the output data is inverted. The Q outputs can be
placed in the high-impedance state by taking the
output-enable (OE
) input high. OE does not affect
the internal operation of the register. Old data can
be retained or new data can be entered while the
outputs are off.
A low level at the clear (CLR
) input resets the
internal registers low. The clear function is
asynchronous and overrides all other register
functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum
I
OL
for the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.
The SN54ALS996 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ALS996 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
11
CLK
2D
2
3D
3
4D
4
5D
5
6D
6
7D
7
8D
8
5Q
19
6Q
18
7Q
17
8Q
16
2Q
22
3Q
21
4Q
20
1Q
23
1D
1
1D
9
EN
2
10
RD
R
13
CLR
N3
14
T/C
EN4
15
OE
3,4
&
EN2
C1
≥ 1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, JT, and NT packages.
logic diagram (positive logic)
To Seven Other Channels
15
23
OE
1Q
14
T/C
13
CLR
10
RD
1D
C1
R
9
EN
11
CLK
1
1D
Pin numbers shown are for the DW, JT, and NT packages.
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing diagram
ÌÌ
ÌÌ
ÌÌ
(T/C = H)
CLR
D
EN
RD
Q
OE
Async
Clear
Write
Input Data
Output
CLK
Read-Back Data
Output Data
Read
Back
t
su
t
h
t
w
t
su
t
dis
t
dis
t
dis
t
p
t
h
†
t
en
t
en
t
en
†
This hold time ensures that the read-back circuit will not create a conflict on the input data bus.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
(OE, RD, EN, CLK, CLR, and T/C) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to D inputs and to disabled 3-state outputs 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS996 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS996 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54ALS996 SN74ALS996
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
All inputs 2
V
IH
High-level input voltage
All inputs except OE, RD 2
V
OE, RD 2.2
V
IL
Low-level input voltage 0.8 0.8 V
p
Q –1 –2.6
IOHHigh-level output current
D –0.4 –0.4
mA
12 24
I
OL
Low-level output current
Q
48
†
mA
D 8 8
f
clock
Clock frequency 0 35 0 35 MHZ
CLR low 10 10
t
w
Pulse duration
CLK low
14.5 14.5
ns
CLK high 14.5 14.5
Data before CLK↑ 15 15
p
EN low before CLK↑ 10 10
tsuSetup time
CLK high before EN↑
‡
15 15
ns
CLR high (inactive) before CLK↑ 10 10
Data after CLK↑ 1 0
t
h
Hold time
EN
low after CLK↑ 5 5
ns
RD high after CLK↑
§
5 5
T
A
Operating free-air temperature –55 125 0 70 °C
†
Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25 V
‡
This setup time ensures that EN
will not false clock the data register.
§
This hold time ensures that there will be no conflict on the input data bus.
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS996 SN74ALS996
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
All outputs VCC = 4.5 V to 5.5 V, IOH = – 0.4 mA VCC –2 VCC –2
V
OH
IOH = – 1 mA 2.4 3.2
V
Q
V
CC
= 4.5
V
IOH = – 2.6 mA 2.4 3.2
IOL = 4 mA 0.25 0.4
D
V
CC
= 4.5
V
IOL = 8 mA 0.35 0.5
V
OL
IOL = 12 mA 0.25 0.4 0.25 0.4
V
Q
VCC = 4.5 V
IOL = 24 mA 0.35 0.5
IOL = 48 mA
‡
0.35 0.5
I
OZH
Q VCC = 5.5 V, VO = 2.7 V 20 20 µA
I
OZL
Q VCC = 5.5 V, VO = 0.4 V –20 –20 µA
D inputs
VI = 5.5 V 0.1 0.1
I
I
All others
V
CC
= 5.5
V
VI = 7 V 0.1 0.1
mA
D inputs
§
20 20
I
IH
All others
V
CC
= 5.5 V,
V
I
= 2.7
V
20 20
µ
A
D inputs
§
–0.1 –0.1
I
IL
All others
V
CC
= 5.5 V,
V
I
= 0.4
V
–0.1 –0.1
mA
I
O
¶
VCC = 5.5 V, VO = 2.25 V
CLR
= 2.5 V
–20 –112 –30 –112 mA
Outputs high 35 55 35 55
I
CC
VCC = 5.5 V,
Outputs low 55 85 55 85
mA
EN, RD low
Outputs disabled 42 65 42 65
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25 V
§
For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current.
¶
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
FROM
TO
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
TA = MIN to MAX
†
PARAMETER
(INPUT)
(OUTPUT)
SN54ALS996 SN74ALS996
UNIT
MIN MAX MIN MAX
f
max
35 35 MHz
t
PLH
CLK
5 30 5 28
t
PHL
(T/C = H or L)
Q
5 24 5 28
ns
t
PLH
CLR (T/C = L)
5 27 7 27
t
PHL
CLR (T/C = H)
Q
5 23 7 23
ns
t
PLH
4 23 5 23
t
PHL
T/C
Q
5 23 5 23
ns
t
PHL
CLR
D
5 30 8 30 ns
t
en
‡
2 18 3 16
t
dis
§
RD
D
1 19 3 19
ns
t
en
‡
2 17 3 16
t
dis
§
EN
D
1 19 3 19
ns
t
en
‡
2 15 4 15
t
dis
§
OE
Q
1 11 1 10
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
ten = t
PZH
or t
PZL
§
t
dis
= t
PHZ
or t
PLZ
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT FOR Q OUTPUTS
From Output
Under Test
Test
Point
500 Ω
S1
C
L
(see Note A)
7 V
500 Ω
LOAD CIRCUIT FOR D OUTPUTS
From Output
Under Test
Test
Point
1 kΩ
S1
C
L
(see Note A)
7 V
1 kΩ
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PHZ
t
PLZ
0.3 V
t
PZL
t
PZH
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note C)
Waveform 2
S1 Open
(see Note C)
[
0 V
V
OH
V
OL
[
3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
t
PHL
t
PLH
t
PLH
t
PHL
Input
Out-of-Phase
Output
(see Note B)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
3.5 V
0.3 V
V
OL
V
OH
V
OH
V
OL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. When measuring propagation delay times of 3-state outputs, switch S1 is open.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
Figure 1. Load Circuits and Voltage Waveforms
SN54ALS996, SN74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
SDAS098B – OCTOBER 1984 – REVISED JANUARY 1995
2–8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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