Datasheet SN74ALS561ADW, SN74ALS561ADWR, SN74ALS561AN, SNJ54ALS561AJ Datasheet (Texas Instruments)
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Carry Output for n-Bit Cascading
• Buffer-Type Outputs Drive Bus Lines
Directly
• Choice of Asynchronous or Synchronous
Clearing and Loading
• Internal Look-Ahead Circuitry for Fast
Cascading
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
These binary counters are programmable and
offer synchronous and asynchronous clearing as
well as synchronous and asynchronous loading.
All synchronous functions are executed on the
positive-going edge of the clock.
The clear function is initiated by applying a low
level to either asynchronous clear (ACLR
) or
synchronous clear (SCLR
). ACLR (direct clear)
overrides all other functions of the device, while
SCLR
overrides only the other synchronous
functions. Data is loaded from the A, B, C, and D
inputs by applying a low level to asynchronous
load (ALOAD
) or by the combination of a low level
at synchronous load (SLOAD
) and a
positive-going clock transition. The counting
function is enabled only when enable P (ENP),
enable T (ENT), ACLR
, ALOAD, SCLR, and
SLOAD
are all high.
A high level at the output-enable (OE
) input forces the Q outputs into the high-impedance state, and a low level
enables those outputs. Counting is independent of OE
. ENT is fed forward to enable the ripple-carry output
(RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces
a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is
enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated
with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter
to ENT of the next counter. However , for very high-speed counting, RCO should be used for cascading because
CCO does not become active until the clock returns to the low level.
The SN54ALS561A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS561A is characterized for operation from 0°C to 70°C.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ALOAD
CLK
A
B
C
D
ENP
ACLR
SCLR
GND
V
CC
RCO
CCO
OE
Q
A
Q
B
Q
C
Q
D
ENT
SLOAD
SN54ALS561A ...J PACKAGE
SN74ALS561A . . . DW OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
CCO
OE
Q
A
Q
B
Q
C
B
C
D
ENP
ACLR
A
CLK
ALOAD
ENT
Q
RCO
SCLR
GND
SLOAD
V
CC
SN54ALS561A . . . FK PACKAGE
(TOP VIEW)
D
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUAR Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OE ACLR ALOAD SCLR SLOAD ENT ENP CLK
OPERATION
H X X X X X X X Q outputs disabled
L L X X X X X X Asynchronous clear
L H L X X X X X Asynchronous load
L HHLXXX↑Synchronous clear
L HHHLXX↑Synchronous load
L HHHHHH↑ Count
L H H H H L X X Inhibit counting
L H H H H X L X Inhibit counting
logic symbol
†
CTRDIV16
C8
1
2
CLK
4,6D/8D
3
A
4
B
5
C
6
D
C6/1, 2, 3, 5+
M5 [COUNT]
Z7
CCO
18
7, 1, 2, 9
RCO
19
1 (CT=15) G9
16
15
14
13
CT=0
8
M4 [SYNC LOAD]
11
M3 [COUNT]
6CT=0 [SYNC CLR]
9
G2
7
ENP
G1
12
ENT
EN10
17
10
OE
SCLR
SLOAD
ACLR
ALOAD
Q
A
Q
B
Q
C
Q
D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
R
S
1D
C1
R
S
1D
C1
R
S
1D
C1
R
S
1D
C1
17
12
7
9
11
2
8
1
3
4
5
6
18
19
16
15
14
13
CCO
RCO
Q
A
Q
B
Q
C
Q
D
OE
ENT
ENP
SCLR
SLOAD
CLK
ACLR
ALOAD
A
B
C
D
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUAR Y 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical load, count, and inhibit sequences
Inhibit Counting
Hi-Z
Continue CountingSync
Load
Sync
Clear
Async
Load
Async
Clear
RCO
CCO
Q
D
Q
C
Q
B
Q
A
D
C
B
A
CLK
ENT
ENP
SLOAD
ALOAD
SCLR
ACLR
OE
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Hi-Z
Hi-Z
Hi-Z
Hi-Z
12 13 14 15 0 1 13 14 15 0 1 5
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS561A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS561A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS561A SN74ALS561A
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.7 0.8 V
p
Q outputs –1 –2.6
IOHHigh-level output current
CCO and RCO –0.4 –0.4
mA
p
Q outputs 12 24
IOLLow-level output current
CCO and RCO 4 8
mA
f
clock
Clock frequency 0 20 0 30 MHz
ACLR or ALOAD low 20 15
t
w
Pulse duration
CLK high
20 16.5
ns
CLK low 25 16.5
High 25 20
ENP, ENT
Low 25 20
Data at A, B, C, D 25 20
Low 21 15
tsuSet
up time before
CLK↑
SCLR
High (inactive) 35 30
ns
Low 20 15
SLOAD
High (inactive) 35 30
ACLR or ALOAD inactive
12 10
t
h
Hold time after CLK↑ for data, ENP, ENT, SCLR, or SLOAD 0 0 ns
T
A
Operating free-air temperature –55 125 0 70 °C
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUAR Y 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS561A SN74ALS561A
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
All outputs VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2
V
OH
p
IOH = –1 mA 2.4 3.3
V
Q outputs
V
CC
= 4.5
V
IOH = –2.6 mA 2.4 3.2
p
IOL = 12 mA 0.25 0.4 0.25 0.4
Q outputs
V
CC
= 4.5
V
IOL = 24 mA 0.35 0.5
V
OL
IOL = 4 mA 0.25 0.4 0.25 0.4
V
CCO and RCO
V
CC
= 4.5
V
IOL = 8 mA 0.35 0.5
I
OZH
VCC = 5.5 V, VO = 2.7 V 20 20 µA
I
OZL
VCC = 5.5 V, VO = 0.4 V –20 –20 µA
ENP and ENT
0.2 0.2
I
I
Other inputs
V
CC
=
5.5 V
,
V
I
=
7 V
0.1 0.1
mA
ENP and ENT
40 40
I
IH
Other inputs
V
CC
= 5.5 V,
V
I
= 2.7
V
20 20
µ
A
I
IL
VCC = 5.5 V, VI = 0.4 V –0.2 –0.2 mA
CCO and RCO
–15 –70 –15 –70
I
O
‡
Q
V
CC
=
5.5 V
,
V
O
=
2.25 V
–20 –112 –30 –112
mA
Outputs high 17 27 17 27
I
CC
VCC = 5.5 V
Outputs low 21 33 21 33
mA
Outputs disabled 22 36 22 36
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUARY 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω
,
R2 = 500 Ω,
TA = MIN to MAX
†
UNIT
SN54ALS561A SN74ALS561A
MIN MAX MIN MAX
f
max
20 30 MHz
t
PLH
4 15 4 12
t
PHL
CLK
Any Q
5 21 5 18
ns
t
PLH
9 35 9 29
t
PHL
CLK
RCO
8 29 8 24
ns
t
PLH
8 35 8 26
t
PHL
CLK
CCO
5 20 5 16
ns
t
PLH
10 38 10 35
t
PHL
ALOAD
Any Q
7 27 7 23
ns
t
PLH
15 50 15 40
t
PHL
ALOAD
RCO
12 35 12 30
ns
t
PLH
25 65 25 55
t
PHL
ALOAD
CCO
12 42 12 33
ns
t
PLH
8 35 8 30
t
PHL
A, B, C
, or
D
Any Q
7 27 7 22
ns
t
PLH
5 20 5 16
t
PHL
ENT
RCO
4 18 4 14
ns
t
PLH
12 35 12 32
t
PHL
ENT
CCO
4 15 4 12
ns
t
PLH
5 22 5 18
t
PHL
ENP
CCO
4 14 4 12
ns
t
PHL
ACLR
Any Q 7 28 7 22 ns
t
PZH
5 24 5 19
t
PZL
OE
Any Q
8 28 8 23
ns
t
PHZ
2 12 2 10
t
PLZ
OE
Any Q
2 20 4 15
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS561A, SN74ALS561A
SYNCHRONOUS 4-BIT COUNTERS
WITH 3-STATE OUTPUTS
SDAS225A – DECEMBER 1982 – REVISED JANUAR Y 1995
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
t
PHZ
t
PLZ
t
PHL
t
PLH
0.3 V
t
PZL
t
PZH
t
PLH
t
PHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
C
L
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
V
OL
V
OH
V
OH
V
OL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
V
OH
V
OL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
V
CC
R
L
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
C
L
(see Note A)
R
L
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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