Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
The SN54ALS137A, SN74ALS137A, and
SN74AS137 are 3-line to 8-line decoders/
demultiplexers with latches on the three address
inputs. When the latch-enable (LE
the devices act as decoders/demultiplexers.
When LE
goes from low to high, the address
present at the select (A, B, and C) inputs is stored
in the latches. Further address changes are
ignored as long as LE
remains high. The
output-enable controls (G1 and G2
outputs independently of the select or
latch-enable inputs. All of the outputs are forced
high if G1 is low or G2
is high. These devices are
ideally suited for implementing glitch-free
decoders in strobed (stored-address) applications
in bus-oriented systems.
The SN54ALS137A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS137A and SN74AS137
are characterized for operation from 0°C to 70°C.
) input is low,
) control the
SN74ALS137A, SN74AS137 ...D OR N PACKAGE
SN54ALS137A ...J PACKAGE
(TOP VIEW)
A
1
B
2
C
3
LE
4
G2
5
G1
6
Y7
7
GND
SN54ALS137A . . . FK PACKAGE
8
(TOP VIEW)
BANC
3 2 1 20 19
C
4
5
LE
6
NC
7
G2
8
G1
910111213
Y7
GND
NC – No internal connection
16
15
14
13
12
11
10
NC
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
9
CC
Y0
V
Y1
18
17
Y2
16
NC
15
Y3
14
Y4
Y6
Y5
INPUTS
ENABLESELECT
LEG1G2CBAY0Y1Y2Y3Y4Y5Y6Y7
XXHXXXHHHHHHHH
XLXXXXHHHHHHHH
LHLL LLLHHHHHHH
LHLLLHHLHHHHHH
LHLLHLHHLHHHHH
LHLLHHHHHLHHHH
LHLHL LHHHHLHHH
LHLHLHHHHHHLHH
LHLHHLHHHHHHLH
LHLHHHHHHHHHHL
HHLXXX Outputs corresponding to stored address = L; all others = H
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
Copyright 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ALS137A, SN74ALS137A, SN74AS137
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
SDAS203C – APRIL 1982 – REVISED JANUARY 1995
X/Y
†
15
0
1
2
3
4
5
6
7
14
13
12
11
10
Y0
Y1
Y2
Y3
Y4
Y5
9
Y6
7
Y7
LE
G1
G2
4
1
A
2
B
3
C
6
5
logic symbols (alternatives)
4
LE
1
A
2
B
3
C
6
G1
5
G2
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
C8
8D
&
1
2
4
EN
logic diagram (positive logic)
1
A
C8
8D
&
DMUX
0
2
15
0
1
2
0
G
7
3
4
5
6
7
15
Y0
14
Y1
14
13
12
11
10
Y0
Y1
Y2
Y3
Y4
Y5
9
Y6
7
Y7
LE
G2
G1
2
B
3
C
4
5
6
Select
Inputs
Latch
Enable
Output
Enables
Pin numbers shown are for the D, J, and N packages.
13
12
11
10
Y2
Y3
Data
Outputs
Y4
Y5
9
Y6
7
Y7
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS137A, SN74ALS137A, SN74AS137
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
4.5 V
V
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
SDAS203C – APRIL 1982 – REVISED JANUARY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Supply voltage4.555.54.555.5V
High-level input voltage22V
Low-level input voltage0.70.8V
High-level output current–0.4–0.4mA
Low-level output current48mA
Pulse duration, LE low1510ns
Setup time at A, B, and C before LE↑1510ns
Hold time at A, B, and C after LE↑55ns
Operating free-air temperature–55125070°C
†
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS137ASN74ALS137A
MIN TYP‡MAXMIN TYP‡MAX
V
IK
V
OH
OL
I
I
I
IH
I
IL
§
I
O
I
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
CC
VCC = 4.5 V,II = –18 mA–1.5–1.5V
VCC = 4.5 V to 5.5 V,IOH = –0.4 mAVCC –2VCC –2V
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Supply voltage4.555.5V
High-level input voltage2V
Low-level input voltage0.8V
High-level output current–2mA
Low-level output current20mA
Pulse duration, LE low6.5ns
Setup time at A, B, and C before LE↑4ns
Hold time at A, B, and C after LE↑1ns
Operating free-air temperature070°C
‡
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS137A, SN74ALS137A, SN74AS137
PARAMETER
TEST CONDITIONS
UNIT
(
)
(
)
(INPUT)
(OUTPUT)
A, B, C
Y
ns
G2
Y
ns
G1
Y
ns
LE
Y
ns
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
SDAS203C – APRIL 1982 – REVISED JANUARY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74AS137
MIN TYP†MAX
V
IK
V
OH
V
OL
I
I
I
IH
I
IL
‡
I
O
I
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
CC
switching characteristics (see Figure 1)
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS137A, SN74ALS137A, SN74AS137
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
SDAS203C – APRIL 1982 – REVISED JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
V
CC
From Output
Under Test
(see Note A)
C
L
Test
Point
R
L
From Output
Under Test
C
(see Note A)
L
R
L
Test
Point
From Output
Under Test
(see Note A)
7 V
RL = R1 = R2
S1
R1
C
L
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V1.3 V
t
w
1.3 V1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V1.3 V
t
PLH
t
PHL
1.3 V1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOL VE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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