Texas Instruments JM38510-37005B2A, JM38510-37005BEA, SN54ALS133J, SN74ALS133D, SN74ALS133DR Datasheet

SN54ALS133, SN74ALS133

13-INPUT POSITIVE-NAND GATES

SDAS202B – APRIL 1982 – REVISED DECEMBER 1994

Copyright  1994, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs

description

These devices contain a 13-input positive-NAND
gate. They perform the following Boolean
functions in positive logic:

Y=A

•B•C•D•E•F•G•H•I•J•K•L•M

Y=A

+B+C+D+E+F+G+H+I+J+K+L+M

The SN54ALS133 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ALS133 is characterized for
operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS A – M

OUTPUT

Y

All inputs H L
One or more inputs L H

logic symbol

†

logic diagram (positive logic)

&

Y

9

1

A

2

B

3

C

4

D

5

E

13

K

14

L

15

M

6

F

7

G

10

H

11

I

12

J

Y

9

1

A

2

B

3

C

4

D

5

E

13

K

14

L

15

M

6

F

7

G

10

H

11

I

12

J

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

SN54ALS133 ...J PACKAGE

SN74ALS133 ...D OR N PACKAGE

(TOP VIEW)

SN54ALS133 . . . FK PACKAGE

(TOP VIEW)

NC – No internal connection

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

A
B
C
D
E
F

G

GND

V

CC

M
L
K
J
I
H
Y

3212019

910111213

4
5
6
7
8

18
17
16
15
14

L
K
NC
J
I

C
D

NC

E
F

AYV

M

G

CC

GND

NC

H

B

NC

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN54ALS133, SN74ALS133
13-INPUT POSITIVE-NAND GATES

SDAS202B – APRIL 1982 – REVISED DECEMBER 1994

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, V

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, V

I

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: SN54ALS133 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ALS133 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

SN54ALS133 SN74ALS133

MIN NOM MAX MIN NOM MAX

UNIT

V

CC

Supply voltage 4.5 5 5.5 4.5 5 5.5 V

V

IH

High-level input voltage 2 2 V

p

0.8

‡

0.8

VILLow-level input voltage

0.7

§

V

I

OH

High-level output current –0.4 –0.4 mA

I

OL

Low-level output current 4 8 mA

T

A

Operating free-air temperature –55 125 0 70 °C

‡

Applies over temperature range –55°C to 70°C

§

Applies over temperature range 70°C to 125°C

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54ALS133 SN74ALS133

PARAMETER

TEST CONDITIONS

MIN TYP¶MAX MIN TYP¶MAX

UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.2 –1.5 V

V

OH

VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 VCC–2 V

IOL = 4 mA 0.25 0.5 0.25 0.4

V

OL

V

CC

= 4.5

V

IOL = 8 mA 0.35 0.5

V

I

I

VCC = 5.5 V, VI = 7 V 0.1 0.1 mA

I

IH

VCC = 5.5 V, VI = 2.7 V 20 20 µA

I

IL

VCC = 5.5 V, VI = 0.4 V –0.1 –0.1 mA

I

O

#

VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA

I

CCH

VCC = 5.5 V, VI = 0 0.24 0.34 0.24 0.34 mA

I

CCL

VCC = 5.5 V, VI = 4.5 V 0.56 0.8 0.56 0.08 mA

¶

All typical values are at VCC = 5 V, TA = 25°C.

#

The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

SN54ALS133, SN74ALS133

13-INPUT POSITIVE-NAND GATES

SDAS202B – APRIL 1982 – REVISED DECEMBER 1994

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics (see Figure 1)

PARAMETER

FROM

(

INPUT

)

TO

(

OUTPUT

)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX

†

UNIT

(INPUT)

(OUTPUT)

SN54ALS133 SN74ALS133

MIN MAX MIN MAX

t

PLH

1 16 3 11

t

PHL

A

ny

Y

1 47 5 25

ns

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

SN54ALS133, SN74ALS133
13-INPUT POSITIVE-NAND GATES

SDAS202B – APRIL 1982 – REVISED DECEMBER 1994

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

t

PHZ

t

PLZ

t

PHL

t

PLH

0.3 V

t

PZL

t

PZH

t

PLH

t

PHL

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

From Output

Under Test

Test
Point

R1

S1

C

L

(see Note A)

7 V

1.3 V

1.3 V1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

t

h

t

su

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

1.3 V 1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

High-Level

Pulse

Low-Level

Pulse

t

w

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

Out-of-Phase

Output

(see Note C)

1.3 V 1.3 V

1.3 V1.3 V

1.3 V 1.3 V

1.3 V1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

V

OL

V

OH

V

OH

V

OL

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

[

0 V

V

OH

V

OL

[

3.5 V

In-Phase

Output

0.3 V

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

R2

V

CC

R

L

Test
Point

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

From Output

Under Test

Test
Point

C

L

(see Note A)

R

L

RL = R1 = R2

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

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