Datasheet SN54ALS1244AJ, SN74ALS1244ADW, SN74ALS1244ADWR, SN74ALS1244AN, SNJ54ALS1244AFK Datasheet (Texas Instruments)

SN54ALS1244A, SN74ALS1244A
OCTAL BUFFERS AND DRIVERS

WITH 3-STATE OUTPUTS

SDAS186B – JULY 1990 – REVISED JANUAR Y 1995

• Low-Power Versions of ′ALS244 Series

• 3-State Outputs Drive Bus Lines or Buffer

Memory Address Registers

• pnp Inputs Reduce dc Loading

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs

description

These octal buffers and drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.

Taken together with the SN74ALS1240, these
devices provide the choice of inverting and
noninverting outputs.

The SN54ALS1244A is characterized for
operation over the full military temperature range
of –55°C to 125°C. The SN74ALS1244A is
characterized for operation from 0°C to 70°C.

SN54ALS1244A ...J PACKAGE

SN74ALS1244A . . . DW OR N PACKAGE

SN54ALS1244A . . . FK PACKAGE

1A2
2Y3
1A3
2Y2
1A4

(TOP VIEW)

1OE

1

1A1

2

2Y4

3

1A2

4

2Y3

5

1A3

6

2Y2

7

1A4

8
9

2Y1

GND

10

(TOP VIEW)

2Y4

3 2 1 20 19

4
5
6
7
8

910111213

1A1

20
19
18
17
16
15
14
13
12
11

V

1OE

CC

V
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1

18
17
16
15
14

CC

1Y1
2A4
1Y2
2A3
1Y3

2Y1

GND

2A1

1Y4

2A2 2OE

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1995, Texas Instruments Incorporated

1

SN54ALS1244A, SN74ALS1244A
OCTAL BUFFERS AND DRIVERS
WITH 3-STATE OUTPUTS

SDAS186B – JULY 1990 – REVISED JANUAR Y 1995

1

2
4
6
8

19

11
13
15
17

†

EN

EN

logic symbol

1OE

1A1
1A2
1A3
1A4

2OE

2A1
2A2
2A3
2A4

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.

18
16
14
12

logic diagram (positive logic)

1A1

1A2

1A3

1A4

2A1

2A2

1

2

4

6

8

19

11

13

18

16

14

12

1Y1

1Y2

1Y3

1Y4

9

2Y1

7

2Y2

1OE

1Y1
1Y2
1Y3
1Y4

9

2Y1

7

2Y2

5

2Y3

3

2Y4

2OE

2A3

2A4

15

17

5

2Y3

3

2Y4

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V
Input voltage, V

Voltage applied to a disabled 3-state output 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

: SN54ALS1244A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . .

A

SN74ALS1244A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

2

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SN54ALS1244A, SN74ALS1244A

UNIT

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

V

V

V

OCTAL BUFFERS AND DRIVERS

WITH 3-STATE OUTPUTS

SDAS186B – JULY 1990 – REVISED JANUAR Y 1995

recommended operating conditions

SN54ALS1244A SN74ALS1244A

MIN NOM MAX MIN NOM MAX

V

CC

V

IH

V

IL

I

OH

I

OL

T

A

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.7 0.8 V
High-level output current –12 –15 mA
Low-level output current 8 16 mA
Operating free-air temperature –55 125 0 70 °C

SN54ALS1244A SN74ALS1244A

MIN TYP†MAX MIN TYP†MAX

V

IK

OH

OL

I

OZH

I

OZL

I

I

I

IH

I

IL

I

O

I

CC

‡

VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2

IOH = –3 mA 2.4 3.2 2.4 3.2

VCC = 4.5 V

= 4.5

CC

VCC = 5.5 V, VO = 2.7 V 20 20 µA
VCC = 5.5 V, VO = 0.4 V –20 –20 µA
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.4 V –0.1 –0.1 mA
VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA

VCC = 5.5 V

IOH = –12 mA 2
IOH = –15 mA 2
IOL = 8 mA 0.25 0.4 0.25 0.4
IOL = 16 mA 0.35 0.5

Outputs high 6 15 6 11
Outputs low 10 20 10 17
Outputs disabled 11 25 11 20

mA

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3

SN54ALS1244A, SN74ALS1244A

A

Y

ns

OE

Y

ns

OE

Y

ns

OCTAL BUFFERS AND DRIVERS
WITH 3-STATE OUTPUTS

SDAS186B – JULY 1990 – REVISED JANUAR Y 1995

switching characteristics (see Figure 1)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,

PARAMETER

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

PLZ

FROM

(INPUT)

TO

(OUTPUT)

R1 = 500 Ω
R2 = 500 Ω,
TA = MIN to MAX

SN54ALS1244A SN74ALS1244A

MIN MAX MIN MAX

3 21 3 14
3 16 3 14
6 28 6 22
6 26 6 22
2 15 2 13
3 25 3 16

,

†

UNIT

4

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From Output

Under Test

(see Note A)

SN54ALS1244A, SN74ALS1244A
OCTAL BUFFERS AND DRIVERS

WITH 3-STATE OUTPUTS

SDAS186B – JULY 1990 – REVISED JANUAR Y 1995

PARAMETER MEASUREMENT INFORMATION

SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

7 V

V

CC

S1

R

L

Test
Point

C

L

R

L

From Output

Under Test

C

(see Note A)

Test
Point

L

From Output

Under Test

(see Note A)

R1

C

L

RL = R1 = R2

Test
Point

R2

LOAD CIRCUIT FOR

BI-STATE

TOTEM-POLE OUTPUTS

Timing

Input

t

su

Data

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

t

PZL

t

PZH

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

1.3 V

t

PHZ

1.3 V

1.3 V

t

1.3 V1.3 V

1.3 V1.3 V

FOR OPEN-COLLECTOR OUTPUTS

h

t

PLZ

LOAD CIRCUIT

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

[

3.5 V

V

OL

0.3 V

V

OH

0.3 V

[

0 V

High-Level

Low-Level

Out-of-Phase

(see Note C)

Pulse

Pulse

Input

In-Phase

Output

Output

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

1.3 V 1.3 V

t

w

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.3 V 1.3 V

t

PLH

t

PHL

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

1.3 V1.3 V

t

PHL

t

PLH

3.5 V

0.3 V

3.5 V

0.3 V

3.5 V

0.3 V

V

V

V

V

OH

OL

OH

OL

NOTES: A. CL includes probe and jig capacitance.

B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

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5

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Copyright  1998, Texas Instruments Incorporated