SN54ALS112A, SN74ALS112A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS199A – APRIL 1982 – REVISED DECEMBER 1994
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• Fully Buffered to Offer Maximum Isolation
From External Disturbance
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
TYPE
TYPICAL MAXIMUM
CLOCK
FREQUENCY
(MHz)
TYPICAL POWER
DISSIPATION
PER FLIP-FLOP
(mW)
′ALS112A 50 6
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE
) or clear (CLR) inputs sets or
resets the outputs, regardless of the levels of the
other inputs. When PRE
and CLR are inactive
(high), data at the J and K inputs meeting the
setup-time requirements is transferred to the
outputs on the negative-going edge of the clock
pulse (CLK). Clock triggering occurs at a voltage
level and is not directly related to the fall time of the
clock pulse. Following the hold-time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by tying
J and K high.
The SN54ALS112A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ALS112A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE CLR CLK J K Q Q
L H X X X H L
H LXXXLH
LLXXXH
†
H
†
HH↓LLQ
0
Q
0
HH↓HLHL
HH↓LHLH
HH↓H H Toggle
H H H X X Q
0
Q
0
†
The output levels in this configuration may not meet the
minimum levels for VOH. Furthermore, this configuration is
nonstable; that is, it does not persist when either PRE
or
CLR
returns to its inactive (high) level.
SN54ALS112A ...J PACKAGE
SN74ALS112A ...D OR N PACKAGE
(TOP VIEW)
SN54ALS112A . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2CLR
2CLK
NC
2K
2J
1J
1PRE
NC
1Q
1Q
1CLK2QV
1CLR
2Q
CC
GND
NC
2PRE
1K
NC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54ALS112A, SN74ALS112A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS199A – APRIL 1982 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
S
4
1J
3
1J
1K
2
1K
R
15
1Q
5
6
C1
1PRE
1CLR
1Q
1
1CLK
10
11
2J
12
2K
14
2Q
9
7
2PRE
2CLR
2Q
13
2CLK
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
PRE
CLK
K
Q Q
CLR
J
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: SN54ALS112A –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALS112A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SN54ALS112A, SN74ALS112A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS199A – APRIL 1982 – REVISED DECEMBER 1994
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
SN54ALS112A SN74ALS112A
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.7 0.8 V
I
OH
High-level output current –0.4 –0.4 mA
I
OL
Low-level output current 4 8 mA
f
clock
Clock frequency 0 25 0 30 MHz
PRE or CLR low 15 10
t
w
Pulse duration
CLK high
20 16.5
ns
CLK low 20 16.5
Data 25 22
t
su
S
etup time before
CLK↓
PRE or CLR inactive 22 20
ns
t
h
Hold time after CLK↓ Data 0 0 ns
T
A
Operating free-air temperature –55 125 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS112A SN74ALS112A
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
V
OH
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 VCC–2 V
IOL = 4 mA 0.25 0.4 0.25 0.4
VOLV
CC
= 4.5
V
IOL = 8 mA 0.35 0.5
V
J, K, or CLK
0.1 0.1
I
I
PRE or CLR
V
CC
=
5.5 V
,
V
I
=
7 V
0.2 0.2
mA
J, K, or CLK
20 20
I
IH
PRE or CLR
V
CC
= 5.5 V,
V
I
= 2.7
V
40 40
µ
A
J, K, or CLK
–0.2 –0.2
I
IL
PRE or CLR
V
CC
= 5.5 V,
V
I
= 0.4
V
–0.4 –0.4
mA
I
O
‡
VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
I
CC
VCC = 5.5 V, See Note 1 2.5 4.5 2.5 4.5 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with J, K, CLK, and PRE
grounded, then with J, K, CLK, and CLR grounded.
SN54ALS112A, SN74ALS112A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS199A – APRIL 1982 – REVISED DECEMBER 1994
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics (see Figure 1)
PARAMETER
FROM
(
INPUT
)
TO
(
OUTPUT
)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω,
TA = MIN to MAX
†
UNIT
(INPUT)
(OUTPUT)
SN54ALS112A SN74ALS112A
MIN MAX MIN MAX
f
max
25 30 MHz
t
PLH
3 26 3 15
t
PHL
PRE
or
CLR
Q
or
Q
4 23 4 18
ns
t
PLH
3 23 3 15
t
PHL
CLK
Q
or
Q
5 24 5 19
ns
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN54ALS112A, SN74ALS112A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SDAS199A – APRIL 1982 – REVISED DECEMBER 1994
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
t
PHZ
t
PLZ
t
PHL
t
PLH
0.3 V
t
PZL
t
PZH
t
PLH
t
PHL
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
From Output
Under Test
Test
Point
R1
S1
C
L
(see Note A)
7 V
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Out-of-Phase
Output
(see Note C)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
V
OL
V
OH
V
OH
V
OL
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
[
0 V
V
OH
V
OL
[
3.5 V
In-Phase
Output
0.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
R2
V
CC
R
L
Test
Point
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
From Output
Under Test
Test
Point
C
L
(see Note A)
R
L
RL = R1 = R2
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 1998, Texas Instruments Incorporated
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