Texas Instruments SN74AHCT138DBR, SN74AHCT138DGVR, SN74AHCT138DR, SN74AHCT138N, SN74AHCT138PWLE Datasheet

SN54AHCT138, SN74AHCT138

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS266J – DECEMBER 1995 – REVISED JANUARY 2000

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Inputs Are TTL-Voltage Compatible

D

Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems

D

Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs

description

The ’AHCT138 3-line to 8-line decoders/
demultiplexers are designed to be used in
high-performance memory-decoding and
data-routing applications that require very short
propagation-delay times. In high-performance
memory systems, this decoder can be used to
minimize the effects of system decoding. When
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this decoder
and the enable time of the memory usually are
less than the typical access time of the memory.
This means that the effective system delay
introduced by the decoder is negligible.

SN54AHCT138 ...J OR W PACKAGE

SN74AHCT138 . . . D, DB, DGV, N, OR PW PACKAGE

SN54AHCT138 . . . FK PACKAGE

C

G

2A

NC

G

2B

G1

NC – No internal connection

(TOP VIEW)

A

1
2

B

3

C

4

G

2A

5

G

2B

6

G1

7

Y7

GND

8

(TOP VIEW)

BANC

3212019

4
5
6
7
8

910111213

Y7

GND

16
15
14
13
12
11
10

NC

9

V

CC

Y6

V
Y0
Y1
Y2
Y3
Y4
Y5
Y6

Y0

18
17
16
15
14

Y5

CC

Y1
Y2
NC
Y3
Y4

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.

The SN54AHCT138 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT138 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

SN54AHCT138, SN74AHCT138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS266J – DECEMBER 1995 – REVISED JANUARY 2000

FUNCTION TABLE

ENABLE INPUTS

G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X H X X X X H H H H H H H H
X XHXXXHHHHHHHH
L XXXXXHHHHHHHH
H LLLLLLHHHHHHH
H LLLLHHLHHHHHH
H LLLHLHHLHHHHH
H LLLHHHHHLHHHH
H LLHLLHHHHLHHH
H LLHLHHHHHHLHH
H LLHHLHHHHHHLH
H L L H H H H H H H H H H L

SELECT INPUTS OUTPUTS

logic symbols (alternatives)

1

A

2

B

3

C

6

G1

4

G

2A

5

G2B

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.

BIN/OCT

1
2
4

&

EN

†

15

0
1
2
3
4
5
6
7

14
13
12
11
10

Y0
Y1
Y2
Y3
Y4
Y5

9

Y6

7

Y7

G1
G2A
G2B

1

A

2

B

3

C

6
4

5

DMUX

0

G

2

&

0

0

1

7

2
3
4
5
6
7

15
14
13
12
11
10

Y0
Y1
Y2
Y3
Y4
Y5

9

Y6

7

Y7

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1

A

Select
Inputs

2

B

3

C

SN54AHCT138, SN74AHCT138

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS266J – DECEMBER 1995 – REVISED JANUARY 2000

15

Y0

14

Y1

13

Y2

12

Y3

Data

11

10

Y4

Y5

9

Y6

Outputs

4

G2A

Enable

Inputs

Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.

G2B

G1

5
6

7

Y7

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I

(see Note 1) –0.5 V to V

O

(V

< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

OK

< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(V

= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

O

Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54AHCT138, SN74AHCT138

UNIT

PARAMETER

TEST CONDITIONS

V

UNIT

V

4.5 V

V

V

4.5 V

V

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS266J – DECEMBER 1995 – REVISED JANUARY 2000

recommended operating conditions (see Note 3)

SN54AHCT138 SN74AHCT138

MIN MAX MIN MAX

V
V
V
V
V
I

OH

I

OL

∆t/∆v Input transition rise or fall rate 20 20 ns/V
T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
†

This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.

Supply voltage 4.5 5.5 4.5 5.5 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

High-level output current –8 –8 mA
Low-level output current 8 8 mA

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

IOH = –50 mA
IOH = –8 mA
IOL = 50 mA
IOL = 8 mA
VI = VCC or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VCC or GND, IO = 0 5.5 V 4 40 40
One input at 3.4 V ,

†

Other inputs at VCC or GND
VI = VCC or GND 5 V 2 10 10 pF

I
I

∆I
C

OH

OL

I
CC

CC

i

, literature number SCBA004.

CC

5.5 V 1.35 1.5 1.5 mA

TA = 25°C SN54AHCT138 SN74AHCT138

MIN TYP MAX MIN MAX MIN MAX

4.4 4.5 4.4 4.4

3.94 3.8 3.8

0.1 0.1 0.1

0.36 0.5 0.44

CC

0 V

CC

V

m

A

m

A

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

UNIT

A, B, C

Any Y

C

15 pF

ns

G1

Any Y

C

15 pF

ns

G2A, G2B

Any Y

C

pF

ns

A, B, C

Any Y

C

50 pF

ns

G1

Any Y

C

50 pF

ns

G2A, G2B

Any Y

C

pF

ns

SN54AHCT138, SN74AHCT138

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS266J – DECEMBER 1995 – REVISED JANUARY 2000

switching characteristics over recommended operating free-air temperature range,
V

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

*

On products compliant to MIL-PRF-38535, this parameter is not production tested.

=

L

=

L

= 15

L

=

L

=

L

= 50

L

p

p

p

p

p

p

TA = 25°C SN54AHCT138 SN74AHCT138

MIN TYP MAX MIN MAX MIN MAX

7.6* 10.4* 1* 12* 1 12

7.6* 10.4* 1* 12* 1 12

6.6* 9.1* 1* 10.5* 1 10.5

6.6* 9.1* 1* 10.5* 1 10.5
7* 9.6* 1* 11* 1 11
7* 9.6* 1* 11* 1 11

8.1 11.4 1 13 1 13

8.1 11.4 1 13 1 13

7.1 10.1 1 11.5 1 11.5

7.1 10.1 1 11.5 1 11.5

7.5 10.6 1 12 1 12

7.5 10.6 1 12 1 12

operating characteristics, V

C

Power dissipation capacitance No load, f = 1 MHz 14 pF

pd

= 5 V, T

CC

PARAMETER TEST CONDITIONS TYP UNIT

= 25°C

A

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54AHCT138, SN74AHCT138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS266J – DECEMBER 1995 – REVISED JANUARY 2000

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

(see Note A)

Test
Point

C

L

From Output

Under Test

(see Note A)

C

L

RL = 1 kΩ

S1

V

CC

GND

Open

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open Drain

Open

V

CC

GND
V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

t

w

Input

Input

In-Phase

Output

Out-of-Phase

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

50% V

t

PHL

50% V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

3-STATE AND OPEN-DRAIN OUTPUTS

CC

CC

LOAD CIRCUIT FOR

3 V

0 V

3 V

0 V

t

PHL

V

t

PLH

CC

CC

OH

V

OL

V

OH

V

OL

50% V

50% V

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at V

(see Note B)

Waveform 2

(see Note B)

CC

Output

S1 at GND

1.5 V

t

CC

CC

h

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V1.5 V 1.5 V

t

PZL

50% V

t

PZH

50% V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

3 V

0 V

3 V

0 V

3 V

0 V

≈V

V

OL

V

OH

≈0 V

CC

Figure 1. Load Circuit and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AHCT138, SN74AHCT138

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS266J – DECEMBER 1995 – REVISED JANUARY 2000

APPLICATION INFORMATION

SN74AHCT138

A0
A1
A2

A3
A4

1
2

3

V

CC

6
4
5

1
2

3

6
4
5

BIN/OCT

1
2

4

&

EN

SN74AHCT138

BIN/OCT

1
2

4

&

EN

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

15
14
13
12
11
10

15
14
13
12
11
10

0
1
2
3
4
5

9

6

7

7

8
9
10
11
12
13

9

14

7

15

SN74AHCT138

1
2

3

6
4
5

BIN/OCT

1
2

4

&

Figure 2. 24-Bit Decoding Scheme

EN

15

0
1
2
3
4
5
6
7

14
13
12
11
10

16
17
18
19
20
21

9

22

7

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN54AHCT138, SN74AHCT138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS266J – DECEMBER 1995 – REVISED JANUARY 2000

APPLICATION INFORMATION

A0
A1
A2

V

CC

A3
A4

1
2

3

6
4
5

1
2

3

6
4
5

SN74AHCT138

BIN/OCT

1
2

4

&

EN

SN74AHCT138

BIN/OCT

1
2

4

&

EN

15

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

14
13
12
11
10

15
14
13
12
11
10

0
1
2
3
4
5

9

6

7

7

8
9
10
11
12
13

9

14

7

15

SN74AHCT138

1
2

3

6
4
5

1
2

3

6
4
5

BIN/OCT

1
2

4

&

EN

SN74AHCT138

BIN/OCT

1
2

4

&

EN

0
1
2
3
4
5
6
7

0
1
2
3
4
5
6
7

15
14
13
12
11
10

15
14
13
12
11
10

16
17
18
19
20
21

9

22

7

23

24
25
26
27
28
29

9

30

7

31

Figure 3. 32-Bit Decoding Scheme

8

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Copyright  2000, Texas Instruments Incorporated