Texas Instruments SN74AHC273DBLE, SN74AHC273DBR, SN74AHC273DGVR, SN74AHC273DW, SN74AHC273DWR Datasheet
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SN54AHC273, SN74AHC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS376E – JUNE 1997 – REVISED JANUARY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Operating Range 2-V to 5.5-V V
CC
D
Contain Eight Flip-Flops With Single-Rail
Outputs
D
Direct Clear Input
D
Individual Data Input to Each Flip-Flop
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
description
These circuits are positive-edge-triggered D-type
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
Q outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going pulse.
When CLK is at either the high or low level, the
D input has no effect at the output.
The SN54AHC273 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHC273 is characterized for operation from –40°C to 85 °C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
CLR
CLK D
OUTPUT
Q
L X X L
H ↑ HH
H ↑ LL
H L X Q
0
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
SN54AHC273 ...J OR W PACKAGE
SN74AHC273 . .. DB, DGV, DW, N, OR PW PACKAGE
(TOP VIEW)
SN54AHC273 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
2Q
3Q
3D
4D
1D1QCLR
5Q
5D
8Q
4Q
GND
CLK
V
CC
8D
7D
7Q
6Q
6D
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54AHC273, SN74AHC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS376E – JUNE 1997 – REVISED JANUARY 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
1D
3
1D
4
2D
7
3D
R
1
1Q
2
2Q
5
3Q
6
8
4D
13
5D
14
6D
4Q
9
5Q
12
6Q
15
CLR
17
7D
18
8D
11
CLK
7Q
16
8Q
19
C1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
CLK
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D
5Q
6D
6Q
7D
7Q
8D
8Q
CLR
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
3 4 7 8 13 14 17 18
2 5 6 9 12 15 16 19
11
1
logic diagram, each flip-flop (positive logic)
CLK(I)
R
Q
C
C
D
C
C
C
C
C
C
TG
C
C
TG
TG
TG
SN54AHC273, SN74AHC273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS376E – JUNE 1997 – REVISED JANUARY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Note 1) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHC273 SN74AHC273
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
V
IH
High-level input voltage
VCC = 3 V
2.1 2.1
V
VCC = 5.5 V 3.85 3.85
VCC = 2 V 0.5 0.5
V
IL
Low-level input voltage
VCC = 3 V
0.9 0.9
V
VCC = 5.5 V 1.65 1.65
V
I
Input voltage 0 5.5 0 5.5 V
V
O
Output voltage 0 V
CC
0 V
CC
V
VCC = 2 V –50 –50
m
A
I
OH
High-level output current
VCC = 3.3 V ± 0.3 V
–4 –4
VCC = 5 V ± 0.5 V –8 –8
mA
VCC = 2 V 50 50
m
A
I
OL
Low-level output current
VCC = 3.3 V ± 0.3 V
4 4
VCC = 5 V ± 0.5 V 8 8
mA
p
VCC = 3.3 V ± 0.3 V 100 100
∆t/∆vInput transition rise or fall rate
VCC = 5 V ± 0.5 V 20 20
ns/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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