Texas Instruments SNJ54ACT16374WD Datasheet
SN54ACT16374, 74ACT16374
16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS124B – MARCH 1990 – REVISED APRIL 1996
D
Members of the Texas Instruments
Widebus
D
Inputs Are TTL-Voltage Compatible
D
3-State Bus-Driving True Outputs
D
Flow-Through Architecture Optimizes
t
Family
PCB Layout
D
Distributed Center-Pin VCC and GND
Configurations Minimize High-Speed
Switching Noise
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-mm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The SN54ACT16374 and 74ACT16374 are 16-bit
edge-triggered D-type flip-flops with 3-state
outputs designed specifically for driving
highly-capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
SN54ACT16374 . . . WD PACKAGE
74ACT16374 . . . DL PACKAGE
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
An output-enable input (OE
) can be used to place the outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system
without need for interface or pullup components. OE
does not affect the internal operations of the flip-flop. Old
data can be retained or new data can be entered while the outputs are in the high-impedance state.
The 74ACT16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit board area.
The SN54ACT16374 is characterized for operation over the full military temperature range of –55°C to 125°C.
The 74ACT16374 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ACT16374, 74ACT16374
16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS124B – MARCH 1990 – REVISED APRIL 1996
FUNCTION TABLE
(each section)
INPUTS
OE CLK D
L ↑ H H
L ↑ LL
L H or L X Q
H X X Z
OUTPUT
Q
0
logic symbol
†
1
1OE
1CLK
2OE
2CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
EN2
EN4
1D
3D
C1
C3
2
11
12
13
14
16
17
19
20
22
23
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
logic diagram (positive logic)
SN54ACT16374, 74ACT16374
16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS124B – MARCH 1990 – REVISED APRIL 1996
1OE
1CLK
1D1
1
48
47
C1
1D
To Seven Other Channels
2CLK
1Q1
2OE
2D1
24
25
36
C1
1D
To Seven Other Channels
132
2Q1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
CC
(see Note 1) –0.5 V to VCC+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Output voltage range, VO (see Note 1) –0.5 V to VCC+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
(V
< 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(V
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DL package 1.2 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
stg
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
recommended operating conditions (see Note 3)
SN54ACT16374 74ACT16374
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
I
OH
I
OL
Dt/D
T
NOTES: 3. Unused inputs must be held high or low to prevent them from floating.
Supply voltage (see Note 4) 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA
Low-level output current 24 24 mA
v Input transition rise or fall rate 0 10 0 10 ns/V
Operating free-air temperature –55 125 –40 85 °C
A
4. All VCC and GND pins must be connected to the proper voltage supply.
CC
CC
0 V
0 V
CC
CC
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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