Texas Instruments SN74AC574DBLE, SN74AC574DBR, SN74AC574DW, SN74AC574DWR, SN74AC574N Datasheet
...
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
D
3-State Outputs Drive Bus Lines Directly
D
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic
Small-Outline (DW) Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flatpacks (W), and Standard Plastic (N) and
Ceramic (J) DIP Packages
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ′AC574 are D-type
edge-triggered flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set
to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE
to place the eight outputs in either a normal logic
state (high or low logic levels) or the highimpedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines
significantly. The high-impedance state and the
increased drive provide the capability to drive bus
lines in a bus-organized system without need for
interface or pullup components.
) input can be used
SN54AC574 ...J OR W PACKAGE
SN74AC574 . . . DB, DW, N, OR PW PACKAGE
SN54AC574 . . . FK PACKAGE
3D
4D
5D
6D
7D
(TOP VIEW)
1
OE
2
1D
3
2D
4
3D
5
4D
6
5D
7
6D
8
7D
9
8D
GND
10
(TOP VIEW)
2D1DOE
3 2 1 20 19
4
5
6
7
8
910111213
8D
GND
20
19
18
17
16
15
14
13
12
11
CLK
V
8Q
CC
V
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
1Q
18
17
16
15
14
7Q
CC
2Q
3Q
4Q
5Q
6Q
OE
does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54AC574 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74AC574 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
INPUTS
OE CLK D
L ↑ H H
L ↑ LL
L H or L X Q
H X X Z
OUTPUT
Q
0
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54AC574, SN74AC574
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS541B – OCTOBER 1995 – REVISED JUNE 1996
logic symbol
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
†
1
11
2
3
4
5
6
7
8
9
EN
1D
C1
19
18
17
16
15
14
13
12
logic diagram (positive logic)
1
OE
11
CLK
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2
To Seven Other Channels
1D
C1
19
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Input clamp current, IIK (VI < 0 or VI > V
Output clamp current, IOK (VO < 0 or VO > V
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
Storage temperature range, T
(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
= 55°C (in still air) (see Note 2): DB package 0.6 W. . . . . . . . . . . . . . . . . .
A
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC)
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC)
DW package 1.6 W. . . . . . . . . . . . . . . . .
N package 1.3 W. . . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
1Q
‡
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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