Texas Instruments SNJ54ABT8652FK, SNJ54ABT8652JT Datasheet

SN54ABT8652, SN74ABT8652

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

SCOPE

 Family of Testability Products

D

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture

D

Functionally Equivalent to ’F652 and
’ABT652 in the Normal-Function Mode

D

SCOPE

 Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,
and HIGHZ

– Parallel-Signature Analysis at Inputs

With Masking Option

– Pseudo-Random Pattern Generation

From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Even-Parity Opcodes

D

Two Boundary-Scan Cells Per I/O for
Greater Flexibility

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Package Options Include Shrink
Small-Outline (DL) and Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Ceramic
DIPs (JT)

description

The ’ABT8652 scan test devices with octal bus
transceivers and registers are members of the
Texas Instruments SCOPE testability
integrated-circuit family. This family of devices
supports IEEE Standard 1149.1-1990 boundary
scan to facilitate testing of complex circuit-board
assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port
(T AP) interface.

In the normal mode, these devices are functionally equivalent to the ’F652 and ’ABT652 octal bus transceivers
and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing
at the device pins or to perform a self test on the boundary-test cells. Activating the T AP in normal mode does
not affect the functional operation of the SCOPE octal bus transceivers and registers.

Copyright  1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

CLKAB

SAB

OEAB

A1
A2
A3

GND

A4
A5
A6
A7

A8
TDO
TMS

CLKBA
SBA
OEBA
B1
B2
B3
B4
V

CC

B5
B6
B7
B8
TDI
TCK

321

13 14

5
6
7
8
9
10
11

B7
B8
TDI
TCK
TMS
TDO
A8

OEBA

SBA
CLKBA
CLKAB

SAB

OEAB

A1

4

15 16 17 18

A3

GND

A4A5A6

A7

B1B2B3

B4

28 27 26

25
24
23
22
21
20
19

12

A2

VB5B6

CC

SN54ABT8652 . . . JT PACKAGE

SN74ABT8652 . . . DL OR DW PACKAGE

(TOP VIEW)

SN54ABT8652 . . . FK PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

SN54ABT8652, SN74ABT8652
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and
output-enable (OEAB and OEBA) inputs. For A-to-B data flow, data on the A bus is clocked into the associated
registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation
to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus
(registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the
high-impedance state. Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA,
and OEBA

inputs. Since the OEBA input is active low, the A outputs are active when OEBA is low and are in

the high-impedance state when OEBA

is high. Figure 1 shows the four fundamental bus-management functions

that can be performed with the ’ABT8652.
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO),
test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions
such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from
data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8652 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT8652 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

DATA I/O

OEAB OEBA CLKAB CLKBA SAB SBA A1–A8 B1–B8

OPERATION OR FUNCTION

L H X X X X Input disabled Input disabled Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ L X X Input Unspecified

†

Store A, hold B

H H ↑↑X

‡

X Input Output Store A in both registers

L X L ↑ X X Unspecified

†

Input Hold A, store B
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X X X H Output Input Stored B data to A bus

H H X X L X Input Output Real-time A data to B bus
H H X X H X Input Output Stored A data to B bus

H L L L H H Output Output

Stored A data to B bus and

stored B data to A bus

†

The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA

. Data-input functions are always

enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

‡

Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered in order to load both registers.

SN54ABT8652, SN74ABT8652

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

REAL-TIME TRANSFER

BUS B TO BUS A

REAL-TIME TRANSFER

BUS A TO BUS B

STORAGE FROM
A, B, OR A AND B

TRANSFER STORED DATA

TO A AND/OR B

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OEAB

3

X
L
L

OEAB

3

L

26

L

1

CLKAB

X

28

CLKBA

X

2

SAB

X

27

SBA

L

1

CLKAB

X

28

CLKBA

X

2

SAB

L

27

SBA

X

26

H

1

CLKAB28CLKBA

X

2

SAB

X

27

SBA

X

1

CLKAB28CLKBA2SAB27SBA

X
H

XX

X

X
X

HL X HH

↑

↑
↑↑

OEBA

OEBA

3

H

26

H

OEAB OEBA

326

OEAB OEBA

X

Pin numbers shown are for the DL, DW, and JT packages.

Figure 1. Bus-Management Functions

SN54ABT8652, SN74ABT8652
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Boundary-Control

Register

Bypass Register

Boundary-Scan Register

Instruction Register

TDI

TMS

TCK

TD

O

TAP

Controller

V

CC

V

CC

One of Eight Channels

OEAB

OEBA

CLKBA

SBA

CLKAB

SAB

A1

B1

1D

C1

1D

C1

25

13

3

26

28

27

1

2

4

16

14

15

Pin numbers shown are for the DL, DW, and JT packages.

SN54ABT8652, SN74ABT8652

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

DESCRIPTION

A1–A8 Normal-function A-bus I/O ports. See function table for normal-mode logic.
B1–B8 Normal-function B-bus I/O ports. See function table for normal-mode logic.

CLKAB, CLKBA Normal-function clock inputs. See function table for normal-mode logic.

GND Ground

OEAB, OEBA Normal-function output-enable inputs. See function table for normal-mode logic.

SAB, SBA Normal-function select inputs. See function table for normal-mode logic.

TCK

T est clock. One of four terminals required by IEEE Standard 1 149.1-1990. Test operations of the device are synchronous
to TCK. Data is captured on the rising edge of TCK, and outputs change on the falling edge of TCK.

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data
through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

TDO

T est data output. One of four terminals required by IEEE Standard 1 149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.

TMS

T est mode select. One of four terminals required by IEEE Standard 1 149.1-1990. TMS directs the device through its T AP
controller states. An internal pullup forces TMS to a high level if left unconnected.

V

CC

Supply voltage

SN54ABT8652, SN74ABT8652
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard
1 149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 2 shows the TAP-controller state diagram.

The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the T AP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and three test-data registers: a 38-bit boundary-scan register, an
11-bit boundary-control register, and a 1-bit bypass register.

Test-Logic-Reset

Run-Test/Idle Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Update-DR

TMS = L

TMS = L

TMS = H

TMS = L

TMS = H

TMS = H

TMS = LTMS = H

TMS = L

TMS = L

TMS = H

TMS = L

Exit2-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Update-IR

TMS = L

TMS = L

TMS = H

TMS = L

TMS = H

TMS = H

TMS = LTMS = H

TMS = L

Exit2-IR

TMS = L

TMS = H TMS = H

TMS = H

TMS = L

TMS = H

TMS = L

TMS = HTMS = H

TMS = H

TMS = L

Figure 2. TAP-Controller State Diagram

SN54ABT8652, SN74ABT8652

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

state diagram description

The TAP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 2 is in accordance with IEEE Standard 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.

As shown, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the T AP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data
registers also can be reset to their power-up values.

The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected
or if a board defect causes it to be open circuited.

For the ’ABT8652, the instruction register is reset to the binary value 11111111, which selects the BYPASS
instruction. Each bit in the boundary-scan register is reset to logic 0 except bit 36, which is reset to logic 1. The
boundary-control register is reset to the binary value 00000000010, which selects the PSA test operation with
no input masking.

Run-T est/Idle

The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

SN54ABT8652, SN74ABT8652
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, then such update
occurs on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the T AP controller exits the Capture-IR state. For the ’ABT8652, the status
value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction register scan. It is possible to return
to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling
edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely . The Pause-IR state suspends and resumes instruction register scan operations without loss of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.