Texas Instruments SNJ54ABT8646FK, SNJ54ABT8646JT Datasheet
SN54ABT8646, SN74ABT8646
SCAN TEST DEVICES WITH
OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS123E – AUGUST 1992 – REVISED JUL Y 1996
D
Members of the Texas Instruments
SCOPE
D
Compatible With the IEEE Standard
Family of Testability Products
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
D
Functionally Equivalent to ’F646 and
’ABT646 in the Normal-Function Mode
D
SCOPE
Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
– Parallel-Signature Analysis at Inputs
With Masking Option
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Even-Parity Opcodes
D
Two Boundary-Scan Cells Per I/O for
Greater Flexibility
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DL) Packages, Ceramic Chip
Carriers (FK), and Standard Ceramic DIPs
(JT)
description
The ’ABT8646 and scan test devices with octal
bus transceivers and registers are members of the
Texas Instruments SCOPE testability
integrated-circuit family. This family of devices
supports IEEE Standard 1149.1-1990 boundary
scan to facilitate testing of complex circuit-board
assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port
(TAP) interface.
SN54ABT8646 . . . JT PACKAGE
SN74ABT8646 . . . DL OR DW PACKAGE
CLKAB
SN54ABT8646 . . . FK PACKAGE
OE
SBA
CLKBA
CLKAB
SAB
DIR
A1
SAB
DIR
GND
TDO
TMS
5
6
7
8
9
10
11
12
A1
A2
A3
A4
A5
A6
A7
A8
4
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(TOP VIEW)
B1B2B3
321
13 14
A3
A2
GND
CLKBA
28
SBA
27
OE
26
B1
25
B2
24
B3
23
B4
22
V
21
B5
20
B6
19
B7
18
B8
17
TDI
16
TCK
15
CC
B4
VB5B6
28 27 26
15 16 17 18
A4A5A6
CC
A7
25
24
23
22
21
20
19
B7
B8
TDI
TCK
TMS
TDO
A8
In the normal mode, these devices are functionally equivalent to the ’F646 and ’ABT646 octal bus transceivers
and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing
at the device pins or to perform a self test on the boundary-test cells. Activating the T AP in normal mode does
not affect the functional operation of the SCOPE octal bus transceivers and registers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54ABT8646, SN74ABT8646
OPERATION OR FUNCTION
SCAN TEST DEVICES WITH
OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS123E – AUGUST 1992 – REVISED JUL Y 1996
description (continued)
Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the
transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR
is low. When OE
buses.
Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is
clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data
is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for
presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB
and SAB, respectively . Figure 1 shows the four fundamental bus-management functions that can be performed
with the ’ABT8646.
In the test mode, the normal operation of the SCOPE bus transceivers and registers is inhibited and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO),
test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions
such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from
data outputs. All testing and scan operations are synchronized to the TAP interface.
is high, both the A and B outputs are in the high-impedance state, effectively isolating both
The SN54ABT8646 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT8646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
X X ↑ X X X Input Unspecified
X XX ↑ X X Unspecified
H X ↑ ↑ X X Input Input Store A and B data
H X L L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X X X H Output Input disabled Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H X X H X Input disabled Output Stored A data to B bus
†
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at
the bus pins is stored on every low-to-high transition of the clock inputs.
DATA I/O
†
†
Input Store B, A unspecified
Store A, B unspecified
†
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT8646, SN74ABT8646
SCAN TEST DEVICES WITH
OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS123E – AUGUST 1992 – REVISED JUL Y 1996
26
OE
L
BUS A
3
DIR
L
1
CLKAB
REAL-TIME TRANSFER
BUS B TO BUS A
CLKBA
X
28
BUS B
27
2
SAB
X
SBA
X
L
26
OE
BUS A
3
DIR
L
H
1
CLKAB
X
REAL-TIME TRANSFER
BUS A TO BUS B
28
CLKBA
X
2
SAB
L
BUS B
27
SBA
X
BUS A
26
X
X
H
Pin numbers shown are for the DL, DW, and JT packages.
3
DIR
X
X
X
1
CLKAB28CLKBA
↑
XX
STORAGE FROM
A, B, OR A AND B
X
↑
↑↑
2
SAB
X
X
BUS B
SBA
Figure 1. Bus-Management Functions
27
BUS A
26
X
X
X
OEOE
L
LH X XHX
3
DIR
L
TRANSFER STORED DA TA
1
CLKAB
X
TO A AND/OR B
28
CLKBA
X
2
SAB
X
BUS B
27
SBA
H
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABT8646, SN74ABT8646
SCAN TEST DEVICES WITH
OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS123E – AUGUST 1992 – REVISED JUL Y 1996
functional block diagram
Boundary-Scan Register
26
OE
3
DIR
CLKBA
SBA
CLKAB
SAB
A1
28
27
1
2
4
1D
C1
One of Eight Channels
C1
1D
25
B1
V
CC
16
TDI
V
CC
14
TMS
TAP
15
TCK
Pin numbers shown for the DL, DW, and JT packages.
4
Controller
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Bypass Register
Boundary-Control
Register
Instruction Register
13
TDO
SN54ABT8646, SN74ABT8646
SCAN TEST DEVICES WITH
OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS123E – AUGUST 1992 – REVISED JUL Y 1996
Terminal Functions
TERMINAL
NAME
A1–A8 Normal-function A-bus I/O ports. See function table for normal-mode logic.
B1–B8 Normal-function B-bus I/O ports. See function table for normal-mode logic.
CLKAB, CLKBA Normal-function clock inputs. See function table for normal-mode logic.
DIR Normal-function direction-control input. See function table for normal-mode logic.
GND Ground
OE Normal-function output-enable input. See function table for normal-mode logic.
SAB, SBA Normal-function select inputs. See function table for normal-mode logic.
TCK
TDI
TDO
TMS
V
CC
T est clock. One of four terminals required by IEEE Standard 1 149.1-1990. Test operations of the device are synchronous
to TCK. Data is captured on the rising edge of TCK, and outputs change on the falling edge of TCK.
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data
through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
T est data output. One of four terminals required by IEEE Standard 1 149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.
Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS input directs the device through
its TAP controller states. An internal pullup forces TMS to a high level if left unconnected.
Supply voltage
DESCRIPTION
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT8646, SN74ABT8646
SCAN TEST DEVICES WITH
OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS123E – AUGUST 1992 – REVISED JUL Y 1996
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard
1 149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 2 shows the TAP-controller state diagram.
The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the T AP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and three test-data registers: a 40-bit boundary-scan register, an
11-bit boundary-control register, and a 1-bit bypass register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = L
Run-Test/Idle Select-DR-Scan
TMS = L
Capture-DR
TMS = L
Shift-DR
TMS = L
TMS = H
TMS = H
Exit1-DR
TMS = L
Pause-DR
TMS = L
TMS = H
Exit2-DR
TMS = H
TMS = HTMS = H
TMS = H TMS = H
TMS = L
TMS = L
Select-IR-Scan
TMS = H
TMS = L
Capture-IR
TMS = L
Shift-IR
TMS = L
TMS = H
TMS = H
Exit1-IR
TMS = L
Pause-IR
TMS = L
TMS = H
Exit2-IR
TMS = H
Update-DR
TMS = LTMS = H
Update-IR
TMS = LTMS = H
Figure 2. TAP-Controller State Diagram
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT8646, SN74ABT8646
SCAN TEST DEVICES WITH
OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS123E – AUGUST 1992 – REVISED JUL Y 1996
state diagram description
The T AP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 2 is in accordance with IEEE Standard 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.
As shown, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the T AP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the ’ABT8646, the instruction register is reset to the binary value 11111111, which selects the BYPASS
instruction. Each bit in the boundary-scan register is reset to logic 0. The boundary-control register is reset to
the binary value 00000000010, which selects the PSA test operation with no input masking.
Run-Test/Idle
The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle.
The test operations selected by the boundary-control register are performed while the T AP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
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7
SN54ABT8646, SN74ABT8646
SCAN TEST DEVICES WITH
OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS123E – AUGUST 1992 – REVISED JUL Y 1996
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.
On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the
high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, then such update
occurs on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK upon, which the TAP controller exits the Capture-IR state.
For the ’ABT8646, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.
On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the
high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss
of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT8646, SN74ABT8646
SCAN TEST DEVICES WITH
OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS123E – AUGUST 1992 – REVISED JUL Y 1996
register overview
With the exception of the bypass register, any test register can be thought of as a serial-shift register with a
shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the
appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register
can be parallel loaded from a source specified by the current instruction. During the appropriate shift state
(Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted
in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from
the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the three data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
T able 3 lists the instructions supported by the ’ABT8646. The even-parity feature specified for SCOPE devices
is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for
SCOPE devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated,
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 11111111, which selects the BYPASS instruction. The IR of scan is shown in Figure 3.
Bit 7
Parity
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
TDOTDI
Figure 3. Instruction Register Order of Scan
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