Texas Instruments SN74ABT8245DW, SN74ABT8245DWR, SNJ54ABT8245FK, SNJ54ABT8245JT Datasheet

SN54ABT8245, SN74ABT8245

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS

SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996

D

Members of the Texas Instruments

SCOPE

D

Compatible With the IEEE Standard

 Family of Testability Products

1149.1-1990 (JTAG) Test Access Port
and Boundary-Scan Architecture

D

Functionally Equivalent to ’F245 and
’ABT245 in the Normal-Function Mode

D

SCOPE

 Instruction Set:

– IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,
and HIGHZ

– Parallel-Signature Analysis at Inputs

With Masking Option

– Pseudo-Random Pattern Generation

From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Even-Parity Opcodes

D

Two Boundary-Scan Cells per I/O for
Greater Flexibility

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Package Options Include Plastic
Small-Outline Packages (DW), Ceramic
Chip Carriers(FK), and Standard Ceramic
DIPs (JT)

description

The ’ABT8245 scan test devices with octal bus
transceivers are members of the Texas Instru­ments SCOPE testability integrated-circuit
family. This family of devices supports IEEE
Standard 1 149.1-1990 boundary scan to facilitate
testing of complex circuit-board assemblies. Scan
access to the test circuitry is accomplished via the
4-wire test access port (TAP) interface.

SN54ABT8245 . . . JT PACKAGE

SN74ABT8245 . . . DW PACKAGE

SN54ABT8245 . . . FK PACKAGE

A2

A1
OE
NC

DIR

B1

B2

NC – No internal connection

DIR

B1
B2
B3
B4

GND

B5
B6
B7

B8
TDO
TMS

5
6
7
8
9
10
11

12

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12

(TOP VIEW)

A3A4A5

4

321

13 14

B4

B3

24
23
22
21
20
19
18
17
16
15
14
13

CC

NC

VA6A7

28 27 26

15 16 17 18

B5B6B7

NC

GND

OE
A1
A2
A3
A4
A5
V
A6
A7
A8
TDI
TCK

CC

25
24
23
22
21
20
19

A8
TDI
TCK
NC
TMS
TDO
B8

In the normal mode, these devices are functionally equivalent to the ’F245 and ’ABT245 octal bus transceivers.
The test circuitry can be activated by the T AP to take snapshot samples of the data appearing at the device pins
or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the
functional operation of the SCOPE octal bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable (OE

) inputs. Data transmission is
allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. The
output-enable (OE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

) input can be used to disable the device so that the buses are effectively isolated.

Copyright  1996, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

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1

SN54ABT8245, SN74ABT8245

OPERATION

SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS

SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996

description (continued)

In the test mode, the normal operation of the SCOPE  bus transceivers is inhibited and the test circuitry is
enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform
boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO),
test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions
such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from
data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8245 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT8245 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(normal mode)

INPUTS

OE DIR

L L B data to A bus
L H A data to B bus

H X Isolation

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functional block diagram

24

OE

1

DIR

SN54ABT8245, SN74ABT8245

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS

SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996

Boundary-Scan Register

23

A1 B1

One of Eight Channels

Bypass Register

Boundary-Control

Register

V

TDI

TMS

TCK

CC

14

V

CC

12

13

Controller

Instruction Register

TAP

11

2

TDO

Pin numbers shown are for the DW and JT packages.

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3

SN54ABT8245, SN74ABT8245
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS

SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996

Terminal Functions

TERMINAL

NAME

A1–A8 Normal-function A-bus I/O ports. See function table for normal-mode logic.
B1–B8 Normal-function B-bus I/O ports. See function table for normal-mode logic.

DIR Normal-function direction-control input. See function table for normal-mode logic.

GND Ground

OE Normal-function output-enable input. See function table for normal-mode logic.

TCK

TDI

TDO

TMS
V

CC

T est clock. One of four terminals required by IEEE Standard 1 149.1-1990. Test operations of the device are synchronous to TCK.
Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.

T est data input. One of four terminals required by IEEE Standard 1 149.1-1990. TDI is the serial input for shifting data through the
instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

T est data output. One of four terminals required by IEEE Standard 1 149.1-1990. TDO is the serial output for shifting data through
the instruction register or selected data register.

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS input directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected.

Supply voltage

DESCRIPTION

4

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SN54ABT8245, SN74ABT8245

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS

SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard
1 149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures data to be captured is valid for fully
one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the T AP controller, and the test registers. As illustrated,
the device contains an 8-bit instruction register and three test-data registers: a 36-bit boundary-scan register,
an 11-bit boundary-control register, and a 1-bit bypass register.

Test-Logic-Reset

TMS = H

TMS = L

TMS = L

Run-Test/Idle Select-DR-Scan

TMS = L

Capture-DR

TMS = L

Shift-DR

TMS = L

TMS = H

TMS = H

Exit1-DR

TMS = L

Pause-DR

TMS = L

TMS = H

Exit2-DR

TMS = H

TMS = HTMS = H

TMS = H TMS = H

TMS = L

TMS = L

Select-IR-Scan

TMS = H

TMS = L

Capture-IR

TMS = L

Shift-IR

TMS = L

TMS = H

TMS = H

Exit1-IR

TMS = L

Pause-IR

TMS = L

TMS = H

Exit2-IR

TMS = H

Update-DR

TMS = LTMS = H

Figure 1. TAP-Controller State Diagram

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Update-IR

TMS = LTMS = H

5

SN54ABT8245, SN74ABT8245
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS

SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996

state diagram description

The T AP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.

As illustrated, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow
in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for
consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data
registers also can be reset to their power-up values.

The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.

For the ’ABT8245, the instruction register is reset to the binary value 11111111, which selects the BYPASS
instruction. Each bit in the boundary-scan register is reset to logic 0. The boundary-control register is reset to
the binary value 00000000010, which selects the PSA test operation with no input masking.

Run-Test/Idle

The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test
operations. The Run-Test/Idle state can also be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle.

The test operations selected by the boundary-control register are performed while the T AP controller is in the
Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.

Capture-DR

When a data register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the T AP controller exits the Capture-DR
state.

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

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SN54ABT8245, SN74ABT8245

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS

SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states end a data-register scan. It is possible to return to the
Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.

On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance
state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, then such update
occurs on the falling edge of TCK following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state.

For the ’ABT8245, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.

On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance
state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of
data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK following entry to the Update-IR
state.

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7

SN54ABT8245, SN74ABT8245
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS

SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996

register overview

With the exception of the bypass register, any test register can be thought of as a serial-shift register with a
shadow latch on each bit. The bypass register differs in that it contains only a shift register. During the
appropriate capture state (Capture-IR for instruction register, Capture-DR for data registers), the shift register
can be parallel loaded from a source specified by the current instruction. During the appropriate shift state
(Shift-IR or Shift-DR), the contents of the shift register are shifted out from TDO while new contents are shifted
in at TDI. During the appropriate update state (Update-IR or Update-DR), the shadow latches are updated from
the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the three data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

T able 3 lists the instructions supported by the ’ABT8245. The even-parity feature specified for SCOPE devices
is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are defined for
SCOPE devices but are not supported by this device default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated,
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 11111111, which selects the BYPASS instruction.

The IR order of scan is shown in Figure 2.

Bit 7
Parity
(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

(LSB)

TDOTDI

Figure 2. Instruction Register Order of Scan

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