Texas Instruments SNJ54ABT7820GB Datasheet

SN54ABT7820

512 × 18 × 2

STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS303E – AUGUST 1994 – REVISED APRIL 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments
Widebus Family

D

Advanced BiCMOS Technology

D

Released as DSCC SMD (Standard
Microcircuit Drawing) 5962-9650901QXA

D

Independent Asynchronous Inputs and
Outputs

D

Two Separate 512 × 18 FIFOs Buffering
Data in Opposite Directions

D

Programmable Almost-Full/Almost-Empty
Flag

D

Empty, Full, and Half-Full Flags

D

Fast Access Times of 12 ns With a 50-pF
Load and Simultaneous Switching Data
Outputs

D

Packaged in 84-Pin Ceramic Pin Grid
Array

GB PACKAGE

(TOP VIEW)

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description

A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN54ABT7820 is arranged as two 512 × 18-bit FIFOs for high speed and fast access times.
It processes data at rates up to 40 MHz, with access times of 18 ns in a bit-parallel format.

The SN54ABT7820 consists of bus transceiver circuits, two 512 × 18 FIFOs, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enable inputs
GAB and GBA control the transceiver functions. The SAB and SBA control inputs select whether real-time or
stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between stored and real-time data. Figure 1 illustrates the eight
fundamental bus-management functions that can be performed with the SN54ABT7820.

The SN54ABT7820 is characterized for operation over the full military temperature range of –55°C to 125°C.

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Widebus is a trademark of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

SN54ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS303E – AUGUST 1994 – REVISED APRIL 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Assignments

TERMINAL NAME TERMINAL NAME TERMINAL NAME TERMINAL NAME

A1 PENA B11 FULLB F9 NC K2 A11
A2 GBA C1 GND F10 B6 K3 GND
A3 SBA C2 HFA F11 GND K4 V

CC

A4 LDCKA C5 UNCKB G1 A5 K5 GND
A5 V

CC

C6 NC G2 GND K6 A17

A6 V

CC

C7 V

CC

G3 A4 K7 GND

A7 V

CC

C10 HFB G9 B4 K8 V

CC

A8 LDCKB C11 GND G10 GND K9 GND

A9 SAB D1 A1 G11 B5 K10 B10
A10 GAB D2 A0 H1 A7 K11 B9
A11 AF/AEB D10 B0 H2 GND L1 A10

B1 FULLA D11 B1 H10 GND L2 A12

B2 AF/AEA E1 A3 H11 B7 L3 A13

B3 RSTA E2 A2 J1 A8 L4 A14

B4 GND E3 V

CC

J2 V

CC

L5 A16

B5 EMPTYB E9 V

CC

J5 A15 L6 B15
B6 UNCKA E10 B2 J6 NC L7 B16
B7 EMPTYA E11 B3 J7 B17 L8 B14
B8 GND F1 A6 J10 V

CC

L9 B13

B9 RSTB F2 GND J11 B8 L10 B12

B10 PENB F3 NC K1 A9 L11 B11

SN54ABT7820

512 × 18 × 2

STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS303E – AUGUST 1994 – REVISED APRIL 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

I/O DESCRIPTION

A0–A17 I/O Port-A data. The 18-bit bidirectional data port for side A.

AF/AEA O

FIFO A almost-full/almost-empty flag. Depth offset values can be programmed for AF/AEA, or the default value of 128
can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is high when FIFO A contains
X or fewer words or (512 – Y) or more words. AF/AEA is set high after FIFO A is reset.

AF/AEB O

FIFO B almost-full/almost-empty flag. Depth offset values can be programmed for AF/AEB, or the default value of 128
can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is high when FIFO B contains
X or fewer words or (512 – Y) or more words. AF/AEB is set high after FIFO B is reset.

B0–B17 I/O Port-B data. The 18-bit bidirectional data port for side B.
EMPTYA O

FIFO A empty flag. EMPTYA is low when FIFO A is empty and is high when FIFO A is not empty. EMPTYA is set low
after FIFO A is reset.

EMPTYB O

FIFO B empty flag. EMPTYB is low when FIFO B is empty and is high when FIFO B is not empty. EMPTYB is set low
after FIFO B is reset.

FULLA O

FIFO A full flag. FULLA is low when FIFO A is full and is high when FIFO A is not full. FULLA is set high after FIFO A
is reset.

FULLB O

FIFO B full flag. FULLB is low when FIFO B is full and is high when FIFO B is not full. FULLB is set high after FIFO B
is reset.

GAB I

Port-B output enable. B0–B17 outputs are active when GAB is high and are in the high-impedance state when GAB
is low.

GBA I

Port-A output enable. A0–A17 outputs are active when GBA is high and are in the high-impedance state when GBA
is low.

HFA O

FIFO A half-full flag. HFA is high when FIFO A contains 256 or more words and is low when FIFO A contains 255 or
fewer words. HFA is set low after FIFO A is reset.

HFB O

FIFO B half-full flag. HFB is high when FIFO B contains 256 or more words and is low when FIFO B contains 255 or
fewer words. HFB is set low after FIFO B is reset.

LDCKA I

FIFO A load clock. Data is written into FIFO A on a low-to-high transition of LDCKA when FULLA is high. The first word
written into an empty FIFO A is sent directly to the FIFO A data outputs.

LDCKB I

FIFO B load clock. Data is written into FIFO B on a low-to-high transition of LDCKB when FULLB is high. The first word
written into an empty FIFO B is sent directly to the FIFO B data outputs.

PENA I

FIFO A program enable. After reset and before a word is written into FIFO A, the binary value on A0–A7 is latched as
an AF/AEA offset value when PENA

is low and LDCKA is high.

PENB I

FIFO B program enable. After reset and before a word is written into FIFO B, the binary value on B0–B7 is latched as
an AF/AEB offset value when PENB

is low and LDCKB is high.
RSTA I FIFO A reset. A low level on RSTA resets FIFO A, forcing EMPTYA low, HFA low, FULLA high, and AF/AEA high.
RSTB I FIFO B reset. A low level on RSTB resets FIFO B, forcing EMPTYB low, HFB low, FULLB high, and AF/AEB high.

SAB I

Port-B read select. SAB selects the source of B0–B17 read data. A low level selects real-time data from A0–A17. A
high level selects the FIFO A output.

SBA I

Port-A read select. SBA selects the source of A0–A17 read data. A low level selects real-time data from B0 –B17. A

high level selects the FIFO B output.
UNCKA I FIFO A unload clock. Data is read from FIFO A on a low-to-high transition of UNCKA when EMPTYA is high.
UNCKB I FIFO B unload clock. Data is read from FIFO B on a low-to-high transition of UNCKB when EMPTYB is high.

SN54ABT7820
512 × 18 × 2
STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS303E – AUGUST 1994 – REVISED APRIL 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

B6

UNCKA

LDCKA

A1

B10

PROG ENB

B5

EMPTYB

PROG ENA

A1

EMPTYA

B7

FULLA

B1

A4

LDCKA

UNCKA

B3

EN2

A2

GBA

EN1

A10

GAB

0

A3

SBA

1

A9

SAB

B11

FULLB

UNCKB

C5

LDCKB

A8

B9

RESET B

A2
A3
A4
A5
A6
A7

B1
B2
B3
B4
B5
B6
B7

D11
E10

E11

G9

G11

F10

H11

D1
E2
E1
G3
G1
F1
H1

A8

J1

B8

J11

ALMOST-FULL/

B2

AF/AEA

ALMOST-EMPTY A

AF/AEB

A11

ALMOST-FULL/

ALMOST-EMPTY B

0

D2

A0

B0

D10

0

HALF-FULL A

C2

HFA HFB

C10

HALF-FULL B

A10
A11
A12
A13
A14
A15
A16

L1
K2
L2
L3
L4
J5
L5

A17

K6

K1

A9

B10
B11
B12

B13
B14

B15
B16

K10

L11
L10

L9
L8

L6
L7

B17

J7

B9

K11

A Data B Data

LDCKB

UNCKB

Φ

FIFO

512 × 18 × 2

SN54ABT7820

MODE

17

17

RSTA

PENA

FULLA

EMPTYA

RSTB
PENB

FULLB
EMPTYB

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

SN54ABT7820

512 × 18 × 2

STROBED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SGBS303E – AUGUST 1994 – REVISED APRIL 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

Q

D

Q

D

B0

1 of 18 Channels

SAB

SBA

EMPTYB

UNCKB

GBA

GAB

RSTA

PENA

FULLA

LDCKA

A0

RSTB
PENB
FULLB
LDCKB

To Other Channels

1 of 18 Channels

To Other Channels

EMPTYA
UNCKA

AF/AEA

AF/AEB

HFB

HFA

[1]
[2]
[3]
[4]

[15]
[16]
[17]
[18]

[1]
[2]
[3]
[4]

[15]
[16]
[17]
[18]

Φ

FIFO B

512 × 18

Φ

FIFO A

512 × 18