Texas Instruments SN74ABT652ADW, SN74ABT652ADWR, SN74ABT652ANT, SN74ABT652ADBLE, SN74ABT652ADBR Datasheet

SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS072F – JANUARY 1991 – REVISED MA Y 1997

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17

D

Typical V

(Output Ground Bounce)

OLP

< 1 V at VCC = 5 V, TA = 25°C

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs

description

These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.

Output-enable (OEAB and OEBA) inputs are
provided to control the transceiver functions.
Select-control (SAB and SBA) inputs are provided
to select either real-time or stored data for
transfer. The circuitry used for select control
eliminates the typical decoding glitch that occurs
in a multiplexer during the transition between
stored and real-time data. A low input selects
real-time data, and a high input selects stored
data. Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the ’ABT652A.

SN54ABT652A . . . JT OR W PACKAGE

SN74ABT652A . . . DB, DW, NT, OR PW PACKAGE

CLKAB

SN54ABT652A . . . FK PACKAGE

A1
A2
A2

NC

A4
A5
A6

NC – No internal connection

(TOP VIEW)

24
23
22
21
20
19
18
17
16
15
14
13

CC

V

B8B7B6

NC

V

CC

CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8

SBA

25
24
23
22
21
20
19

OEBA
B1
B2
NC
B3
B4
B5

1

SAB

2

OEAB

GND

3

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

10

A8

11
12

(TOP VIEW)

OEAB

SAB

CLKABNCCLKBA

3212827

426

5
6
7
8
9
10
11

12 13

14 15 16 17 18

A7

A8

GND

Data on the A- or B-data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions
at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control inputs. When SAB
and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA

. In this configuration, each output reinforces its input. When all
other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last
state.

To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

SN54ABT652A, SN74ABT652A

OPERATION OR FUNCTION

OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS072F – JANUARY 1991 – REVISED MA Y 1997

description (continued)

The SN54ABT652A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT652A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OEAB OEBA CLKAB CLKBA SAB SBA A1–A8 B1–B8

L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified

H H ↑↑X

L X H or L ↑ X X Unspecified
L L ↑↑XX‡Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus

L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus

H L H or L H or L H H Output Output

†

The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

‡

Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.

‡

X Input Output Store A in both registers

DATA I/O

†

‡

‡

Input Hold A, store B

Store A, hold B

Stored A data to B bus and

stored B data to A bus

. Data-input functions are always

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT652A, SN74ABT652A

OCTAL REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS072F – JANUARY 1991 – REVISED MA Y 1997

BUS A

3 21 1 23 2 22 1 23 2 22321

OEAB

OEBA

LL

CLKABXCLKBAXSABXSBA

REAL-TIME TRANSFER

BUS B TO BUS A

BUS A

BUS B

OEAB OEBA

L

BUS B

BUS A

HH

BUS A

BUS B

CLKABXCLKBAXSABLSBA

X

REAL-TIME TRANSFER

BUS A TO BUS B

BUS B

3 21 23 2 22 3 21 1 2 22

OEAB

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

OEBA
X
L
L

H
X
H

1

CLKAB CLKBAXSABXSBA

↑

XX

↑

X

↑↑

STORAGE FROM

A, B, OR A AND B

X
X
X

Figure 1. Bus-Management Functions

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23

OEAB OEBA

H L H or L H H

CLKAB CLKBA SAB SBA

H or L

TRANSFER STORED DA TA

TO A AND/OR B

3

SN54ABT652A, SN74ABT652A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS

SCBS072F – JANUARY 1991 – REVISED MA Y 1997

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.

†

SBA

SAB

A1

A2
A3
A4
A5
A6
A7
A8

21
3
23
22

1
2

4

5
6
7
8
9
10
11

EN1 [BA]
EN2 [AB]

C4

G5

C6

G7

5

≥1

1

5

7

6D ≥1

1

7

4D

1

2

OEBA

OEAB

CLKBA

CLKAB

19
18
17
16
15
14
13

20

B1

B2
B3
B4
B5
B6
B7
B8

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265