Datasheet SN74ABT646ADBLE, SN74ABT646ADBR, SN74ABT646ADGVR, SN74ABT646ADW, SN74ABT646ADWR Datasheet (Texas Instruments)
...
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G – JULY 1991 – REVISED MAY 1997
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
Typical V
(Output Ground Bounce)
OLP
< 1 V at VCC = 5 V, TA = 25°C
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
description
These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
input bus or from the internal registers. Data on
the A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ’ABT646A.
Output-enable (OE
inputs are provided to control the transceiver
functions. In the transceiver mode, data present at
the high-impedance port can be stored in either
register or in both.
) and direction-control (DIR)
SN54ABT646A ...JT OR W PACKAGE
SN74ABT646A . . . DB, DW, NT, OR PW PACKAGE
CLKAB
SN54ABT646A . . . FK PACKAGE
A1
A2
A3
NC
A4
A5
A6
NC – No internal connection
(TOP VIEW)
1
SAB
2
DIR
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
11
GND
12
(TOP VIEW)
DIR
SAB
CLKAB
432128
5
6
7
8
9
10
11
12 13 14 15 16
A8
A7
GND
24
23
22
21
20
19
18
17
16
15
14
13
NC
NC
CC
V
27 26
17 18
B8
V
CC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
CLKBA
SBA
25
24
23
22
21
20
19
B7
B6
OE
B1
B2
NC
B3
B4
B5
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),
A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT646A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT646A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G – JULY 1991 – REVISED MAY 1997
BUS A
21
OE OE
L
3
DIR
L
BUS A
1
23
CLKAB
REAL-TIME TRANSFER
BUS B TO BUS A
CLKBA
X
X
2
SAB
X
BUS B
22
SBA
L
BUS B
21
L
BUS A
3
DIR
H
BUS A
1
CLKAB
REAL-TIME TRANSFER
BUS A TO BUS B
CLKBA
X
23
BUS B
2
22
SAB
X
L
SBA
X
BUS B
21
X
X
H
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
3
DIR
X
X
X
1
CLKAB23CLKBA
↑
XX
STORAGE FROM
A, B, OR A AND B
2
22
SAB
X
↑
↑↑
SBA
X
X
X
X
X
Figure 1. Bus-Management Functions
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
OEOE
L
LH L XHX
3
DIR
L
1
CLKAB
X
TRANSFER STORED DA TA
TO A AND/OR B
23
CLKBA
L
2
SAB
X
22
SBA
H
OPERATION OR FUNCTION
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G – JULY 1991 – REVISED MAY 1997
FUNCTION TABLE
INPUTS
OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8
X X ↑ X X X Input Unspecified
X XX ↑ X X Unspecified
H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus
†
The data-output functions may be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
DATA I/Os
†
†
Input Store B, A unspecified
Store A, B unspecified
†
†
logic symbol
‡
OE
DIR
CLKBA
SBA
CLKAB
SAB
A1
A2
A3
A4
A5
A6
A7
A8
21
3
23
22
1
2
4
5
6
7
8
9
10
11
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
5
≥1
1
5
7
6D ≥1
7
1
20
19
18
17
16
15
14
13
B1
B2
B3
B4
B5
B6
B7
B8
4D
1
2
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G – JULY 1991 – REVISED MAY 1997
logic diagram (positive logic)
21
OE
3
DIR
SBA
SAB
23
22
1
2
One of Eight
Channels
CLKBA
CLKAB
1D
C1
4
A1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
20
B1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G – JULY 1991 – REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
Input clamp current, I
Output clamp current, I
Package thermal impedance, θJA (see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54ABT646A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
SN74ABT646A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
SN54ABT646A SN74ABT646A
MIN MAX MIN MAX
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 5 5 ns/V
T
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
A
CC
0 V
CC
V
†
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5
SN54ABT646A, SN74ABT646A
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
4.5 V
VOLV
V
V
I
V
V
V
GND
A
V
CC
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G – JULY 1991 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABT646A SN74ABT646A
MIN TYP†MAX MIN MAX MIN MAX
V
IK
OH
V
hys
Control inputs
I
A or B ports
‡
I
OZH
‡
I
OZL
I
off
I
CEX
¶
I
O
I
CC
#
∆I
CC
C
Control inputs VI = 2.5 V or 0.5 V 7 pF
i
C
A or B ports VO = 2.5 V or 0.5 V 12 pF
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
The parameters I
§
This data sheet limit may vary among suppliers.
¶
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
#
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
=
CC
= 4.5
CC
= 5.5 V,
CC
VCC = 5.5 V, VO = 2.7 V 10
VCC = 5.5 V, VO = 0.5 V –10
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
OZH
and I
include the input leakage current.
OZL
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
=
or
I
CC
Outputs high 50 50 50 µA
Outputs high 250 250 250 µA
Outputs low 30 30 30 mA
Outputs disabled 250 250 250 µA
±1 ±1 ±1
±100 ±100 ±100
§
§
1.5 1.5 1.5 mA
10
–10
§
§
10
–10
µ
§
µA
§
µA
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT646A
VCC = 5 V,
TA = 25°C
MIN MAX
f
clock
t
w
t
su
t
h
6
Clock frequency 0 125 0 125 MHz
Pulse duration, CLK high or low 4 4 ns
Setup time, A or B before CLKAB↑ or CLKBA↑ 3 3.5 ns
Hold time, A or B after CLKAB↑ or CLKBA↑ 1.5 1.5 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MIN MAX
UNIT
CLKBA or CLKAB
A or B
ns
A or B
B or A
ns
SAB
SBA
†
B or A
ns
OE
A or B
ns
OE
A or B
ns
DIR
A or B
ns
DIR
A or B
ns
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G – JULY 1991 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT646A
VCC = 5 V,
f
clock
t
w
t
su
t
h
TA = 25°C
MIN MAX
Clock frequency 0 125 0 125 MHz
Pulse duration, CLK high or low 4 4 ns
Setup time, A or B before CLKAB↑ or CLKBA↑ 3 3 ns
Hold time, A or B after CLKAB↑ or CLKBA↑ 0 0 ns
MIN MAX
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
PLZ
= 50 pF (unless otherwise noted) (see Figure 2)
L
FROM
(INPUT)
or
TO
(OUTPUT)
SN54ABT646A
VCC = 5 V,
TA = 25°C
MIN TYP MAX
125 125 MHz
2.2 4 5.1 2.2 6.7
1.7 4 5.1 1.2 6.7
1.5 3 4.3 1.5 5
1.5 3.3 4.6 1.5 5.6
1.5 4 5.7 1.5 7.8
1.5 3.6 4.9 1.5 6.2
1.5 4.3 5.3 1.5 7
3 5.8 8 3 10.5
1.5 3.5 5.8 1 7.3
1.5 3 4 1.5 5.7
1.5 4.5 5.7 1.5 7.3
2.5 6.5 9 2.5 11
1.5 3.8 6.5 1 9
1.5 3.8 4.7 1.2 6.7
MIN MAX
UNIT
UNIT
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7
SN54ABT646A, SN74ABT646A
CLKBA or CLKAB
A or B
ns
A or B
B or A
ns
SAB
SBA
†
B or A
ns
OE
A or B
ns
OE
A or B
ns
DIR
A or B
ns
DIR
A or B
ns
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUPUTS
SCBS069G – JULY 1991 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
PLZ
= 50 pF (unless otherwise noted) (see Figure 2)
L
FROM
(INPUT)
or
TO
(OUTPUT)
SN74ABT646A
VCC = 5 V,
TA = 25°C
MIN TYP MAX
125 125 MHz
2.2 4 5.1 2.2 5.6
1.7 4 5.1 1.7 5.6
1.5 3 4.3 1.5 4.8
1.5 3.3 4.6 1.5 5.4
1.5 4 5.1 1.5 6.5
1.5 3.6 4.9 1.5 5.9
1.5 4.3 5.3 1.5 6.3
3 5.8 7.4 3 8.8
1.5 3.5 4.5 1.5 5
1.5 3 4 1.5 4.5
1.5 4.5 5.7 1.5 6.7
2.5 6.5 9 2.5 9.5
1.5 3.8 5 1.5 5.7
1.5 3.8 4.7 1.5 6
MIN MAX
UNIT
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
Input
CL = 50 pF
(see Note A)
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
500 Ω
LOAD CIRCUIT
t
w
SN54ABT646A, SN74ABT646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
SCBS069G – JULY 1991 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
500 Ω
S1
Open
GND
3 V
0 V
Timing Input
Data Input
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
WITH 3-STATE OUPUTS
Open
7 V
Open
3 V
1.5 V
0 V
t
su
h
3 V
0 V
Input
t
PLH
Output
t
PHL
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
1.5 V1.5 V
Figure 2. Load Circuit and Voltage Waveforms
t
PHL
t
PLH
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
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