SN54ABT543A, SN74ABT543A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS157F – JANUARY 1991 – REVISED MA Y 1997
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
description
The ’ABT543A octal transceivers contain two sets
of D-type latches for temporary storage of data
flowing in either direction. Separate latch-enable
(LEAB
or LEBA) and output-enable (OEAB or
OEBA) inputs are provided for each register to
permit independent control in either direction of
data flow.
The A-to-B enable (CEAB) input must be low to
enter data from A or to output data from B. If CEAB
is low and LEAB is low, the A-to-B latches are
transparent; a subsequent low-to-high transition
of LEAB
With CEAB and OEAB both low, the 3-state
B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to
A is similar, but requires using the CEBA
and OEBA inputs.
T o ensure the high-impedance state during power
up or power down, OE should be tied to V
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
puts the A latches in the storage mode.
, LEBA,
CC
SN54ABT543A . . . JT OR W PACKAGE
SN74ABT543A . . . DB, DW, NT, OR PW PACKAGE
OEBA
CEAB
SN54ABT543A . . . FK PACKAGE
A2
A3
A4
NC
A5
A6
A7
NC – No internal connection
(TOP VIEW)
LEBA
GND
1
2
3
A1
A2
4
5
A3
A4
6
7
A5
8
A6
9
A7
10
A8
11
12
(TOP VIEW)
A1
OEBA
LEBANCCEBA
3212827
426
5
6
7
8
9
10
11
12 13
14 15 16 17 18
A8
GND
CEAB
NC
24
23
22
21
20
19
18
17
16
15
14
13
CC
V
OEAB
V
CC
CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
OEAB
B1
25
24
23
22
21
20
19
B8
LEAB
B2
B3
B4
NC
B5
B6
B7
The SN54ABT543A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT543A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT543A, SN74ABT543A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS157F – JANUARY 1991 – REVISED MA Y 1997
logic symbol
FUNCTION TABLE
INPUTS
CEAB LEAB OEAB A
H X X X Z
X XHX Z
L HLXB
L LLL L
L L L H H
†
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA
‡
Output level before the indicated steady-state
input conditions were established
†
OUTPUT
B
‡
0
, LEBA, and OEBA.
§
A1
A2
A3
A4
A5
A6
A7
A8
2
23
1
13
11
14
3
4
5
6
7
8
9
10
1EN3
G1
1C5
2EN4
G2
2C6
3
6D
1
5D
1
4
22
21
20
19
18
17
16
15
B1
B2
B3
B4
B5
B6
B7
B8
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54ABT543A, SN74ABT543A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS157F – JANUARY 1991 – REVISED MA Y 1997
A1
2
23
1
13
11
14
3
C1
1D
To Seven Other Channels
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
C1
1D
22
B1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
Current into any output in the low state, IO: SN54ABT543A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT543A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
(V
< 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
O
(see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
O
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABT543A, SN74ABT543A
UNIT
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
V
VOLV
4.5 V
V
I
V
V
V
GND
A
V
CC
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS157F – JANUARY 1991 – REVISED MA Y 1997
recommended operating conditions (see Note 3)
SN54ABT543A SN74ABT543A
MIN MAX MIN MAX
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 5 5 ns/V
T
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
V
V
I
I
OZH
I
OZL
I
off
I
CEX
I
O
I
CC
∆I
C
C
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
The parameters I
§
This data sheet limit may vary among suppliers.
¶
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
#
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
High-level output current –24 –32 mA
Low-level output current 48 64 mA
Operating free-air temperature –55 125 –40 85 °C
A
TA = 25°C SN54ABT543A SN74ABT543A
MIN TYP†MAX MIN MAX MIN MAX
IK
OH
hys
Control inputs
A or B ports
‡
‡
¶
A or B ports
#
CC
Control inputs VI = 2.5 V or 0.5 V 4 pF
i
A or B ports VO = 2.5 V or 0.5 V 7 pF
io
OZH
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
= 4.5
CC
=
CC
= 5.5 V,
CC
VCC = 5.5 V, VO = 2.7 V 10
VCC = 5.5 V, VO = 0.5 V –10
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
VCC = 5.5 V,
VO = 5.5 V
VCC = 5.5 V, VO = 2.5 V –50* –100 –180* –50 –200 –50 –180 mA
=
= 5.5 V,
IO = 0,
VI = VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
and I
include the input leakage current.
OZL
IOH = –24 mA 2 2
IOH = –32 mA 2* 2
IOL = 48 mA 0.55 0.55
IOL = 64 mA 0.55* 0.55
100 mV
=
or
I
CC
Outputs high 50 50 50 µA
Outputs high 1 250* 350 250 µA
Outputs low 24 30* 34 30 mA
Outputs disabled 0.5 250* 350 250 µA
±1 ±1 ±1
±100 ±100 ±100
§
§
1.5 1.5 1.5 mA
10
–10
CC
§
§
0 V
10
–10
CC
V
µ
§
µA
§
µA
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Data bef
LEAB
LEBA↑
tsuSetup time
ns
Data bef
CEAB
CEBA↑
thHold time
ns
Data bef
LEAB
LEBA↑
tsuSetup time
ns
Data bef
CEAB
CEBA↑
thHold time
ns
SN54ABT543A, SN74ABT543A
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS157F – JANUARY 1991 – REVISED MA Y 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT543A
VCC = 5 V,
TA = 25°C
MIN MAX
t
w
Pulse duration, LEAB or LEBA low 3.5 3.5 ns
ore
p
ore
Data after LEAB or LEBA↑ 1 1
Data after CEAB or CEBA↑ 1 1
or
or
High 2.5 2.5
Low 3 3
High 2.5 2.5
Low 3 3
MIN MAX
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT543A
VCC = 5 V,
TA = 25°C
MIN MAX
t
w
Pulse duration, LEAB or LEBA low 3.5 3.5 ns
ore
p
ore
Data after LEAB or LEBA↑ 0.5 0.5
Data after CEAB or CEBA↑ 0.5 0.5
or
or
High 3.5 3.5
Low 3 3
High 3.5 3.5
Low 3 3
MIN MAX
UNIT
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABT543A, SN74ABT543A
A or B
B or A
ns
LEBA
LEAB
A or B
ns
OEBA
OEAB
A or B
ns
OEBA
OEAB
A or B
ns
CEBA
CEAB
A or B
ns
CEBA or CEAB
A or B
ns
A or B
B or A
ns
LEBA
LEAB
A or B
ns
OEBA
OEAB
A or B
ns
OEBA
OEAB
A or B
ns
CEBA
CEAB
A or B
ns
CEBA or CEAB
A or B
ns
OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS157F – JANUARY 1991 – REVISED MA Y 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
†
This data sheet limit may vary among suppliers.
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
or
or
or
or
TO
(OUTPUT)
SN54ABT543A
VCC = 5 V,
TA = 25°C
MIN TYP MAX
†
1.6
1.6
2.5
2.5
3.2†
2.5
4.4 4.4 1.6
1.6 4.4 5.1 1.6 6.2
†
4.1 5.1 1.6
1.6 4.6 5.4 1.6 6.4
1.4 3.9 4.1 1.4 5.1
2 5 4.9 2 5.8
†
5.9 5.8 2.5
†
5.5 6.1 2.5
1.4 3.9 4.7 1.4 5.6
2 5 5.7 2 6.2
5.9 6.5
†
5.5 6.7 2.5
MIN MAX
†
†
†
†
3.2†
†
UNIT
5.5
6.6
6.9
7.6
7.3
7.8
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
†
This data sheet limit may vary among suppliers.
PLZ
= 50 pF (unless otherwise noted) (see Figure 1)
L
FROM
(INPUT)
or
or
or
or
TO
(OUTPUT)
SN74ABT543A
VCC = 5 V,
TA = 25°C
MIN TYP MAX
†
1.8
1.5
2.5
2.5
2.9†
2.4
4.4 5.9 1.8
1.9 4.4 5.9 1.9 6.9
†
4.1 5.6 1.5
2.1 4.6 6.1 2.1 7.1
1.4 3.9 5.4 1.4 6.4
2.5 5 6.5 2.5 7.5
†
5.9 7.4 2.5
†
5.5 7 2.5
1.4 3.9 5.4 1.4 6.4
2.5 5 6.5 2.5 7.5
5.9 7.4
†
5.5 7 2.4
MIN MAX
†
†
†
†
2.9†
†
UNIT
6.9
6.6
8.4
8
8.4
8
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
SN54ABT543A, SN74ABT543A
OCTAL REGISTERED TRANSCEIVERS
SCBS157F – JANUARY 1991 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
7 V
500 Ω
500 Ω
S1
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
WITH 3-STATE OUTPUTS
Open
7 V
Open
LOAD CIRCUIT
t
w
Input
Input
Output
Output
INVERTING AND NONINVERTING OUTPUTS
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
1.5 V
t
PHL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
PHL
1.5 V
t
1.5 V1.5 V
PLH
3 V
0 V
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
t
PZL
t
PLZ
1.5 V
t
t
PZH
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
PHZ
1.5 V
VOLTAGE WAVEFORMS
t
h
1.5 V
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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