Texas Instruments SN74ABT16240ADGGR, SN74ABT16240ADGVR, SN74ABT16240ADL, SN74ABT16240ADLR, SNJ54ABT16240AWD Datasheet

SN54ABT16240A, SN74ABT16240A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998
D
Widebus
D
State-of-the-Art
Family
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
T ypical V at V
D
Distributed VCC and GND Pin Configuration
= 5 V, TA = 25°C
CC
(Output Ground Bounce) < 1 V
OLP
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Latch-Up Performance Exceeds 500 mA Per JESD 17
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
description
The ’ABT16240A devices are 16-bit buffers and line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
SN54ABT16240A . . . WD PACKAGE
SN74ABT16240A . . . DGG, DGV, OR DL PACKAGE
1OE
1Y1 1Y2
GND
1Y3 1Y4
V
CC
2Y1 2Y2
GND
2Y3 2Y4 3Y1 3Y2
GND
3Y3 3Y4
V
CC
4Y1 4Y2
GND
4Y3 4Y4
4OE
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE 1A1 1A2 GND 1A3 1A4 V
CC
2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 V
CC
4A1 4A2 GND 4A3 4A4 3OE
These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide inverting outputs and symmetrical active-low output-enable (OE
T o ensure the high-impedance state during power up or power down, OE
) inputs.
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16240A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16240A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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SN54ABT16240A, SN74ABT16240A 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE A
L H L L LH
HXZ
OUTPUT
Y
logic symbol
1
1OE 2OE 3OE
4OE
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4
48 25 24
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
EN1 EN2
EN3 EN4
11
12
13
14
11 12 13 14 16 17 19 20 22 23
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
2Y1
9
2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
SN54ABT16240A, SN74ABT16240A
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS095G – DECEMBER 1991 – REVISED OCTOBER 1998
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
47
46
44
43
48
41
40
38
37
11
12
25
3OE
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
2Y1
9
2Y2
2Y3
2Y4
3A1
3A2
3A3
3A4
4OE
4A1
4A2
4A3
4A4
36
35
33
32
24
30
29
27
26
13
14
16
17
19
20
22
23
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V Voltage range applied to any output in the high or power-off state, V Current into any output in the low state, I
Input clamp current, I Output clamp current, I Package thermal impedance, θ
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54ABT16240A 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
O
SN74ABT16240A 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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