SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
3:21 Data Channel Expansion at up to 163
Million Bytes per Second Throughput
D
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
D
3 Data Channels and Clock Low-Voltage
Differential Channels In and 21 Data and
Clock Low-Voltage TTL Channels Out
D
Operates From a Single 3.3-V Supply and
250 mW (Typ)
D
5-V Tolerant SHTDN Input
D
ESD Protection Exceeds 4 kV on Bus Pins
D
Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch
D
Consumes Less Than 1 mW When Disabled
D
Wide Phase-Lock Input Frequency Range
31 MHz to 68 MHz
D
No External Components Required for PLL
D
Open-Circuit Receiver Fail-Safe Design
D
Inputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
D
Improved Replacement for the DS90C562
description
The SN75LVDS86 FlatLink receiver contains
three serial-in 7-bit parallel-out shift registers, a 7×
clock synthesizer, and four low-voltage dif ferential signaling (L VDS) line receivers in a single integrated circuit.
These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81,
’83, ’84, or ’85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage TTL
(LVTTL) synchronous data at a lower transfer rate.
When receiving, the high-speed L VDS data is received and loaded into registers at seven times the L VDS input
clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for
the expanded data. The SN75LVDS86 presents valid data on the falling edge of the output clock (CLKOUT).
The SN75L VDS86 requires only four line-termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear
(SHTDN
) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A
low level on this signal clears all internal registers to a low level.
The L VDS receivers of the SN75L VDS86 include an open-circuit fail-safe design such that when the inputs are
not connected to an LVDS driver, the receiver outputs go to a low-level. This occurs even when the line is
differentially terminated at the receiver inputs.
The SN75LVDS86 is characterized for operation over ambient free-air temperatures of 0_C to 70_C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments Incorporated.
1
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9
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17
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24
48
47
46
45
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42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D17
D18
GND
D19
D20
NC
L VDSGND
A0M
A0P
A1M
A1P
L VDSV
CC
L VDSGND
A2M
A2P
CLKINM
CLKINP
L VDSGND
PLLGND
PLL V
CC
PLLGND
SHTDN
CLKOUT
D0
V
CC
D16
D15
D14
GND
D13
V
CC
D12
D11
D10
GND
D9
V
CC
D8
D7
D6
GND
D5
D4
D3
V
CC
D2
D1
GND
DGG PACKAGE
(TOP VIEW)
NC – Not Connected
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Serial In
CLK
Serial-In/Parallel-
Out Shift Register
Serial In
CLK
Serial In
CLK
Control Logic
CLK
Clock In
7× Clock/PLL
SHTDN
CLKINP
A2P
A2M
A1P
A1M
A0P
A0M
CLKOUT
CLKINM
D14
D15
D16
D17
D18
D19
D20
D7
D8
D9
D10
D11
D12
D13
D0
D1
D2
D3
D4
D5
D6
A, B, ...G
Clock Out
A, B, ...G
A, B, ...G
Serial-In/Parallel-
Out Shift Register
Serial-In/Parallel-
Out Shift Register
Input Bus
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLKOUT
CLKIN
D0
A0
A1
A2
D0–1 D6 D4 D3 D2 D1 D0 D6+1
D7–1 D13 D12 D11 D10 D9 D8 D7 D13+1
D14–1 D20 D19 D18 D17 D16 D15 D14 D20+1
Current CyclePrevious Cycle Next Cycle
Dn – 1 Dn Dn + 1
D5
Figure 1. SN75LVDS86 Load and Shift Timing Sequences
equivalent input and output schematic diagrams
V
CC
50 Ω
300 kΩ
7 V
SHTDN
V
CC
7 V
5 Ω
D Output
INPUT
OUTPUT
V
CC
300 kΩ
AnM
7 V
7 V
300 kΩ
AnP
INPUT
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (Dxx terminals) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(any terminal except SHTDN) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(SHTDN) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND unless otherwise noted.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DGG 1316 mW 13.1 mW/°C 726 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with
no air flow.
recommended operating conditions (see Figure 2)
MIN NOM MAX UNIT
Supply voltage, V
CC
3 3.3 3.6 V
High-level input voltage, VIH (SHTDN) 2 V
Low-level input voltage, VIL (SHTDN) 0.8 V
Differential input voltage, |VID| 0.1 0.6 V
Common-mode input voltage, VIC (see Figure 2 and Figure 3)
|VID|
2
2.4
*
|VID|
2
V
VCC – 0.8
Operating free-air temperature, T
A
0 70 °C
timing requirements
MIN NOM MAX UNIT
t
c
Cycle time, input clock
§
14.7 tc32.4 ns
t
su1
Setup time, input (see Figure 7) 600 ps
t
h1
Hold time, input (see Figure 7) 600 ps
§
Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles.
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IT+
Positive-going differential input threshold voltage 100 mV
V
IT–
Negative-going differential input threshold voltage
‡
–100 mV
V
OH
High-level output voltage IOH = –4 mA 2.4 V
V
OL
Low-level output voltage IOL = 4 mA 0.4 V
Disabled, All inputs open 280 µA
Enabled,
AnM = 1.4 V ,
AnP = 1 V,
tc = 15.38 ns
58 72 mA
I
CC
Quiescent current (average)
Enabled,
CL = 8 pF,
Grayscale pattern (see Figure 4),
tc = 15.38 ns
69 mA
Enabled,
CL = 8 pF,
Worst-case pattern (see Figure 5)
tc = 15.38 ns
94 mA
I
IH
High-level input current (SHTDN) VIH = V
CC
±20 µA
I
IL
Low-level input current (SHTDN) VIL = 0 ±20 µA
I
I
Input current (LVDS input terminals A and CLKIN) 0 ≤ VI ≤ 2.4 V ±20 µA
I
OZ
High-impedance output current VO = 0 or V
CC
±10 µA
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going
input voltage threshold only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
t
su2
Set up time, D0 – D20 valid to CLKOUT↓
C
= 8 pF,
5 ns
t
h2
Hold time, CLKOUT↓ to D0 – D20 valid
L
,
See Figure 6
5 ns
t
RSKM
Receiver input skew margin§ (see Figure 7)
tc = 15.38 ns (±0.2%),
|Input clock jitter| < 50 ps¶,
490 ps
t
d
Delay time, CLKIN↑ to CLKOUT↓
(see Figure 7)
tc = 15.38 ns (±0.2%),
CL = 8 pF
3.7 ns
tc = 15.38 + 0.75 sin (2π500E3t) ±0.05 ns,
See Figure 8
±80
p
∆t
c(o)
Cycl
e time, change in output clock perio
d#
tc = 15.38 + 0.75 sin (2π3E6t) ±0.05 ns,
See Figure 8
±300
ps
t
en
Enable time, SHTDN↑ to Dn valid
See Figure 9 1 ms
t
dis
Disable time, SHTDN↓ to off state
See Figure 10 400 ns
t
t
Transition time, output (10% to 90% tr or tf) CL = 8 pF 3 ns
t
w
Pulse duration, output clock 0.43 t
c
ns
†
All typical values are at VCC = 3.3 V, TA = 25°C.
§
The parameter t
(RSKM)
is the timing margin available to the transmitter and interconnection skews and clock jitter. It is defined by
t
c
14
*
t
su1
ń
t
h1
¶
|Input clock jitter| is the magnitude of the change in input clock period.
#
∆t
c(o)
is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
ID
AP
AM
V
IAM
V
IAP
V
IC
(V
IAP
+ V
IAM
)/2
Figure 2. Voltage Definitions
0
2.5
2
1.5
1
0.5
0
0.1 0.2 0.3 0.4 0.5 0.6
|VID| – Differential Input Voltage – V
Maximum at VCC = 3 V
Maximum at VCC >3.15 V
Minimum
V
IC
– Common-Mode Input Voltage – V
Figure 3. Maximum Common-Mode Input Voltage Vs Differential Input Voltage and V
CC
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CLKIN
D0, 6, 12
D1, 7, 13
D2, 8, 14
D3, 9, 15
D18, 19, 20
ALL OTHERS
NOTE A: The 16-grayscale test-pattern test device power consumption for a typical display pattern.
Figure 4. 16-Grayscale Test-Pattern Waveforms
t
c
NOTE A: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVTTL outputs.
CLKIN/CLKOUT
Even Dn
Odd Dn
Figure 5. Worst-Case Test-Pattern Waveforms
D0–D20
t
su2
CLKOUT
t
h2
70% V
OH
70% V
OH
30% V
OH
30% V
OH
Figure 6. Setup and Hold Time Waveforms
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Device
Under
Test
(DUT)
CLKIN
Tektronix
HFS9003/HFS9DG1
Stimulus System
(repeating patterns of
1110111 and 0001000)
Tektronix
Microwave Logic
Multi-BERT-100RX
Word Error Detector
An D0 – D27
CLKOUT
An
CLKIN
t
c
CLKOUT
t
d
0 V
≈300 mV
≈–300 mV
80%
20%
tr < 1 ns
V
OL
V
OH
1.4 V
t
d
3
7
tct
(RSKM)
t
h1
t
su1
4
7
tct
(RSKM)
and An
7× CLK
(Internal)
CLKIN
or An
CLKOUT
t
W
t
W
±
±
(see Note A)
(see Note A)
NOTE A: CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance or delay is then
reduced until there are no data errors observed. The magnitude of the advance or delay is t
(
RSKM
)
.
Figure 7. Receiver Input Skew Margin, Setup/Hold Time, and Delay Time Definitions
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Reference
VCO
Device
Under
Test
Modulation
∑
+
+
V(t) = A sin (2 π f
(mod)
t)
HP8656B
Signal Generator
0.1 MHz – 990 MHz
HP8665A
Synthesized Signal
Generator
0.1 MHz – 4200 MHz
RF OUTPUT Modulation Input
Device Under Test DTS2070C
Digital Time Scope
Output CLKIN CLKOUT Input
Figure 8. Output Clock Jitter Test Setup
CLKIN
t
en
SHTDN
An
Dn
ValidInvalid
Figure 9. Enable Time Waveforms
CLKIN
CLKOUT
t
dis
SHTDN
Figure 10. Disable Time Waveforms
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
70
60
55
45
30 40 50 60 70
f
clk
– Clock Frequency – MHz
VCC = 3 V
VCC = 3.6 V
– Supply Current – mA
I
CC
80
40
50
65
75
Grayscale Data Pattern
CL = 8 pF
TA = 25°C
VCC = 3.3 V
Figure 11. RMS Grayscale ICC vs Clock Frequency
200
100
50
0
0 0.5 1 1.5
Zero-to-Peak Output Jitter – ps
250
300
ZERO-TO-PEAK OUTPUT JITTER
vs
MODULATION FREQUENCY
2 2.5 3
150
f
(mod)
– Modulation Frequency – MHz
VCC = 3.3 V
TA = 25°C
Input jitter = 750 sin (6.28 f
(mod)
t) ps
Figure 12. Typical FlatLink PLL Characteristics
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
RED0 RED0
RED1 RED1
RED2 RED2
RED3 RED3
NA RED4
NA RED5
GREEN0 GREEN0
GREEN1 GREEN1
GREEN2 GREEN2
GREEN3 GREEN3
NA GREEN4
NA GREEN5
BLUE0 BLUE0
BLUE1 BLUE1
BLUE2 BLUE2
BLUE3 BLUE3
NA BLUE4
NA BLUE5
H_SYNC H_SYNC
V_SYNC V_SYNC
ENABLE ENABLE
CLOCK CLOCK
12-BIT
18-BIT
Graphics Controller
SN75LVDS86SN75LVDS84/5
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKOUT
24
26
27
29
30
31
33
34
35
37
39
40
41
43
45
46
47
1
2
4
5
23
100 Ω
8
9
41
40
100 Ω
10
11
39
38
100 Ω
14
15
35
34
100 Ω
16
17
33
32
Cable Flat Panel DisplayHost
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
A0M
A0P
A1M
A1P
A2M
A2P
CLKINM
CLKINP
NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types.
B. NA – not applicable, these unused inputs should be left open.
Figure 13. 18-Bit Color Host to Flat Panel Display Application
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SN75LVDS86SN75LVDS81/83
100 Ω
8
9
48
47
100 Ω
10
11
46
45
100 Ω
14
15
42
41
16
17
100 Ω
40
39
Cable Flat Panel DisplayHost
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
A0M
A0P
A1M
A1P
A2M
A2P
CLKINM
CLKINP
RED0 RED0
RED1 RED1
RED2 RED2
RED3 RED3
NA RED4
NA RED5
GREEN0 GREEN0
GREEN1 GREEN1
GREEN2 GREEN2
GREEN3 GREEN3
NA GREEN4
NA GREEN5
BLUE0 BLUE0
BLUE1 BLUE1
BLUE2 BLUE2
BLUE3 BLUE3
NA BLUE4
NA BLUE5
H_SYNC H_SYNC
V_SYNC V_SYNC
ENABLE ENABLE
CLOCK CLOCK
12-BIT
18-BIT
Graphics Controller
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKOUT
24
26
27
29
30
31
33
34
35
37
39
40
41
43
45
46
47
1
2
4
5
23
38
37
Y3M
Y3P
NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types.
B. NA – not applicable, these unused inputs should be left open.
Figure 14. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application
†
†
See the
FlatLink Designer’s Guide
(SLLA012) for more application information.
SN75LVDS86
FLATLINK RECEIVER
SLLS268C – MARCH 1997 – REVISED MA Y 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PIN SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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