Texas Instruments SN75LVDS84DGG, SN75LVDS84DGGR, SN75LVDS85DGG, SN75LVDS85DGGR Datasheet

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

21:3 Data Channel Compression at up to
163 Million Bytes per Second Throughput

D

Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display
With V ery Low EMI

D

21 Data Channels Plus Clock In
Low-Voltage TTL and 3 Data Channels Plus
Clock Out Low-Voltage Differential

D

Operates From a Single 3.3-V Supply and
250 mW (Typ)

D

5-V Tolerant Data Inputs

D

ESD Protection Exceeds 6 kV

D

SN75LVDS84 Has Falling Clock-Edge
Triggered Inputs, SN75LVDS85 Has Rising
Clock-Edge-Triggered Inputs

D

Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch

D

Consumes Less Than 1 mW When Disabled

D

Wide Phase-Lock Input Frequency Range:

31 MHz to 68 MHz

D

No External Components Required for PLL

D

Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard

D

Improved Replacement for the DS90C561

description

The SN75L VDS84 and SN75L VDS85 FlatLink transmitters each contain three 7-bit parallel-load serial-out shift
registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single
integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be
synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as
the SN75L VDS82 or SN75LVDS86.

When transmitting, data bits D0 – D20 are each loaded into registers of the SN75L VDS84 upon the falling edge
and into the registers of the SN75L VDS85 on the rising edge of the input clock signal (CLKIN). The frequency
of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The
three serial streams and a phase-locked clock (CLKOUT) are then output to L VDS output drivers. The frequency
of CLKOUT is the same as the input clock, CLKIN.

AVAILABLE OPTIONS

†

LATCHING CLOCK EDGE

FALLING RISING

SN75LVDS84DGG
SN75LVDS84DGGR

SN75LVDS85DGG
SN75LVDS85DGGR

†

The R suffix indicates taped and reeled packaging.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FlatLink is a trademark of Texas Instruments Incorporated.

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34
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32
31
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28
27
26
25

D4

V

CC

D5
D6

GND

D7
D8

V

CC

D9

D10

GND

D11
D12

NC
D13
D14

GND

D15
D16
D17

V

CC

D18
D19

GND

D3
D2
GND
D1
D0
NC
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSV

CC

LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLV

CC

PLLGND
SHTDN
CLKIN
D20

DGG PACKAGE

(TOP VIEW)

NC – Not Connected

SN75LVDS84, SN75LVDS85
FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The SN75LVDS84 or SN75LVDS85 require no external components and little or no control. The data bus
appears the same at the input to the transmitter and output of the receiver with the data transmission transparent
to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input
to inhibit the clock and shut off the L VDS output drivers for lower power consumption. A low level on this signal
clears all internal registers to a low level.

The SN75LVDS84 and SN75LVDS85 are characterized for operation over ambient free-air temperatures of
0_C to 70_C.

functional block diagram

A,B, ...G
SHIFT/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

7

A,B, ...G
SHIFT/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

7

A,B, ...G
SHIFT/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

7

Control Logic

7×CLK

CLK

CLKINH

7× Clock/PLL

SHTDN

CLKIN

D14 – D20

D7 – D13

D0 – D6

Y0P
Y0M

Y1P
Y1M

Y2P
Y2M

CLKOUTP
CLKOUTM

SN75LVDS84 only

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKOUT

CLKIN

(’LVDS85)

D0

Y0

Y1

Y2

D0–1 D6 D5 D4 D3 D2 D1 D0 D6+1

D7–1 D13 D12 D11 D10 D9 D8 D7 D13+1

D14–1 D20 D19 D18 D17 D16 D15 D14 D20+1

Current Cycle

Next
Cycle

Previous Cycle

CLKIN

(’LVDS84)

Figure 1. Load and Shift Timing Sequences

schematics of input and output

V

CC

50 Ω

300 kΩ

7 V

D or

SHTDN

V

CC

7 V

10 kΩ

5 Ω

YnP or YnM

EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH OUTPUT

SN75LVDS84, SN75LVDS85
FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (all terminals) –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(all terminals) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GND terminals.

DISSIPATION RATING T ABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

‡

ABOVE TA = 25°C

TA = 70°C

POWER RATING

DGG 1316 mW 13.1 mW/°C 726 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board mounted and
with no air flow.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

3 3.3 3.6 V

High-level input voltage, V

IH

2 V

Low-level input voltage, V

IL

0.8 V

Differential load impedance, Z

L

90 132 Ω

Operating free-air temperature, T

A

0 70 °C

timing requirements

MIN NOM MAX UNIT

t

c

Input clock period 14.7 32.4 ns

t

w

Pulse duration, high-level input clock 0.4t

c

0.6t

c

ns

t

t

Transition time, input signal 5 ns

t

su

Setup time, data, D0 – D27 valid before CLKIN↓ (’84) or CLKIN↑ (’85) (See Figure 2) 3 ns

t

h

Hold time, data, D0 – D27 valid after CLKIN↓ (’84) or CLKIN↑ (’85) (See Figure 2) 1.5 ns

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IT

Input threshold voltage 1.4 V

|VOD| Differential steady-state output voltage magnitude

247 454 mV

∆|VOD|

Change in the steady-state differential output voltage
magnitude between opposite binary states

R

L

=

100 Ω

,

See Figure 3

50 mV

V

OC(SS)

Steady-state common-mode output voltage

1.125 1.375 V

V

OC(PP)

Peak-to-peak common-mode output voltage

See Figure 3

80 150 mV

I

IH

High-level input current VIH = V

CC

20 µA

I

IL

Low-level input current VIL = 0 ±10 µA

p

V

O(Yn)

= 0 ±24 mA

IOSShort-circuit output current

VOD = 0 ±12 mA

I

OZ

High-impedance output current VO = 0 to V

CC

±10 µA

Disabled,
All inputs at GND

280 µA

I

CC(AVG)

Quiescent supply current (average)

Enabled,
RL = 100 Ω (4 places)
Gray-scale pattern (see Figure 4),
VCC = 3.3 V,
tc = 15.38 ns

68 80 mA

Enabled,
RL = 100 Ω, (4 places)
Worst-case pattern (see Figure 5),
tc = 15.38 ns

75 100 mA

C

I

Input capacitance 3 pF

†

All typical values are at VCC = 3.3 V, TA = 25°C.