Datasheet SN75LVDS84DGG, SN75LVDS84DGGR, SN75LVDS85DGG, SN75LVDS85DGGR Datasheet (Texas Instruments)

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

21:3 Data Channel Compression at up to
163 Million Bytes per Second Throughput

D

Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display
With V ery Low EMI

D

21 Data Channels Plus Clock In
Low-Voltage TTL and 3 Data Channels Plus
Clock Out Low-Voltage Differential

D

Operates From a Single 3.3-V Supply and
250 mW (Typ)

D

5-V Tolerant Data Inputs

D

ESD Protection Exceeds 6 kV

D

SN75LVDS84 Has Falling Clock-Edge
Triggered Inputs, SN75LVDS85 Has Rising
Clock-Edge-Triggered Inputs

D

Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch

D

Consumes Less Than 1 mW When Disabled

D

Wide Phase-Lock Input Frequency Range:

31 MHz to 68 MHz

D

No External Components Required for PLL

D

Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard

D

Improved Replacement for the DS90C561

description

The SN75L VDS84 and SN75L VDS85 FlatLink transmitters each contain three 7-bit parallel-load serial-out shift
registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single
integrated circuit. These functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be
synchronously transmitted over three balanced-pair conductors for receipt by a compatible receiver, such as
the SN75L VDS82 or SN75LVDS86.

When transmitting, data bits D0 – D20 are each loaded into registers of the SN75L VDS84 upon the falling edge
and into the registers of the SN75L VDS85 on the rising edge of the input clock signal (CLKIN). The frequency
of CLKIN is multiplied seven times and then used to unload the data registers in 7-bit slices and serially. The
three serial streams and a phase-locked clock (CLKOUT) are then output to L VDS output drivers. The frequency
of CLKOUT is the same as the input clock, CLKIN.

AVAILABLE OPTIONS

†

LATCHING CLOCK EDGE

FALLING RISING

SN75LVDS84DGG
SN75LVDS84DGGR

SN75LVDS85DGG
SN75LVDS85DGGR

†

The R suffix indicates taped and reeled packaging.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FlatLink is a trademark of Texas Instruments Incorporated.

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2
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5
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7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

D4

V

CC

D5
D6

GND

D7
D8

V

CC

D9

D10

GND

D11
D12

NC
D13
D14

GND

D15
D16
D17

V

CC

D18
D19

GND

D3
D2
GND
D1
D0
NC
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSV

CC

LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLV

CC

PLLGND
SHTDN
CLKIN
D20

DGG PACKAGE

(TOP VIEW)

NC – Not Connected

SN75LVDS84, SN75LVDS85
FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The SN75LVDS84 or SN75LVDS85 require no external components and little or no control. The data bus
appears the same at the input to the transmitter and output of the receiver with the data transmission transparent
to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input
to inhibit the clock and shut off the L VDS output drivers for lower power consumption. A low level on this signal
clears all internal registers to a low level.

The SN75LVDS84 and SN75LVDS85 are characterized for operation over ambient free-air temperatures of
0_C to 70_C.

functional block diagram

A,B, ...G
SHIFT/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

7

A,B, ...G
SHIFT/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

7

A,B, ...G
SHIFT/LOAD

CLK

Parallel-Load 7-Bit

Shift Register

7

Control Logic

7×CLK

CLK

CLKINH

7× Clock/PLL

SHTDN

CLKIN

D14 – D20

D7 – D13

D0 – D6

Y0P
Y0M

Y1P
Y1M

Y2P
Y2M

CLKOUTP
CLKOUTM

SN75LVDS84 only

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

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CLKOUT

CLKIN

(’LVDS85)

D0

Y0

Y1

Y2

D0–1 D6 D5 D4 D3 D2 D1 D0 D6+1

D7–1 D13 D12 D11 D10 D9 D8 D7 D13+1

D14–1 D20 D19 D18 D17 D16 D15 D14 D20+1

Current Cycle

Next
Cycle

Previous Cycle

CLKIN

(’LVDS84)

Figure 1. Load and Shift Timing Sequences

schematics of input and output

V

CC

50 Ω

300 kΩ

7 V

D or

SHTDN

V

CC

7 V

10 kΩ

5 Ω

YnP or YnM

EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH OUTPUT

SN75LVDS84, SN75LVDS85
FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

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absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (all terminals) –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(all terminals) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GND terminals.

DISSIPATION RATING T ABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

‡

ABOVE TA = 25°C

TA = 70°C

POWER RATING

DGG 1316 mW 13.1 mW/°C 726 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board mounted and
with no air flow.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

3 3.3 3.6 V

High-level input voltage, V

IH

2 V

Low-level input voltage, V

IL

0.8 V

Differential load impedance, Z

L

90 132 Ω

Operating free-air temperature, T

A

0 70 °C

timing requirements

MIN NOM MAX UNIT

t

c

Input clock period 14.7 32.4 ns

t

w

Pulse duration, high-level input clock 0.4t

c

0.6t

c

ns

t

t

Transition time, input signal 5 ns

t

su

Setup time, data, D0 – D27 valid before CLKIN↓ (’84) or CLKIN↑ (’85) (See Figure 2) 3 ns

t

h

Hold time, data, D0 – D27 valid after CLKIN↓ (’84) or CLKIN↑ (’85) (See Figure 2) 1.5 ns

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IT

Input threshold voltage 1.4 V

|VOD| Differential steady-state output voltage magnitude

247 454 mV

∆|VOD|

Change in the steady-state differential output voltage
magnitude between opposite binary states

R

L

=

100 Ω

,

See Figure 3

50 mV

V

OC(SS)

Steady-state common-mode output voltage

1.125 1.375 V

V

OC(PP)

Peak-to-peak common-mode output voltage

See Figure 3

80 150 mV

I

IH

High-level input current VIH = V

CC

20 µA

I

IL

Low-level input current VIL = 0 ±10 µA

p

V

O(Yn)

= 0 ±24 mA

IOSShort-circuit output current

VOD = 0 ±12 mA

I

OZ

High-impedance output current VO = 0 to V

CC

±10 µA

Disabled,
All inputs at GND

280 µA

I

CC(AVG)

Quiescent supply current (average)

Enabled,
RL = 100 Ω (4 places)
Gray-scale pattern (see Figure 4),
VCC = 3.3 V,
tc = 15.38 ns

68 80 mA

Enabled,
RL = 100 Ω, (4 places)
Worst-case pattern (see Figure 5),
tc = 15.38 ns

75 100 mA

C

I

Input capacitance 3 pF

†

All typical values are at VCC = 3.3 V, TA = 25°C.

SN75LVDS84, SN75LVDS85
FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

†

MAX UNIT

t

d0

Delay time, CLKOUT↑ to serial bit
position 0

–0.2 0 0.2 ns

t

d1

Delay time, CLKOUT↑ to serial bit
position 1

1
7

tc*

0.2

1
7

tc)

0.2

ns

t

d2

Delay time, CLKOUT↑ to serial bit
position 2

2
7

tc*

0.2

2
7

tc)

0.2

ns

t

d3

Delay time, CLKOUT↑ to serial bit
position 3

tc = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps‡,

3
7

tc*

0.2

3
7

tc)

0.2

ns

t

d4

Delay time, CLKOUT↑ to serial bit
position 4

See Figure 6

4
7

tc*

0.2

4
7

tc)

0.2

ns

t

d5

Delay time, CLKOUT↑ to serial bit
position 5

5
7

tc*

0.2

5
7

tc)

0.2

ns

t

d6

Delay time, CLKOUT↑ to serial bit
position 6

6
7

tc*

0.2

6
7

tc)

0.2

ns

t

sk(o)

Output skew,

tn*

n
7

t

c

–0.2 0.2 ns

t

d7

Delay time, CLKIN↓ to CLKOUT↑

tc = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps‡,
See Figure 6

4.2 ns

tc = 15.38 + 0.75 sin (2π500E3t) ± 0.05 ns,
See Figure 7

±70 ps

∆t

c(o)

Cycl

e time, Output clock jitter

§

tc = 15.38 + 0.75 sin (2π3E6t) ± 0.05 ns,
See Figure 7

±187 ps

t

w

Pulse duration, high-level output clock

4
7

t

c

ns

t

t

Transition time, differential output
voltage (tr or tf)

See Figure 3 260 700 1500 ps

t

en

Enable time, SHTDN↑ to phase lock
(Yn valid)

See Figure 8 1 ms

t

dis

Disable time, SHTDN↓ to off state
(CLKOUT low)

See Figure 9 250 ns

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

|Input clock jitter| is the magnitude of the change in the input clock period.

§

Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Dn

t

su

t

h

CLKIN

(’LVDS85)

CLKIN

(’LVDS84)

NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns.

Figure 2. Setup and Hold Time Definition

CL = 10 pF Max
(2 Places)

49.9 Ω ± 1% (2 Places)

V

OC

V

OD

YP

YM

V

OD(H)

V

OC(SS)

V

OC(SS)

V

OD(L)

100%
80%

20%
0%

0 V

V

OC(PP)

t

r

t

f

0 V

(a) SCHEMATIC

(b) WAVEFORMS

NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making

measurements at YP or YM, the complementary output is similarly loaded.

Figure 3. Test Load and Voltage Definitions for LVDS Outputs

SN75LVDS84, SN75LVDS85
FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

CLKIN

D0, 6, 12

D1, 7, 13

D2, 8, 14

D3, 9, 15

D18, 19, 20

All others

NOTES: A. The 16-grayscale test-pattern test device power consumption for a typical display pattern.

B. VIH = 2 V and VIL = 0.8 V
C. SN75LVDS84 shown (CLKIN is inverted for SN75LVDS85).

Figure 4. 16-Grayscale Test-Pattern Waveforms

t

c

CLKIN

Even Dn

Odd Dn

NOTES: A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.

B. VIH = 2 V and VIL = 0.8 V
C. SN75LVDS84 shown (CLKIN is inverted for SN75LVDS85).

Figure 5. Worst-Case Test-Pattern Waveforms

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Yn

V

OD(H)

V

OD(L)

0 V

td0 – t

d6

t

d2

t

d3

t

d4

t

d5

t

d6

t

d7

CLKOUT

ÏÏ

t

d1

t

d0

≈ 0.5 V

1.4 V

t

d7

CLKIN

≈ 2.5 V

CLKOUT

or

Yn

CLKIN

(’LVDS85)

CLKIN

(’LVDS84)

Figure 6. Timing Definitions

Reference

VCO

Device

Under

Test

Modulation

∑

+

+

V(t) = A sin (2 π f

(mod)

t)

HP8656B

Signal Generator

0.1 MHz – 990 MHz

HP8665A

Synthesized Signal

Generator

0.1 MHz – 4200 MHz

RF Output Modulation Input

Device Under Test DTS2070C

Digital Time Scope

OUTPUT

CLKIN CLKOUT Input

Figure 7. Clock Jitter Test Setup

SN75LVDS84, SN75LVDS85
FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

CLKIN

t

en

SHTDN

Dn

Yn

ValidInvalid

NOTE A: SN75L VDS84 shown.

Figure 8. Enable Time Waveforms

CLKIN

CLKOUT

t

dis

SHTDN

NOTE A: SN75L VDS84 shown.

Figure 9. Disable Time Waveforms

Figure 10

AVERAGE SUPPLY CURRENT

vs

CLOCK FREQUENCY

70

60

50

45

40

30 40 50 60 70

f

clk

– Clock Frequency – MHz

VCC = 3.3 V

– Average Supply Current – mA

I

CC

55

65

75

VCC = 3.6 V

Grayscale Data Pattern
RL = 100 Ω
TA = 25°C

VCC = 3 V

Figure 11

60

40

0

0 0.5 1 1.5

Zero-to-Peak Output Jitter – ps

200

ZERO-TO-PEAK OUTPUT JITTER

vs

MODULATION FREQUENCY

2 2.5 3

100

f

(mod)

– Modulation Frequency – MHz

Input jitter = 750 sin (6.28 f

(mod)

t) ps
VCC = 3.3 V
TA = 25°C

20

80

120

140

160

180

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

RED0 RED0
RED1 RED1
RED2 RED2
RED3 RED3
NA RED4
NA RED5
GREEN0 GREEN0
GREEN1 GREEN1
GREEN2 GREEN2
GREEN3 GREEN3
NA GREEN4
NA GREEN5
BLUE0 BLUE0
BLUE1 BLUE1
BLUE2 BLUE2
BLUE3 BLUE3
NA BLUE4
NA BLUE5
H_SYNC H_SYNC
V_SYNC V_SYNC
ENABLE ENABLE
CLOCK CLOCK

12-BIT

18-BIT

Graphics Controller

SN75LVDS84 SN75LVDS86

100 Ω

8

9

41

40

100 Ω

10

11

39

38

100 Ω

14

15

35

34

100 Ω

16

17

33

32

Cable Flat Panel DisplayHost

A0M

A0P

A1M

A1P

A2M

A2P

CLKINM

CLKINP

Y0M

Y0P

Y1M

Y1P

Y2M

Y2P

CLKOUTM

CLKOUTP

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKIN

44
45
47
48

1
3
4
6
7

9
10
12
13
15
16
18
19
20
22
23
25
26

NOTES: A. The five 100-Ω terminating resistors are recommended to be 0603 types.

B. NA – not applicable, these unused inputs should be left open.

Figure 12. Color Host to LCD Panel Application

SN75LVDS84, SN75LVDS85
FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

RED0 RED0
RED1 RED1
RED2 RED2
RED3 RED3
NA RED4
NA RED5
GREEN0 GREEN0
GREEN1 GREEN1
GREEN2 GREEN2
GREEN3 GREEN3
NA GREEN4
NA GREEN5
BLUE0 BLUE0
BLUE1 BLUE1
BLUE2 BLUE2
BLUE3 BLUE3
NA BLUE4
NA BLUE5
H_SYNC H_SYNC
V_SYNC V_SYNC
ENABLE ENABLE
CLOCK CLOCK

12-BIT

18-BIT

Graphics Controller

SN75LVDS84 SN75LVDS82

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKIN

44
45
47
48

1
3
4
6
7

9
10
12
13
15
16
18
19
20
22
23
25
26

100 Ω

9

10

41

40

100 Ω

11

12

39

38

100 Ω

15

16

35

34

33

32

100 Ω

Cable Flat Panel DisplayHost

A0M

A0P

A1M

A1P

A2M

A2P

CLKINM

CLKINP

Y0M

Y0P

Y1M

Y1P

Y2M

Y2P

CLKOUTM

CLKOUTP

100 Ω

A3M

A3P

NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types.

B. NA – not applicable, these unused inputs should be left open.

Figure 13. 18-Bit Color Host to 24-Bit LCD Display Panel Application

†

†

See the FlatLink Designer’s Guide (SLLA012) for more application information.

SN75LVDS84, SN75LVDS85

FLATLINK TRANSMITTERS

SLLS270C – MARCH 1997 – REVISED NOVEMBER 1999

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040078/F 12/97

48 PIN SHOWN

0,25

0,15 NOM

Gage Plane

6,00

6,20

8,30
7,90

0,75
0,50

Seating Plane

25

0,27
0,17

24

A

48

1

1,20 MAX

M

0,08

0,10

0,50

0°–8°

56

14,10

13,90

48

DIM

A MAX

A MIN

PINS **

12,40

12,60

64

17,10

16,90

0,15
0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright  1999, Texas Instruments Incorporated