Texas Instruments SN75LVDS83BDGG, SN75LVDS83BZQL Schematic [ru]

swivel

SN75LVDS83B

FlatLink Transmitter

TM

PackageOptions
TSSOP:8x14mmDGG
BGA:4.5x7mm

Application

processor

(e.g.OMAP )

TM

SN75LVDS83B

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FLATLINK™ TRANSMITTER

Check for Samples: SN75LVDS83B

1

FEATURES

2

• LVDS Display Serdes Interfaces Directly to
LCD Display Panels with Integrated LVDS

• Package Options: 4.5mm x 7mm BGA, and

8.1mm x 14mm TSSOP

• 1.8V up to 3.3V Tolerant Data Inputs to
Connect Directly to Low-Power, Low-Voltage
Application and Graphic Processors

• Transfer Rate up to 135Mpps (Mega Pixel Per
Second); Pixel Clock Frequency Range 10MHz
to 135MHz

• Suited for Display Resolutions Ranging From
HVGA up to HD With Low EMI

• Operates From a Single 3.3V Supply and
170mW (typ.) at 75MHz

• 28 Data Channels Plus Clock In Low-Voltage
TTL to 4 Data Channels Plus Clock Out Low-

SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

Voltage Differential

• Consumes Less Than 1mW When Disabled

• Selectable Rising or Falling Clock Edge
Triggered Inputs

• ESD: 5kV HBM

• Support Spread Spectrum Clocking (SSC)

• Compatible with all OMAP™2x, OMAP™3x,
and DaVinci™ Application Processors

APPLICATIONS

• LCD Display Panel Driver

• UMPC and Netbook PC

• Digital Picture Frame

DESCRIPTION

The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock
synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These
functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair
conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS
receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The
frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and
serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers.
The frequency of CLKOUT is the same as the input clock, CLKIN.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2OMAP, DaVinci, FlatLink are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2009–2011, Texas Instruments Incorporated

SN75LVDS83B

SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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DESCRIPTION (CONTINUED)

The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at
the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The
only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a
low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the
clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all
internal registers to a low-level.

The SN75LVDS83B is characterized for operation over ambient air temperatures of -10°C to 70°C.
Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock

frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.

ORDERING INFORMATION

PART NUMBER PART MARKING PACKAGE

SN75LVDS83BZQLR LVDS83B in BGA package 56-pin ZQL LARGE T&R

SN75LVDS83BDGG LVDS83B in TSSOP package 56-pin DGG TUBE

SN75LVDS83BDGGR LVDS83B in TSSOP package 56-pin DGG LARGE T&R

(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or

refer to our web site at www.ti.com.

(1)

ABSOLUTE MAXIMUM RATINGS

Supply voltage range, VCC, IOVCC, LVDSVCC, PLLVCC
Voltage range at any output terminal -0.5 to VCC + 0.5 V
Voltage range at any input terminal -0.5 to IOVCC + 0.5 V
Continuous power dissipation See the dissipation rating table
Storage temperature, T

ESD rating Charged Device Model (CDM)

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.
(2) All voltages are with respect to the GND terminals.
(3) In accordance with JEDEC Standard 22, Test Method A114-A.
(4) In accordance with JEDEC Standard 22, Test Method C101.
(5) In accordance with JEDEC Standard 22, Test Method A115-A.

s

Human Body Model (HBM)

Machine Model (MM)

(5)

(1)

VALUE UNIT

(2)

(3)

all pins 5 kV

(4)

all pins 500 V

all pins 150 V

-0.5 to 4 V

–65 to 150 °C

2 Copyright © 2009–2011, Texas Instruments Incorporated

SN75LVDS83B

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SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN NOM MAX UNIT

Supply voltage, VCC 3 3.3 3.6
LVDS output Supply voltage, LVDSVCC 3 3.3 3.6
PLL analog supply voltage, PLLVCC 3 3.3 3.6 V
IO input reference supply voltage, IOVCC 1.62 1.8 / 2.5 / 3.3 3.6
Power supply noise on any VCC terminal 0.1

IOVCC = 1.8V IOVCC/2 + 0.3V

High-level input voltage, V

Low-level input voltage, V

Differential load impedance, Z

IH

IL

L

Operating free-air temperature, T

A

IOVCC = 2.5V IOVCC/2 + 0.4V V
IOVCC = 3.3V IOVCC/2 + 0.5V
IOVCC = 1.8V IOVCC/2 - 0.3V
IOVCC = 2.5V IOVCC/2 - 0.4V V
IOVCC = 3.3V IOVCC/2 - 0.5V

90 132 Ω

-10 70 C

DISSIPATION RATINGS

PACKAGE CIRCUIT BOARD MODEL

DGG 1111mW 12.3mW/°C 555mW

ZQL 1034mW 11.5mW/°C 517mW

(3)

DGG

ZQL 2000mW 22mW/°C 1000mW

Low-K

High-K

(1)

TJA≤ 25°C

1730mW 19mW/°C 865mW

DERATING FACTOR

ABOVE TJA= 25°C POWER RATING

(1) In accordance with the High-K and Low-K thermal metric definitions of EIA/JESD51-2.
(2) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(3) DGG junction to case thermal reistance (θJC) is 15.4°C/W.

(2)

TJA= 70°C

TIMING REQUIREMENTS

PARAMETER MIN MAX UNIT

Input clock period, t

Input clock modulation

High-level input clock pulse width duration, t
Input signal transition time, t

c

with modulation frequency 30kHz 8%
with modulation frequency 50kHz 6%

w

t

Data set up time, D0 through D27 before CLKIN (See Figure 3) 2 ns
Data hold time, D0 through D27 after CLKIN 0.8 ns

7.4 100 ns

0.4 t

c

0.6 t

c

3 ns

ns

Copyright © 2009–2011, Texas Instruments Incorporated 3

1

2
3

4

5

6

7

8

9

10

11

12

13

14
15

16

17
18

19

20

21

22
23

24

25

26

27

28 29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

IOVCC

VCC

LVDSVCC

GND

CLKSEL

D16

D15

D14

GND

CLKOUTM

D13

D17

D5

D6

D7

D8

D10

D11

D18

GND

D21

D23

D24

D2

D3

D4

GND
D1

D0

D27
GND

Y0M

GND

GND

PLLVCC
GND

SHTDN

CLKIN

D26
GND

GND

D9

D12

D19

D20

D22

IOVCC

D25

Y0P

Y1M

Y1P

Y2M

Y2P

Y3M

Y3P

CLKOUTP

SN75LVDS83B

SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

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DGG PACKAGE

(TOP VIEW)

4 Copyright © 2009–2011, Texas Instruments Incorporated

Pin # Signal Pin # Signal Pin # Signal Pin # Signal

1 IOVCC 15 D15 29 GND 43 GND
2 D5 16 D16 30 D26 44 LVDSVCC
3 D6 17 CLKSEL 31 CLKIN 45 Y1P
4 D7 18 D17 32 SHTDN 46 Y1M
5 GND 19 D18 33 GND 47 Y0P
6 D8 20 D19 34 PLLVCC 48 Y0M
7 D9 21 GND 35 GND 49 GND
8 D10 22 D20 36 GND 50 D27

9 VCC 23 D21 37 Y3P 51 D0
10 D11 24 D22 38 Y3M 52 D1
11 D12 25 D23 39 CLKOUTP 53 GND
12 D13 26 IOVCC 40 CLKOUTM 54 D2
13 GND 27 D24 41 Y2P 55 D3
14 D14 28 D25 42 Y2M 56 D4

DGG PIN LIST

13 2456

K

G

H

J

D

E

F

C

D13

D14

D16

D17

GND Y3M

D15

GND

GND

GND

Y1P

Y2P

LVDSVCC

Y1M

Y2M

GND

Y0M

CLKM

CLKSEL

D8

CLKP

Y0P

D12

D11

D19

D3

D1

D27D6

D7

GND

D4D5

D0

D2

Y3P

D18

B

A

D22

D20

D26

GND

GNDD24

D21

D23

SHTDND25

CLKIN

PLLVCC

IOVCC

IOVCC

VCC

GND

GND

D10

D9

SN75LVDS83B

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SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

ZQL PACKAGE

(TOP VIEW)

ZQL PIN LIST

Copyright © 2009–2011, Texas Instruments Incorporated 5

Ball # Signal Ball # Signal Ball # Signal

A1 GND A2 CLKIN A3 D26
A4 D24 A5 D23 A6 D22
B1 GND B2 PLLVCC B3 SHTDN
B4 D25 B5 D21 B6 D20
C1 Y3M C2 Y3P C3 GND
C4 IOVCC C5 GND C6 D19
D1 CLKM D2 CLKP D3 GND
D4 CLKSEL D5 D18 D6 D17
E1 Y2M E2 Y2P E3 ball not populated
E4 ball not populated E5 D15 E6 D16
F1 LVDSVCC F2 GND F3 ball not populated
F4 ball not populated F5 GND F6 D14
G1 Y1M G2 Y1P G3 GND
G4 IOVCC G5 D12 G6 D13
H1 Y0M H2 Y0P H3 GND
H4 D10 H5 VCC H6 D11
J1 D27 J2 D0 J3 D3
J4 D6 J5 GND J6 D9

SN75LVDS83B

SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

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ZQL PIN LIST (continued)

K1 D1 K2 D2 K3 D4
K4 D5 K5 D7 K6 D8

PIN FUNCTIONS

TERMINAL I/O DESCRIPTION

Y0P, Y0M, Y1P, Differential LVDS data outputs.
Y1M, Y2P, Y2M Outputs are high-impedance when SHTDN is pulled low (de-asserted)

Y3P, Y3M LVDS Out Output is high-impedance when SHTDN is pulled low (de-asserted).

CLKP, CLKM

D0 – D27

CMOS IN with

CLKIN Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL.
SHTDN

CLKSEL
VCC 3.3V digital supply voltage

IOVCC I/O supply reference voltage (1.8V up to 3.3V matching the GPU data output signal swing)
PLLVCC Power Supply
LVDSVCC 3.3V LVDS output analog supply
GND Supply ground for VCC, IOVCC, LVDSVCC, and PLLVCC.

(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals

directly to this plane.

pulldn

Differential LVDS Data outputs.
Note: if the application only requires 18-bit color, this output can be left open.

Differential LVDS pixel clock output.
Output is high-impedance when SHTDN is pulled low (de-asserted).

Data inputs; supports 1.8V to 3.3V input voltage selectable by VDD supply. To connect a graphic
source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily
intuitive).
For input bit assignment see Figure 14 to Figure 17 for details.
Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23,
and D27 to GND.

Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and
high (assert) for normal operation.

Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger
(CLKSEL = VIL).

(1)

3.3V PLL analog supply

6 Copyright © 2009–2011, Texas Instruments Incorporated

Parallel-Load7-bit

ShiftRegister

A,B,...G
SHIFT/LOAD
>CLK

7D0,D1,D2,D3,

D4,D6,D7

Y0P

Y0M

Parallel-Load7-bit

ShiftRegister

A,B,...G
SHIFT/LOAD
>CLK

7D8,D9,D12,D13,

D14,D15,D18

Y1P

Y1M

Parallel-Load7-bit

ShiftRegister

A,B,...G
SHIFT/LOAD
>CLK

7D19,D20,D21,D22,

D24,D25,D26

Y2P

Y2M

7XClock/PLL

7XCLK

>CLK

CLKINH

RISING/FALLINGEDGE

CLKIN

CLKOUTP
CLKOUTM

SHTDN

Parallel-Load7-bit

ShiftRegister

A,B,...G
SHIFT/LOAD
>CLK

7D27,D5,D10,D11,

D16, D17,D23

Y3P
Y3M

ControlLogic

CLKSEL

SN75LVDS83B

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SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

FUNCTIONAL BLOCK DIAGRAM

Copyright © 2009–2011, Texas Instruments Incorporated 7

D0-1

D8-1

D19-1

D27-1

D7

D18

D26

D23 D17

D25

D15

D6

D16

D24

D14

D4

D11

D22

D13

D3

D10

D21

D12

D2

D5

D20

D9

D1

D27

D19

D8

D0

D23+1

D26+1

D18+1

D7+1

Dn

CLKIN

CLKOUT

Y0

Y1

Y2

Y3

Previouscycle

Currentcycle

Next

CLKIN

or

7V

Dor

IOVCC

LVDSVCC

SHTDN

50W

7V

5W

YnP or
YnM

10kW

300kW

SN75LVDS83B

SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

Figure 1. Typical SN75LVDS83B Load and Shift Sequences

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Figure 2. Equivalent Input and Output Schematic Diagrams

8 Copyright © 2009–2011, Texas Instruments Incorporated

SN75LVDS83B

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SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

V

T

|VOD| 250 450

Δ|VOD| output voltage magnitude between 1 35 mV

V

OC(SS)

V

OC(PP)

I

IH

I

IL

I

OS

I

OZ

R

pdn

I

Q

I

CC

C

I

(1) All typical values are at VCC = 3.3V, TA= 25°C.

Input voltage threshold IOVCC/2 V
Differential steady-state output voltage mV

magnitude

RL= 100Ω, See Figure 4

Change in the steady-state differential
opposite binary states

Steady-state common-mode output
voltage

Peak-to-peak common-mode output

See Figure 4
t

(Dx, CLKin) = 1ns

R/F

1.125 1.375 V

voltage
High-level input current VIH= IOVCC 25 μA
Low-level input current VIL= 0 V ±10 μA

Short-circuit output current

VOY= 0 V ±24 mA
VOD= 0 V ±12 mA

High-impedance state output current VO= 0 V to VCC ±20 μA
Input pull-down integrated resistor on all

inputs (Dx, CLKSEL, SHTDN, CLKIN)

Quiescent current (average) 2 100 μA

IOVCC = 1.8V 200
IOVCC = 3.3V 100
disabled, all inputs at GND;

SHTDN = V

IL

SHTDN = VIH, RL= 100Ω (5 places),
grayscale pattern (Figure 5)
VCC = 3.3V, f

CLK

= 75MHz

I

(VCC)

I

(IOVCC)

I

(IOVCC)

+ I

+ I

(PLLVCC)

(LVDSVCC)

with IOVCC = 3.3V 0.4 mA
with IOVCC = 1.8V 0.1

SHTDN = VIH, RL= 100Ω (5 places), 50%
transition density pattern (Figure 5),
VCC = 3.3V, f

CLK

= 75MHz

I

(VCC)

I

(IOVCC)

I

(IOVCC)

+ I

+ I

(PLLVCC)

(LVDSVCC)

with IOVCC = 3.3V 0.6 mA
with IOVCC = 1.8V 0.2

SHTDN = VIH, RL= 100Ω (5 places), worst­case pattern (Figure 6),
VCC = 3.6V, f

Supply current (average)

CLK

= 75MHz

I

(VCC)

I

(IOVCC)

I

(IOVCC)

+ I

+ I

(PLLVCC)

(LVDSVCC)

with IOVCC = 3.3V 1.3 mA
with IOVCC = 1.8V 0.5

SHTDN = VIH, RL= 100Ω (5 places), worst­case pattern (Figure 6),
f

= 100MHz

CLK

I

(VCC)

I

(IOVCC)

I

(IOVCC)

+ I

+ I

(PLLVCC)

(LVDSVCC)

with IOVCC = 3.6V 1.6 mA
with IOVCC = 1.8V 0.6

SHTDN = VIH, RL= 100Ω (5 places), worst­case pattern (Figure 6),
f

= 135MHz

CLK

I

(VCC)

I

(IOVCC)

I

(IOVCC)

+ I

+ I

(PLLVCC)

(LVDSVCC)

with IOVCC = 3.6V 2.1 mA
with IOVCC = 1.8V 0.8

Input capacitance 2 pF

51.9

53.3

63.7

81.6

102.2

(1)

MAX UNIT

35 mV

kΩ

Copyright © 2009–2011, Texas Instruments Incorporated 9

SN75LVDS83B

SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

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SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

4

±26

±44

±35

±42

/7t

(1)

1

2

3

4

5

6

c

c

MAX UNIT

/7tc+ 0.1 ns

/7tc+ 0.1 ns

/7tc+ 0.1 ns

/7tc+ 0.1 ns

/7tc+ 0.1 ns

/7tc+ 0.1 ns

ns

ps

ns

PARAMETER TEST CONDITIONS MIN TYP

Delay time, CLKOUT↑ after Yn valid

t

t

t

t

t

t

t

t

0

1

2

3

4

5

6

c(o)

(serial bit position 0, equal D1, D9, -0.1 0 0.1 ns
D20, D5)

Delay time, CLKOUT↑ after Yn valid
(serial bit position 1, equal D0, D8,

1

/7tc- 0.1

D19, D27)
Delay time, CLKOUT↑ after Yn valid

(serial bit position 2, equal D7, D18,

2

/7tc- 0.1

D26. D23)
Delay time, CLKOUT↑ after Yn valid

(serial bit position 3; equal D6, D15,
D25, D17)

Delay time, CLKOUT↑ after Yn valid
(serial bit position 4, equal D4, D14,

See Figure 7, tC= 10ns,
|Input clock jitter| < 25ps

3

(2)

/7tc- 0.1

4

/7tc- 0.1

D24, D16)
Delay time, CLKOUT↑ after Yn valid

(serial bit position 5, equal D3, D13,

5

/7tc- 0.1

D22, D11)
Delay time, CLKOUT↑ after Yn valid

(serial bit position 6, equal D2, D12,

6

/7tc- 0.1

D21, D10)
Output clock period t

tC= 10ns; clean reference clock, see

Figure 8

tC= 10ns with 0.05UI added noise
modulated at 3MHz, see Figure 8

Δt

c(o)

Output clock cycle-to-cycle jitter

(3)

tC= 7.4ns; clean reference clock,
see Figure 8

tC= 7.4ns with 0.05UI added noise
modulated at 3MHz, see Figure 8

t

w

t

r/f

t

en

t

dis

High-level output clock pulse
duration

Differential output voltage transition
time (tror tf)

Enable time, SHTDN↑ to phase lock
(Yn valid)

Disable time, SHTDN↓ to off-state
(CLKOUT high-impedance)

See Figure 4 225 500 ps

f

= 135MHz, See Figure 9 6 µs

(clk)

f

= 135MHz, See Figure 10 7 ns

(clk)

(1) All typical values are at VCC= 3.3 V, TA= 25°C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed

over 15,000 cycles.Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.

THERMAL CHARACTERISTICS

PARAMETER TEST CONDITIONS UNIT

Junction-to-free-air

θ

JA

thermal resistance

Junction-to-case

θ

JC

thermal resistance
Junction-to-board

θ

JB

thermal resistance
Junction-to-top of

ψ

JT

package

Low-K JEDEC test board, 1s (single signal layer), no air flow 85
High-K JEDEC test board, 2s2p (double signal layer, double

buried power plane), no air flow
Cu cold plate measurement process 25.2 15.9 °C/W

EIA/JESD 51-8 31.0 32.5 °C/W

EIA/JESD 51-2 0.8 0.4 °C/W

10 Copyright © 2009–2011, Texas Instruments Incorporated

ZQL DGG

MIN TYP MAX MIN TYP MAX

67.1 63.4

°C/W