Texas Instruments SN75LVDS82DGG, SN75LVDS82DGGR Datasheet

SN75LVDS82

FLATLINK RECEIVER

SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

4:28 Data Channel Expansion at up to 227.5
Million Bytes per Second (Mbytes/s)
Throughput

D

Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI

D

4 Data Channels and Clock Low-Voltage
Differential Channels In and 28 Data and
Clock Low-Voltage TTL Channels Out

D

Operates From a Single 3.3-V Supply With
250 mW Typ

D

5-V Tolerant SHTDN Input

D

Falling Clock-Edge-Triggered Outputs

D

Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch

D

Consumes Less Than 1 mW When Disabled

D

Wide Phase-Lock Input Frequency
Range...31 MHz to 68 MHz

D

No External Components Required for PLL

D

Inputs Meet or Exceed the Requirements of
the ANSI EIA/TIA-644 Standard

D

Improved Replacement for the National
DS90C582

description

The SN75LVDS82 FlatLink receiver contains
four serial-in 7-bit parallel-out shift registers, a 7×
clock synthesizer, and five low-voltage dif ferential
signaling (LVDS) line receivers in a single
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the
SN75LVDS81, over five balanced-pair conductors and expansion to 28 bits of single-ended low-voltage TTL
(L VTTL) synchronous data at a lower transfer rate. The SN75L VDS82 can also be used with the SN75L VDS84
or SN75LVDS85 for 21-bit transfers.

When receiving, the high-speed L VDS data is received and loaded into registers at the rate of seven times (7×)
the L VDS input clock (CLKIN). The data is then unloaded to a 28-bit wide L VTTL parallel bus at the CLKIN rate.
A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for
the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).

The SN75L VDS82 requires only five line-termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear
(SHTDN

) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A

low-level on SHTDN

clears all internal registers to a low level.

The SN75LVDS82 is characterized for operation over ambient air temperatures of 0_C to 70_C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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32
31
30
29

D22
D23
D24

GND

D25
D26
D27

L VDSGND

A0M

A0P

A1M

A1P

L VDSV

CC

L VDSGND

A2M

A2P

CLKINM

CLKINP

A3M

A3P

L VDSGND

PLLGND

PLL V

CC

PLLGND

SHTDN

CLKOUT

D0

GND

V

CC

D21
D20
D19
GND
D18
D17
D16
V

CC

D15
D14
D13
GND
D12
D11
D10
V

CC

D9
D8
D7
GND
D6
D5
D4
D3
V

CC

D2
D1

DGG PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1999, Texas Instruments Incorporated

FlatLink is a registered trademark of Texas Instruments Incorporated.

SN75LVDS82
FLATLINK RECEIVER

SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Serial In

CLK

Serial-In/Parallel-

Out Shift Register

Serial In

CLK

Serial In

CLK

Serial In

CLK

Control Logic

7× CLK
Clock In

7× Clock/PLL

SHTDN

CLKINP

A4P

A4M

A3P

A3M

A2P

A2M

A1P

A1M

CLKOUT

CLKINM

D27
D5
D10
D11
D16
D17
D23

D19
D20
D21
D22
D24
D25
D26

D8
D9
D12
D13
D14
D15
D18

D0
D1
D2
D3
D4
D6
D7

A, B, ...G

Clock Out

A, B, ...G

A, B, ...G

A, B, ...G

Serial-In/Parallel-

Out Shift Register

Serial-In/Parallel-

Out Shift Register

Serial-In/Parallel-

Out Shift Register

Input Bus

SN75LVDS82

FLATLINK RECEIVER

SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLKOUT

CLKIN

D0

A0

A1

A2

A3

D0–1 D7 D6 D4 D3 D2 D1 D0 D7+1

D8–1 D18 D15 D14 D13 D12 D9 D8 D18+1

D19–1 D26 D25 D24 D22 D21 D20 D19 D26+1

D27–1 D23 D17 D16 D11 D10 D5 D27 D23+1

Current CyclePrevious Cycle Next Cycle

Dn – 1 Dn Dn + 1

Figure 1. SN75LVDS82 Load and Shift Timing Sequences

equivalent input and output schematic diagrams

V

CC

50 Ω

300 kΩ

7 V

SHTDN

V

CC

7 V

5 Ω

D Output

INPUT

OUTPUT

V

CC

300 kΩ

AnM

7 V

7 V

300 kΩ

AnP

INPUT

SN75LVDS82
FLATLINK RECEIVER

SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, V

CC

(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (Dxx terminals) –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(any terminal except SHTDN) –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(SHTDN) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation (see Dissipation Rating Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating temperature range, T

A

0_C to 70_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to GND unless otherwise noted.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

‡

ABOVE TA = 25°C

TA = 70°C

POWER RATING

DGG 1377 mW 11.0 mW/°C 822 mW

‡

This is the inverse of the junction-to ambient thermal resistance when board-mounted and with no air flow.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

3 3.3 3.6 V
High-level input voltage, VIH (SHTDN) 2 V
Low-level input voltage, VIL (SHTDN) 0.8 V
Differential input voltage, |VID| 0.1 0.6 V

Common-mode input voltage, VIC (see Figure 2 and Figure 3)

|VID|

2

2.4

*

|VID|

2

V

VCC – 0.8

Operating free-air temperature, T

A

0 70 °C

timing requirements

MIN NOM MAX UNIT

t

c

Cycle time, input clock

§

14.7 32.4 ns

t

su1

Setup time, input (see Figure 7) 600 ps

t

h1

Hold time, input (see Figure 7) 600 ps

§

Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles.

SN75LVDS82

FLATLINK RECEIVER

SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IT+

Positive-going differential input threshold voltage 100 mV

V

IT–

Negative-going differential input threshold voltage

‡

–100 mV

V

OH

High-level output voltage IOH = –4 mA 2.4 V

V

OL

Low-level output voltage IOL = 4 mA 0.4 V

Disabled,
All inputs open

280 µA

Enabled,
AnP = 1 V,
AnM = 1.4 V ,
tc = 15.38 ns

60 74 mA

I

CC

Quiescent current (average)

Enabled,
CL = 8 pF,
Grayscale pattern (see Figure 4),
tc = 15.38 ns

74 mA

Enabled,
CL = 8 pF,
Worst-case pattern (see Figure 5)
tc = 15.38 ns

107 mA

I

IH

High-level input current (SHTDN) VIH = V

CC

±20 µA

I

IL

Low-level input current (SHTDN) VIL = 0 ±20 µA

I

IN

Input current (LVDS input terminals A and CLKIN) 0 ≤ VI ≤ 2.4 V ±20 µA

I

OZ

High-impedance output current VO = 0 or V

CC

±10 µA

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

The algebraic convention, in which the less-positive (more-negative) limit is designed minimum, is used in this data sheet for the negative-going
input voltage threshold only.