SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
4:28 Data Channel Expansion at up to 227.5
Million Bytes per Second (Mbytes/s)
Throughput
D
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
D
4 Data Channels and Clock Low-Voltage
Differential Channels In and 28 Data and
Clock Low-Voltage TTL Channels Out
D
Operates From a Single 3.3-V Supply With
250 mW Typ
D
5-V Tolerant SHTDN Input
D
Falling Clock-Edge-Triggered Outputs
D
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
D
Consumes Less Than 1 mW When Disabled
D
Wide Phase-Lock Input Frequency
Range...31 MHz to 68 MHz
D
No External Components Required for PLL
D
Inputs Meet or Exceed the Requirements of
the ANSI EIA/TIA-644 Standard
D
Improved Replacement for the National
DS90C582
description
The SN75LVDS82 FlatLink receiver contains
four serial-in 7-bit parallel-out shift registers, a 7×
clock synthesizer, and five low-voltage dif ferential
signaling (LVDS) line receivers in a single
integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the
SN75LVDS81, over five balanced-pair conductors and expansion to 28 bits of single-ended low-voltage TTL
(L VTTL) synchronous data at a lower transfer rate. The SN75L VDS82 can also be used with the SN75L VDS84
or SN75LVDS85 for 21-bit transfers.
When receiving, the high-speed L VDS data is received and loaded into registers at the rate of seven times (7×)
the L VDS input clock (CLKIN). The data is then unloaded to a 28-bit wide L VTTL parallel bus at the CLKIN rate.
A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for
the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).
The SN75L VDS82 requires only five line-termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear
(SHTDN
) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A
low-level on SHTDN
clears all internal registers to a low level.
The SN75LVDS82 is characterized for operation over ambient air temperatures of 0_C to 70_C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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21
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24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
D22
D23
D24
GND
D25
D26
D27
L VDSGND
A0M
A0P
A1M
A1P
L VDSV
CC
L VDSGND
A2M
A2P
CLKINM
CLKINP
A3M
A3P
L VDSGND
PLLGND
PLL V
CC
PLLGND
SHTDN
CLKOUT
D0
GND
V
CC
D21
D20
D19
GND
D18
D17
D16
V
CC
D15
D14
D13
GND
D12
D11
D10
V
CC
D9
D8
D7
GND
D6
D5
D4
D3
V
CC
D2
D1
DGG PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
FlatLink is a registered trademark of Texas Instruments Incorporated.
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Serial In
CLK
Serial-In/Parallel-
Out Shift Register
Serial In
CLK
Serial In
CLK
Serial In
CLK
Control Logic
7× CLK
Clock In
7× Clock/PLL
SHTDN
CLKINP
A4P
A4M
A3P
A3M
A2P
A2M
A1P
A1M
CLKOUT
CLKINM
D27
D5
D10
D11
D16
D17
D23
D19
D20
D21
D22
D24
D25
D26
D8
D9
D12
D13
D14
D15
D18
D0
D1
D2
D3
D4
D6
D7
A, B, ...G
Clock Out
A, B, ...G
A, B, ...G
A, B, ...G
Serial-In/Parallel-
Out Shift Register
Serial-In/Parallel-
Out Shift Register
Serial-In/Parallel-
Out Shift Register
Input Bus
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLKOUT
CLKIN
D0
A0
A1
A2
A3
D0–1 D7 D6 D4 D3 D2 D1 D0 D7+1
D8–1 D18 D15 D14 D13 D12 D9 D8 D18+1
D19–1 D26 D25 D24 D22 D21 D20 D19 D26+1
D27–1 D23 D17 D16 D11 D10 D5 D27 D23+1
Current CyclePrevious Cycle Next Cycle
Dn – 1 Dn Dn + 1
Figure 1. SN75LVDS82 Load and Shift Timing Sequences
equivalent input and output schematic diagrams
V
CC
50 Ω
300 kΩ
7 V
SHTDN
V
CC
7 V
5 Ω
D Output
INPUT
OUTPUT
V
CC
300 kΩ
AnM
7 V
7 V
300 kΩ
AnP
INPUT
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (Dxx terminals) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(any terminal except SHTDN) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(SHTDN) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation (see Dissipation Rating Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating temperature range, T
A
0_C to 70_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND unless otherwise noted.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DGG 1377 mW 11.0 mW/°C 822 mW
‡
This is the inverse of the junction-to ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
3 3.3 3.6 V
High-level input voltage, VIH (SHTDN) 2 V
Low-level input voltage, VIL (SHTDN) 0.8 V
Differential input voltage, |VID| 0.1 0.6 V
Common-mode input voltage, VIC (see Figure 2 and Figure 3)
|VID|
2
2.4
*
|VID|
2
V
VCC – 0.8
Operating free-air temperature, T
A
0 70 °C
timing requirements
MIN NOM MAX UNIT
t
c
Cycle time, input clock
§
14.7 32.4 ns
t
su1
Setup time, input (see Figure 7) 600 ps
t
h1
Hold time, input (see Figure 7) 600 ps
§
Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles.
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IT+
Positive-going differential input threshold voltage 100 mV
V
IT–
Negative-going differential input threshold voltage
‡
–100 mV
V
OH
High-level output voltage IOH = –4 mA 2.4 V
V
OL
Low-level output voltage IOL = 4 mA 0.4 V
Disabled,
All inputs open
280 µA
Enabled,
AnP = 1 V,
AnM = 1.4 V ,
tc = 15.38 ns
60 74 mA
I
CC
Quiescent current (average)
Enabled,
CL = 8 pF,
Grayscale pattern (see Figure 4),
tc = 15.38 ns
74 mA
Enabled,
CL = 8 pF,
Worst-case pattern (see Figure 5)
tc = 15.38 ns
107 mA
I
IH
High-level input current (SHTDN) VIH = V
CC
±20 µA
I
IL
Low-level input current (SHTDN) VIL = 0 ±20 µA
I
IN
Input current (LVDS input terminals A and CLKIN) 0 ≤ VI ≤ 2.4 V ±20 µA
I
OZ
High-impedance output current VO = 0 or V
CC
±10 µA
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
The algebraic convention, in which the less-positive (more-negative) limit is designed minimum, is used in this data sheet for the negative-going
input voltage threshold only.
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
t
su2
Setup time, D0 – D27 valid to CLKOUT↓
C
= 8 pF,
5 ns
t
h2
Hold time, CLKOUT↓ to D0 – D27 valid
L
,
See Figure 6
5 ns
t
RSKM
Receiver input skew margin‡ (see Figure 7)
tc = 15.38 ns (±0.2%),
|Input clock jitter| < 50 ps§,
490 ps
t
d
Delay time, CLKIN↑ to CLKOUT↓
(see Figure 7)
tc = 15.38 ns (±0.2%),
CL = 8 pF
3.7 ns
tc = 15.38 + 0.75 sin (2π500E3t) ±0.05 ns,
See Figure 8
±80
p
∆t
c(o)
Cycl
e time, change in output clock perio
d
¶
tc = 15.38 + 0.75 sin (2π3E6t) ±0.05 ns,
See Figure 8
±300
ps
t
en
Enable time, SHTDN↑ to Dn valid
See Figure 9 1 ms
t
dis
Disable time, SHTDN↓ to off state
See Figure 10 400 ns
t
t
Transition time, output (10% to 90% tr or tf) CL = 8 pF 3 ns
t
w
Pulse duration, output clock 0.43 t
c
ns
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
The parameter t
(RSKM)
is the timing margin available to the transmitter and interconnection skews and clock jitter. It is defined by
t
c
14
*
t
su1
ń
t
h1
§
|Input clock jitter| is the magnitude of the change in input clock period.
¶
∆t
c(o)
is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
ID
AP
AM
V
IAM
V
IAP
V
IC
(V
IAP
+ V
IAM
)/2
Figure 2. Voltage Definitions
0
2.5
2
1.5
1
0.5
0
0.1 0.2 0.3 0.4 0.5 0.6
|VID| – Differential Input Voltage – V
Maximum at 3 V V
CC
Maximum at VCC >3.15 V
Minimum
V
IC
– Common-Mode Input Voltage – V
Figure 3. Common-Mode Input Voltage Versus Differential Input Voltage
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
CLKOUT
D0, 8, 16
D1, 9, 17
D2, 10, 18
D3, 11, 19
D4–7, 12–15, 20–23
D24–27
NOTE A: The 16-grayscale test-pattern tests device power consumption for a typical display pattern.
Figure 4. 16-Grayscale Test-Pattern Waveforms
t
c
NOTE A: The worst-case test pattern produces the maximum switching frequency for all of the outputs.
CLKOUT
EVEN Dn
ODD Dn
Figure 5. Worst-Case Test-Pattern Waveforms
Dn
t
su2
CLKOUT
t
h2
70% V
OH
70% V
OH
30% V
OH
30% V
OH
Figure 6. Setup and Hold Time Waveforms
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Device
Under
Test (DUT)
CLKIN
Tektronix
HFS9003/HFS9DG1
Stimulus System
(repeating patterns of
F0FFFFF and 0F00000
Tektronix
Microwave Logic
Multi-BERT-100RX
Word Error Detector
An D0 – D27
CLKOUT
NOTE A: CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The magnitude of the advance or
delay is t
(RSKM)
.
An
CLKIN
t
c
CLKOUT
t
d
0 V
≈300 mV
≈–300 mV
90%
10%
tr < 1 ns
V
OL
V
OH
1.4 V
t
d
3
7
tc)
t
(RSKM)
t
h1
t
su1
4
7
tc)
t
(RSKM)
and An
7× CLK
(Internal)
CLKIN
or An
CLKOUT
t
w
Figure 7. Receiver Input Skew Margin and Delay Timing Waveforms
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Reference
VCO
Device
Under
Test
Modulation
∑
+
+
V(t) = A sin (2 π f
(mod)
t)
HP8656B
Signal Generator
0.1 MHz – 990 MHz
HP8665A
Synthesized Signal
Generator
0.1 MHz – 990 MHz
RF Output Modulation Input
Device Under Test DTS2070C
Digital Time Scope
RF OUTPUT CLKIN CLKOUT Input
Figure 8. Input Clock Jitter Test
CLKIN
t
en
SHTDN
An
Dn
ValidInvalid
Figure 9. Enable Time Waveforms
CLKIN
CLKOUT
t
dis
SHTDN
Figure 10. Disable Time Waveforms
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
70
60
55
45
30 40 50 60 70
f
clk
– Clock Frequency – MHz
VCC = 3 V
– Supply Current – mA
I
CC
80
40
50
65
75
Grayscale Data Pattern
CL = 8 pF
TA = 25°C
VCC = 3.3 V
85
VCC = 3.6 V
Figure 11
200
100
50
0
0 0.5 1 1.5
Zero-to-Peak Output Jitter – ps
250
300
ZERO-TO-PEAK OUTPUT JITTER
vs
MODULATION FREQUENCY
2 2.5 3
150
f
(mod)
– Modulation Frequency – MHz
VCC = 3.3 V
TA = 25°C
Input jitter = 750 sin (6.28 f
(mod)
t) ps
Figure 12
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
RED0 RED0 RED0
RED1 RED1 RED1
RED2 RED2 RED2
RED3 RED3 RED3
RSVD RED4 RED4
RSVD RED5 RED5
NA NA RED6
NA NA RED7
GREEN0 GREEN0 GREEN0
GREEN1 GREEN1 GREEN1
GREEN2 GREEN2 GREEN2
GREEN3 GREEN3 GREEN3
RSVD GREEN4 GREEN4
RSVD GREEN5 GREEN5
NA NA GREEN6
NA NA GREEN7
BLUE0 BLUE0 BLUE0
BLUE1 BLUE1 BLUE1
BLUE2 BLUE2 BLUE2
BLUE3 BLUE3 BLUE3
RSVD BLUE4 BLUE4
RSVD BLUE5 BLUE5
NA NA BLUE6
NA NA BLUE7
H_SYNC H_SYNC H_SYNC
V_SYNC V_SYNC V_SYNC
ENABLE ENABLE ENABLE
NA NA RSVD
CLOCK CLOCK CLOCK
12-BIT
18-BIT 24-BIT
Graphic Controller
SN75LVDS82SN75LVDS81
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKOUT
27
29
30
32
33
35
7
34
37
38
39
43
45
46
41
42
47
51
53
54
55
1
49
50
3
5
6
2
100 Ω
9
10
48
47
100 Ω
11
12
46
45
100 Ω
15
16
42
41
100 Ω
19
20
38
37
100 Ω
17
18
40
39
Cable Flat Panel DisplayHost
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
Y3M
Y3P
CLKOUTM
CLKOUTP
A0M
A0P
A1M
A1P
A2M
A2P
A3M
A3P
CLKINM
CLKINP
26
NOTES: A. The five 100-Ω terminating resistors are recommended to be 0603 types.
B. NA – not applicable, these unused inputs should be left open.
Figure 13. 24-Bit Color Host to 24-Bit LCD Flat Panel Display Application
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SN75LVDS82SN75LVDS84/85
100 Ω
9
10
41
40
100 Ω
11
12
39
38
100 Ω
15
16
35
34
19
20
100 Ω
17
18
40
39
Cable Flat Panel DisplayHost
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
A0M
A0P
A1M
A1P
A2M
A2P
A3M
A3P
CLKINM
CLKINP
RED0 RED0 RED0
RED1 RED1 RED1
RED2 RED2 RED2
RED3 RED3 RED3
RSVD RED4 RED4
RSVD RED5 RED5
NA NA RED6
NA NA RED7
GREEN0 GREEN0 GREEN0
GREEN1 GREEN1 GREEN1
GREEN2 GREEN2 GREEN2
GREEN3 GREEN3 GREEN3
RSVD GREEN4 GREEN4
RSVD GREEN5 GREEN5
NA NA GREEN6
NA NA GREEN7
BLUE0 BLUE0 BLUE0
BLUE1 BLUE1 BLUE1
BLUE2 BLUE2 BLUE2
BLUE3 BLUE3 BLUE3
RSVD BLUE4 BLUE4
RSVD BLUE5 BLUE5
NA NA BLUE6
NA NA BLUE7
H_SYNC H_SYNC H_SYNC
V_SYNC V_SYNC V_SYNC
ENABLE ENABLE ENABLE
NA NA RSVD
CLOCK CLOCK CLOCK
12-BIT
18-BIT 24-BIT
Graphic Controller
D0
D1
D2
D3
D4
D6
D27
D5
D7
D8
D9
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKOUT
27
29
30
32
33
35
7
34
37
38
39
43
45
46
41
42
47
51
53
54
55
1
49
50
3
5
6
2
26
NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types.
B. NA – not applicable, these unused inputs should be left open.
Figure 14. 18-Bit Color Host to 24-Bit Color LCD Panel Display Application
SN75LVDS82
FLATLINK RECEIVER
SLLS259D – NOVEMBER 1996 – REVISED MA Y 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PIN SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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