Texas Instruments SN75LVDS81DGG, SN75LVDS81DGGR Datasheet
SN75LVDS81
FLATLINK TRANSMITTER
SLLS258B – NOVEMBER 1996 – REVISED MA Y 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
28:4 Data Channel Compression at up to
227.5 Million Bytes per Second Throughput
D
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
D
28 Data Channels and Clock In Low-Voltage
TTL
D
4 Data Channels and Clock-Out
Low-Voltage Differential
D
Operates From a Single 3.3-V Supply With
250 mW (Typ)
D
5-V Tolerant Data Inputs
D
Falling Clock-Edge-Triggered Inputs
D
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
D
Consumes Less Than 1 mW When Disabled
D
Wide Phase-Lock Input Frequency
Range...31 MHz to 68 MHz
D
No External Components Required for PLL
D
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D
Improved Replacement for the National
DS90C581
description
The SN75LVDS81 FlatLink transmitter contains
four 7-bit parallel-load serial-out shift registers, a
7× clock synthesizer, and five low-voltage
differential-signaling (LVDS) line drivers in a
single integrated circuit. These functions allow
28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for
receipt by a compatible receiver, such as the SN75LVDS82. The SN75L VDS81 can also be used in 21-bit links
with the SN75LVDS86 receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the falling edge of the input
clock signal (CLKIN) The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data
registers in 7-bit slices and serially . The four serial streams and a phase-locked clock (CLKOUT) are then output
to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS81 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The
only user intervention is the possible use of the shutdown/clear (SHTDN
) active-low input to inhibit the clock
and shut off the LVDS output drivers for lower power consumption. A low-level on SHTDN
clears all internal
registers to a low level.
The SN75LVDS81 is characterized for operation over free-air temperature ranges of 0_C to 70_C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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V
CC
D5
D6
D7
GND
D8
D9
D10
V
CC
D11
D12
D13
GND
D14
D15
D16
NC
D17
D18
D19
GND
D20
D21
D22
D23
V
CC
D24
D25
D4
D3
D2
GND
D1
D0
D27
L VDSGND
Y0M
Y0P
Y1M
Y1P
L VDSV
CC
L VDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
Y3M
Y3P
L VDSGND
PLLGND
PLL V
CC
PLLGND
SHTDN
CLKIN
D26
GND
DGG PACKAGE
(TOP VIEW)
NC – Not Connected
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
FlatLink is a registered trademark of Texas Instruments Incorporated.
SN75LVDS81
FLATLINK TRANSMITTER
SLLS258B – NOVEMBER 1996 – REVISED MA Y 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
Control Logic
7×CLK
CLK
CLKINH
7× Clock/PLL
SHTDN
CLKIN
D5, D10, D11, D16,
D17, D23, D27
D19, D20, D21, D22,
D24, D25, D26
D8, D9, D12, D13,
D14, D15, D18
D0, D1, D2, D3,
D4, D6, D7
Y0P
Y0M
Y1P
Y1M
Y2P
Y2M
Y3P
Y3M
CLKOUTP
CLKOUTM
Input Bus
SN75LVDS81
FLATLINK TRANSMITTER
SLLS258B – NOVEMBER 1996 – REVISED MA Y 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLKOUT
CLKIN
D0
Y0
Y1
Y2
Y3
D0–1 D7 D6 D4 D3 D2 D1 D0 D7+1
D8–1 D18 D15 D14 D13 D12 D9 D8 D18+1
D19–1 D26 D25 D24 D22 D21 D20 D19 D26+1
D27–1 D23 D17 D16 D11 D10 D5 D27 D23+1
ÉÉÉ
Current Cycle
Next
Cycle
Previous Cycle
Figure 1. SN75LVDS81 Load and Shift Timing Sequences
equivalent input and output schematic diagrams
V
CC
50 Ω
300 kΩ
7 V
D or
SHTDN
V
CC
7 V
10 kΩ
5 Ω
YnP or YnM
INPUT OUTPUT
SN75LVDS81
FLATLINK TRANSMITTER
SLLS258B – NOVEMBER 1996 – REVISED MA Y 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) –0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(all terminals) –0.3 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(all terminals) –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation see Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
DGG 1377 mW 11.0 mW/°C 882 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
3 3.3 3.6 V
High-level input voltage, V
IH
2 V
Low-level input voltage, V
IL
0.8 V
Differential load impedance, Z
L
90 132 Ω
Operating free-air temperature, T
A
0 70 °C
timing requirements
MIN NOM MAX UNIT
t
c
Input clock cycle time 14.7 32.4 ns
t
w
High-level input clock pulse width duration 0.4t
c
0.6t
c
ns
t
t
Input signal transition time 5 ns
t
su
Data setup time, D0 – D27 before CLKIN↓ See Figure 2 3 ns
t
h
Data hold time, D0 – D27 valid after CLKIN↓ See Figure 2 1.5 ns
SN75LVDS81
FLATLINK TRANSMITTER
SLLS258B – NOVEMBER 1996 – REVISED MA Y 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IT
Input threshold voltage 1.4 V
|VOD| Differential steady-state output voltage magnitude
247 454 mV
∆|VOD|
Change in the steady-state differential output voltage
magnitude between opposite binary states
R
L
=
100 Ω
,
See Figure 3
50 mV
V
OC(SS)
Steady-state common-mode output voltage
1.125 1.375 V
V
OC(PP)
Peak-to-peak common-mode output voltage
See Figure 3
150 mV
I
IH
High-level input current VIH = V
CC
20 µA
I
IL
Low-level input current VIL = 0 ±10 µA
p
V
O(Yn)
= 0 ±24 mA
IOSShort-circuit output current
VOD = 0 ±12 mA
I
OZ
High-impedance state output current VO = 0 to V
CC
±10 µA
Disabled,
All inputs at GND
280 µA
I
CC
Quiescent supply current
Enabled,
RL = 100 Ω,
Gray-scale pattern (see Figure 4),
VCC = 3.3 V,
tc = 15.28 ns
72 80 mA
Enabled,
RL = 100 Ω,
Worst-case pattern (see Figure 5),
tc = 15.28 ns
85 110 mA
C
I
Input capacitance 3 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
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