Meets or Exceeds the Requirements of
ANSI TIA/EIA-644 Standard
D
Operates With a Single 3.3-V Supply
D
Designed for Signaling Rate of Up To
155 Mbps
D
Differential Input Thresholds ±100 mV Max
D
Low-Voltage TTL (LVTTL) Logic Output
Levels
D
Open-Circuit Fail Safe
D
Characterized For Operation From
0°C to 70°C
description
The SN75LVDS32 and SN75LVDS9637 are
differential line receivers that implement the
electrical characteristics of low-voltage differential
signaling (L VDS). This signaling technique lowers
SN75LVDS32D (Marked as 75LVDS32)
SN75LVDS9637D (Marked as DF637 or 7L9637)
1B
1A
1Y
2Y
2A
2B
GND
V
CC
1Y
2Y
GND
(TOP VIEW)
1
2
3
G
4
5
6
7
8
(TOP VIEW)
1
2
3
4
16
15
14
13
12
11
10
V
CC
4B
4A
4Y
G
3Y
3A
9
3B
1A
8
1B
7
2A
6
5
2B
the output voltage levels of 5-V differential
standard levels (such as EIA/TIA-422B) to reduce
the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state
with a ±100 mV allow operation with a differential input voltage within the input common-mode voltage range.
The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.
The intended application of these devices and signaling technique is both point-to-point and multidrop (one
driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The
transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance
of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.
The SN75LVDS32 and SN75LVDS9637 are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
logic diagram
’L VDS32 logic diagram
(positive logic)
4
G
12
G
2
1A
1
1B
6
2A
7
2B
10
3A
9
3B
14
4A
15
4B
DIFFERENTIAL INPUTENABLESOUTPUT
–100 mV < VID < 100 mV
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
3
1Y
5
2Y
11
3Y
13
4Y
Function Tables
SN75LVDS32
A, BG
VID ≥ 100 mV
VID ≤ –100 mV
XLHZ
Open
H
X
H
X
H
X
H
X
’L VDS9637D logic diagram
(positive logic)
1A
1B
2A
2B
8
7
6
5
G
X
L
X
L
X
L
X
L
Y
H
H
?
?
L
L
H
H
2
1Y
3
2Y
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
logic symbol
DIFFERENTIAL INPUT
–100 mV < VID < 100 mV?
H = high level, L = low level, ? = indeterminate
†
†
This symbol is in accordance with ANSI/IEEE Std
91-1984 and IEC Publication 617-12.
Function Table
SN75LVDS9637
OUTPUT
A, BY
VID ≥ 100 mVH
VID ≤ –100 mVL
OpenH
1A
1B
2A
2B
3A
3B
4A
4B
SN75LVDS32
4
G
12
G
2
1
6
7
10
9
14
15
≥ 1
EN
logic symbol
3
1Y
5
2Y
11
3Y
13
4Y
†
SN75LVDS9637
8
1A
7
1B
6
2A
5
2B
†
This symbol is in accordance with ANSI/IEEE Std
91-1984 and IEC Publication 617-12.
2
3
1Y
2Y
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
equivalent input and output schematic diagrams
EQUIVALENT OF EACH A OR B INPUTEQUIVALENT OF G, G, 1,2EN OR
V
CC
300 kΩ300 kΩ
Input
A InputB Input
7 V7 V
3,4EN INPUTS
50 Ω
7 V
V
CC
TYPICAL OF ALL OUTPUTS
V
CC
5 Ω
Y Output
7 V
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
D (8)725 mW5.8 mW/°C464 mW
D (16)950 mW7.6 mW/°C608 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with
no air flow.