SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
D
Meets or Exceeds the Requirements of
ANSI TIA/EIA-644 Standard
D
Operates With a Single 3.3-V Supply
D
Designed for Signaling Rate of Up To
155 Mbps
D
Differential Input Thresholds ±100 mV Max
D
Low-Voltage TTL (LVTTL) Logic Output
Levels
D
Open-Circuit Fail Safe
D
Characterized For Operation From
0°C to 70°C
description
The SN75LVDS32 and SN75LVDS9637 are
differential line receivers that implement the
electrical characteristics of low-voltage differential
signaling (L VDS). This signaling technique lowers
SN75LVDS32D (Marked as 75LVDS32)
SN75LVDS9637D (Marked as DF637 or 7L9637)
1B
1A
1Y
2Y
2A
2B
GND
V
CC
1Y
2Y
GND
(TOP VIEW)
1
2
3
G
4
5
6
7
8
(TOP VIEW)
1
2
3
4
16
15
14
13
12
11
10
V
CC
4B
4A
4Y
G
3Y
3A
9
3B
1A
8
1B
7
2A
6
5
2B
the output voltage levels of 5-V differential
standard levels (such as EIA/TIA-422B) to reduce
the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state
with a ±100 mV allow operation with a differential input voltage within the input common-mode voltage range.
The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.
The intended application of these devices and signaling technique is both point-to-point and multidrop (one
driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The
transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance
of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.
The SN75LVDS32 and SN75LVDS9637 are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright 1999, Texas Instruments Incorporated
1
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
logic diagram
’L VDS32 logic diagram
(positive logic)
4
G
12
G
2
1A
1
1B
6
2A
7
2B
10
3A
9
3B
14
4A
15
4B
DIFFERENTIAL INPUT ENABLES OUTPUT
–100 mV < VID < 100 mV
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
3
1Y
5
2Y
11
3Y
13
4Y
Function Tables
SN75LVDS32
A, B G
VID ≥ 100 mV
VID ≤ –100 mV
X L H Z
Open
H
X
H
X
H
X
H
X
’L VDS9637D logic diagram
(positive logic)
1A
1B
2A
2B
8
7
6
5
G
X
L
X
L
X
L
X
L
Y
H
H
?
?
L
L
H
H
2
1Y
3
2Y
2
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
logic symbol
DIFFERENTIAL INPUT
–100 mV < VID < 100 mV ?
H = high level, L = low level, ? = indeterminate
†
†
This symbol is in accordance with ANSI/IEEE Std
91-1984 and IEC Publication 617-12.
Function Table
SN75LVDS9637
OUTPUT
A, B Y
VID ≥ 100 mV H
VID ≤ –100 mV L
Open H
1A
1B
2A
2B
3A
3B
4A
4B
SN75LVDS32
4
G
12
G
2
1
6
7
10
9
14
15
≥ 1
EN
logic symbol
3
1Y
5
2Y
11
3Y
13
4Y
†
SN75LVDS9637
8
1A
7
1B
6
2A
5
2B
†
This symbol is in accordance with ANSI/IEEE Std
91-1984 and IEC Publication 617-12.
2
3
1Y
2Y
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3
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
equivalent input and output schematic diagrams
EQUIVALENT OF EACH A OR B INPUT EQUIVALENT OF G, G, 1,2EN OR
V
CC
300 kΩ300 kΩ
Input
A Input B Input
7 V 7 V
3,4EN INPUTS
50 Ω
7 V
V
CC
TYPICAL OF ALL OUTPUTS
V
CC
5 Ω
Y Output
7 V
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Input voltage range, V
I
(A or B) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
D (8) 725 mW 5.8 mW/°C 464 mW
D (16) 950 mW 7.6 mW/°C 608 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with
no air flow.
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
‡
POWER RATING
TA = 70°C
–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
4
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Magnitude of differential input voltage, |VID| 0.1 0.6 V
Common-mode input voltage, VIC (see Figure 1)
Operating free-air temperature, T
CC
IH
IL
A
G, G 2 V
G, G 0.8 V
COMMON-MODE INPUT VOLTAGE RANGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
3 3.3 3.6 V
|VID|
2
0 70 °C
|VID|
2.4
*
VCC – 0.8 V
2
V
2
1.5
1
– Common Mode Input Voltage – V
0.5
IC
V
0
0 0.1 0.2 0.3
VID – Differential Input Voltage – V
Figure 1. VIC Versus VID and V
Max at VCC >3.15 V
Max at VCC = 3 V
Min
0.4 0.5 0.6
CC
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5
SN75LVDS32, SN75LVDS9637
Á
Á
Á
Á
ББББББББББББББББ
ББББББББББББББББ
See Figure 2 and Table 1
ББББББББББББББББ
ББББББББББББББББ
БББББББББББ
БББББББББББ
SN75LVDS32
БББББББББББ
ББББББББББББББББ
I
ББББББББББББББББ
Input current (A or B inputs)
A
ББББББББББББББББ
ББББББББББББББББ
ББББББББББББББББ
ББББББББББББББББ
ББББББББББББББББ
ББББББББББББББББ
ББББББББББББББББ
See Figure 3
ББББББББББББББББ
ББББББББББББББББ
ББББББББББББББББ
ББББББББББББББББ
ББББББББББББББББ
See Figure 4
ББББББББББББББББ
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
SN75LVDSxxxx electrical characteristics over recommended operating conditions (unless
otherwise noted)
SN75LVDS32,
БББББББББББББББББ
V
V
V
V
ITH+
ITH–
OH
OL
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage
Low-level output voltage
PARAMETER
‡
ББББББ
TEST CONDITIONS
IOH = –8 mA
IOL = 8 mA
Enabled, No load
I
CC
I
I
I(OFF)
I
IH
I
IL
I
OZ
†
All typical values are at TA = 25°C and with VCC = 3.3 V.
‡
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for the negative-going
Supply current
p
p
Power-off input current (A or B inputs)
High-level input current (G, or G inputs)
Low-level input current (G, or G inputs)
High-impedance output current
SN75LVDS9637
Disabled
No load
VI = 0
VI = 2.4 V
VCC = 0, VI = 3.6 V
VIH = 2 V
VIL = 0.8 V
VO = 0 or V
CC
differential input voltage threshold only.
SN75LVDS9637
БББББ
MIN
TYP†MAX
100
–100
2.4
0.4
10
0.25
0.5
5.5
–2
–10
–20
–1.2
–3
6
±10
18
10
20
10
10
Á
UNIT
mV
mV
V
V
mA
µ
µA
µA
µA
µA
SN75LVDSxxxx switching characteristics over recommended operating conditions (unless
otherwise noted)
SN75LVDS32,
PARAMETER
t
pLH
t
pHL
t
sk(p)
t
sk(o)
t
sk(pp)
t
r
t
f
t
pHZ
t
pLZ
t
pZH
t
pZL
†
All typical values are at 25°C and with a 3.3-V supply.
‡
t
§
t
¶
t
with the same supply voltages, same temperature, and have identical packages and test circuits.
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Pulse skew (|t
Channel-to-channel output skew
Part-to-part skew
PHL
– t
|)
PLH
†
‡
Output signal rise time, 20% to 80%
Output signal fall time, 80% to 20%
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low-level output
is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output
sk(p)
is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
sk(o)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
sk(pp)
TEST CONDITIONS
CL = 100 pF,
SN75LVDS9637
MIN
TYP†MAX
2.1
2.1
0.6
0.7
1.5
1.5
0.6
0.6
25
25
25
25
UNIT
6
ns
6
ns
ns
ns
ns
ns
1
ns
ns
ns
ns
ns
6
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SN75LVDS32, SN75LVDS9637
Á
Á
Á
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
A
V
ID
B
V
(VIA + VIB)/2
V
IA
IC
V
IB
Figure 2. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
Y
V
O
APPLIED
VOLTAGES
БББББ
V
IA
1.25 V
1.15 V
2.4 V
2.3 V
0.1 V
0 V
1.5 V
0.9 V
2.4 V
1.8 V
0.6 V
0 V
V
IB
1.15 V
1.25 V
2.3 V
2.4 V
0 V
0.1 V
0.9 V
1.5 V
1.8 V
2.4 V
0 V
0.6 V
RESULTING DIFFERENTIAL
INPUT VOLTAGE
БББББББ
V
ID
100 mV
–100 mV
100 mV
–100 mV
100 mV
–100 mV
600 mV
–600 mV
600 mV
–600 mV
600 mV
–600 mV
RESULTING COMMON-
MODE INPUT VOLTAGE
БББББ
V
IC
1.2 V
1.2 V
2.35 V
2.35 V
0.05 V
0.05 V
1.2 V
1.2 V
2.1 V
2.1 V
0.3 V
0.3 V
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7
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
V
ID
V
IA
V
IB
CL 10 pF
V
O
V
IA
V
IB
V
ID
t
PHL
V
O
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
80%
20%
t
f
80%
20%
t
PLH
t
r
1.4 V
1 V
0.4 V
0
–0.4 V
V
OH
1.4 V
V
OL
Figure 3. Timing Test Circuit and Wave Forms
8
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
1.2 V
Inputs
(see Note A)
V
TEST
A
G
G
t
PLZ
t
PZL
Y
V
TEST
A
G
G
t
PHZ
t
PZH
Y
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
B
500 Ω
A
G
G
10 pF
(see Note B)
t
t
PZL
PZH
V
O
t
PLZ
t
PHZ
±
2.5 V
1 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
2.5 V
1.4 V
VOL +0.5 V
V
OL
0
1.4 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
V
OH
VOH –0.5 V
1.4 V
0
V
TEST
Figure 4. Enable/Disable Time Test Circuit and Wave Forms
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9
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
using an LVDS receiver with RS-422 data
Receipt of data from a TIA/EIA-422 line driver may be accomplished using a TIA/EIA-644 line receiver with the
addition of an attenuator circuit. This technique gives the user a very high-speed and low-power 422 receiver.
If the ground noise between the transmitter and receiver is not a concern (less than ±1 V), the answer can be
as simple as shown below in Figure 5. The use of a resistor divider circuit in front of the L VDS receiver attenuates
the 422 differential signal to LVDS levels.
The resistors present a total differential load of 100 Ω to match the characteristic impedance of the transmission
line and to reduce the signal 10:1. The maximum 422 differential output signal or 6 V is reduced to 600 mV . The
high input impedance of the LVDS receiver prevents input bias offsets and maintains a better than 200-mV
differential input voltage threshold at the inputs to the divider . This circuit is used in front of each L VDS channel
that also receives 422 signals.
R1
45.3 Ω
’LVDS32
R3
5.11 Ω
R4
5.11 Ω
R2
45.3 Ω
NOTE A: The components used were standard values.
R1, R2 = NRC12F45R3TR, NIC Components, 45.3 Ohm, 1/8W, 1%, 1206 Package
R3, R4 = NRC12F5R11TR, NIC Components, 5.11 Ohm, 1/8W, 1%, 1206 Package
The resistor values do not need to be 1% tolerance. However, it can be dif ficult locating a supplier of resistors
having values less than 100 Ω in stock and readily available. The user may find other suppliers with
comparable parts having tolerances of 5% or even 10%. These parts are adequate for use in this circuit.
A
B
Y
Figure 5. RS-422 Data Input to an LVDS Receiver Under Low Ground Noise Conditions
If ground noise between the RS-422 driver and LVDS receiver is a concern, then the common-mode voltage
must be attenuated. The circuit must then be modified to connect the node between R3 and R4 to the LVDS
receiver ground. This modification to the circuit increases the common-mode voltage from ±1 V to greater than
±4.5 V.
10
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
APPLICATIONS INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission where ground
differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers
approach ECL speeds without the power and dual supply requirements.
TRANSMISSION DISTANCE
vs
SIGNALING RATE
100
30% Jitter
(see Note A)
10
5% Jitter
(see Note A)
1
Transmission Distance – m
24 AWG UTP 96 Ω
(PVC Dielectric)
0.1
10 100 1000
Signaling Rate – Mbps
NOTE A: This parameter is the percentage of distortion of the unit interval (UI) with a pseudo-random data pattern.
Figure 6. T ypical Transmission Distance Versus Signaling Rate
3.3 V
16
V
CC
0.001 µF
(see Note A)
4B
4A
4Y
3Y
3A
3B
0.1 µF
(see Note A)
15
100 Ω
14
13
12
G
11
10
9
(see Note B)
See Note C
100 Ω
100 Ω
100 Ω
1
1B
2
1A
3
1Y
4
V
CC
G
5
2Y
6
2A
7
2B
8
GND
NOTES: A. Place a 0.1 µF and a 0.001 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitors should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 7. Typical Application Circuit Schematic
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11
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
TpBias on
Twisted-Pair A
TP
55 Ω
55 Ω
TP
5 kΩ
VG on
Twisted-Pair B
3.3 V
500 Ω
500 Ω
3.3 V
1/4 ’LVDS31
Strb/Data_TX
Strb/Data_Enable
’LVDS32
Data/Strobe
20 kΩ
1 Arb_RX
20 kΩ
500 Ω
500 Ω
3.3 V
7 kΩ7 kΩ
NOTES: A. Resistors are leadless thick-film (0603) 5% tolerance.
B. Decoupling capacitance is not shown but recommended.
C. VCC is 3 V to 3.6 V.
D. The differential output voltage of the ’LVDS31 can exceed that allowed by IEEE1394.
20 kΩ
20 kΩ
10 kΩ
3.3 kΩ
Figure 8. 100-Mbps IEEE 1394 Transceiver
2 Arb_RX
Twisted-Pair B Only
Port_Status
12
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SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair . The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and
100 mV if it is within its recommended input common-mode voltage range. TI’s L VDS receiver is different in how
it handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the L VDS receiver
will pull each line of the signal pair to near V
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high level, regardless of the differential input voltage.
300 kΩ 300 kΩ
through 300-kΩ resistors as shown in Figure 9. The fail-safe
CC
V
CC
A
Rt
B
VIT ≈ 2.3 V
Y
Figure 9. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not af fect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
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13
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
0.01 µF
16
V
1
1B
100 Ω
100 Ω
NOTES: A. Place a 0.1 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The
capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
2
1A
3
1Y
4
V
CC
G
5
2Y
6
2A
7
2B
8
GND
CC
4B
4A
4Y
3Y
3A
3B
15
14
13
12
G
11
10
9
≈3.6 V
0.1 µF
(see Note A)
100 Ω
(see Note B)
See Note C
100 Ω
5 V
1N645
(2 places)
Figure 10. Operation with 5-V Supply
related information
IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at
for more information.
For more application guidelines, please see the following documents:
D
Low-Voltage Differential Signalling Design Notes
D
Interface Circuits for TIA/EIA-644
D
Reducing EMI with LVDS
D
Slew Rate Control of LVDS Circuits
D
Using an LVDS Receiver with RS-422 Data
D
Evaluating the LVDS EVM
(SLLA030)
(SLLA033)
(LVDS) (SLLA038)
(SLLA034)
(SLLA014)
(SLLA031)
www.ti.com
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75LVDS32, SN75LVDS9637
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
SLLS360A – JUNE 1999 – REVISED MARCH 2000
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
14
1
0.069 (1,75) MAX
A
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.004 (0,10)
DIM
8
7
PINS **
0.010 (0,25)
0.157 (4,00)
0.150 (3,81)
M
0.244 (6,20)
0.228 (5,80)
Seating Plane
0.004 (0,10)
8
14
0.008 (0,20) NOM
0°–8°
16
Gage Plane
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
A MAX
A MIN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.197
(5,00)
0.189
(4,80)
0.344
(8,75)
0.337
(8,55)
0.394
(10,00)
0.386
(9,80)
4040047/D 10/96
15
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