Texas Instruments SN75LVDS31D, SN75LVDS31DR Datasheet

D

Meets or Exceeds the Requirements of
ANSI TIA/EIA-644 Standard

D

Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load

D

Signaling Rates up to 155 Mbps

D

Operates From a Single 3.3-V Supply

D

Driver at High Impedance When Disabled or
With VCC = 0

D

Low-Voltage TTL (LVTTL) Logic Input
Levels

D

Characterized For Operation From
0°C to 70°C

description

The SN75LVDS31 and SN75LVDS9638 are
differential line drivers that implement the
electrical characteristics of low-voltage differential
signaling (L VDS). This signaling technique lowers
the output voltage levels of 5 V differential

SN75LVDS31, SN75LVDS9638

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS359A – JUNE 1999 – REVISED MARCH 2000

SN75LVDS31D (Marked as 75LVDS31)

SN75LVDS9638D (Marked as DF638 or 7L9638)

GND

V

CC

1A
2A

GND

(TOP VIEW)

1A
1Y
1Z

G
2Z
2Y
2A

(TOP VIEW)

16
15
14
13
12
11
10

V

CC

4A
4Y
4Z
G
3Z
3Y

9

3A

1Y

8

1Z

7

2Y

6
5

2Z

1
2
3
4
5
6
7
8

1
2
3
4

standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow
operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output
voltage magnitude of 247 mV into a 100-Ω load when enabled.

The intended application of these devices and signaling technique is for point-to-point baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be
printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN75LVDS31 and SN75LVDS9638 are characterized for operation from 0°C to 70°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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Copyright  2000, Texas Instruments Incorporated

1

SN75LVDS31, SN75LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS359A – JUNE 1999 – REVISED MARCH 2000

4
12

1

7

9

15

†

SN75LVDS31

≥ 1

EN

2

1Y

3

1Z

6

2Y

5

2Z

10

3Y

11

3Z

14

4Y

13

4Z

†

SN75LVDS9638

8

2

3

1Y

7

1Z

6

2Y

5

2Z

logic symbol

G
G

1A

2A

3A

4A

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.

logic symbol

1A

2A

’LVDS31 logic diagram (positive logic)

4

G

12

1A

2A

3A

4A

G

1

7

9

15

10
11

14
13

2

1Y

3

1Z

6

2Y

5

2Z

3Y
3Z

4Y
4Z

’LVDS9638 logic diagram (positive logic)

8

1A

2A

2

3

1Y

7

1Z

6

2Y

5

2Z

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.

2

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HIGH-SPEED DIFFERENTIAL LINE DRIVERS

Function Tables

SN75LVDS31

INPUT

A

H H X H L

L H X L H

H X L H L

L X L L H

X L H Z Z
Open H X L H
Open X L L H

H = high level, L = low level, X = irrelevant,
Z = high impedance (off)

ENABLES OUTPUTS

G

G

SN75LVDS9638

INPUT

A

H H L

L L H

OPEN L H

H = high level, L = low level

OUTPUTS

Y Z

Y Z

SN75LVDS31, SN75LVDS9638

SLLS359A – JUNE 1999 – REVISED MARCH 2000

equivalent input and output schematic diagrams

EQUIVALENT OF EACH A INPUT EQUIVALENT OF G, G INPUTS TYPICAL OF ALL OUTPUTS

Input

7 V

50 Ω

300 kΩ

V

CC

Input

50 Ω

7 V

V

CC

10 kΩ

V

CC

5 Ω

Y or Z
Output

7 V

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3

SN75LVDS31, SN75LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS359A – JUNE 1999 – REVISED MARCH 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65_C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.

DISSIPATION RATING TABLE

PACKAGE

D (8) 725 mW 5.8 mW/°C 464 mW

D (16) 950 mW 7.6 mW/°C 608 mW

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

‡

POWER RATING

TA = 70°C

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Operating free-air temperature, T

CC

IH

IL

A

3 3.3 3.6 V
2 V

0.8 V

0 70 °C

†

4

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SN75LVDS31, SN75LVDS9638

ICCSu ly current

SN75LVDS9638

V

V

IOSShort-circuit output current

See Figure 2

See Figure 4

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS359A – JUNE 1999 – REVISED MARCH 2000

electrical characteristics over recommended operating conditions (unless otherwise noted)

SN75LVDS31,

PARAMETER TEST CONDITIONS

V

OD

∆V

OD

∆V

OC(SS)

V

OC(SS)

V

OC(PP)

I

IH

I

IL

I

OZ

I

O(OFF)

C

I

†

All typical values are at TA = 25°C and with VCC = 3.3 V.

Differential output voltage magnitude

Change in differential output voltage magnitude
between logic states

Change in steady-state common-mode output voltage
between logic states

Steady-state common-mode output voltage
Peak-to-peak common-mode output voltage 50 150 mV

SN75LVDS31

pp

High-level input current VIH = 2 4 20 µA
Low-level input current VIL = 0.8 V 0.1 10 µA

p

High-impedance output current VO = 0 or 2.4 V ±1 µA
Power-off output current VCC = 0, VO = 2.4 V ±1 µA
Input capacitance 3 pF

RL = 100 Ω, See Figure 2

See Figure 3

VI = 0.8 V or 2 V,
No load

VI = 0.8 or 2 V,
Enabled

VI = 0 or VCC,

= 0.8 V or 2

I

V

or V

O(Y)

VOD = 0 ±12 mA

O(Z)

Enabled,

RL = 100 Ω,

Disabled
No load
RL = 100 Ω

= 0 –4 –24 mA

SN75LVDS9638

MIN TYP†MAX

247 340 454 mV

–50

1.125 1.2 1.375 V
–50 50 mV

0.25 1 mA

4.7 8 mA

50 mV

9 20 mA

25 35 mA

9 13 mA

UNIT

switching characteristics over recommended operating conditions (unless otherwise noted)

SN75LVDS31,

PARAMETER TEST CONDITIONS

t

pLH

t

pHL

t

r

t

f

t

sk(p)

t

sk(o)

t

sk(pp)

t

pZH

t

pZL

t

pHZ

t

pLZ

†

All typical values are at TA = 25°C and with VCC = 3.3 V.

‡

t

sk(p)

§

t

sk(o)

¶

t

sk(pp)

with the same supply voltages, same temperature, and have identical packages and test circuits.

Propagation delay time, low-to-high-level output 6 ns
Propagation delay time, high-to-low-level output 6 ns
Differential output signal rise time (20% to 80%)
Differential output signal fall time (80% to 20%)
Pulse skew (|t
Channel-to-channel output skew
Part-to-part skew
Propagation delay time, high-impedance-to-high-level output 25 ns
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output 25 ns

is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.

is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate

PHL

– t

¶

PLH

‡

|)

§

RL = 100 Ω, CL = 10 pF,

SN75LVDS9638

MIN TYP†MAX

0.5 1.2 ns

0.5 1.2 ns

0.6 ns

0.6 ns
1 ps

25 ns
25 ns

UNIT

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5

SN75LVDS31, SN75LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS359A – JUNE 1999 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

I

OY

I

I

A

V

I

Figure 1. Voltage and Current Definitions

Y

Input

(see Note A)

NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,

pulse width = 10 ± 0.2 ns.

B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.

Z

V

Y

Z

OD

CL = 10 pF
(2 Places)
(see Note B)

I

OZ

100 ± 1 %

V

OD

V

OZ

Input

V

OD

t

PLH

V

OY

V

OC

0

(VOY + VOZ)/2

t

f

t

PHL

2 V

1.4 V

0.8 V

t

r

100%
80%

20%
0%

Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal

49.9 Ω ± 1% (2 Places)

Y

Input

(see Note A)

NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,

pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
C. The measurement of V

A

Z

V

OC
CL = 10 pF
(2 Places)
(see Note B)

is made on test equipment with a –3 dB bandwidth of at least 300 MHz.

OC(PP)

A

V

OC(PP)

(see Note C)

V

OC

3 V

0

V

OC(SS)

Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output V oltage

6

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SN75LVDS31, SN75LVDS9638

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS359A – JUNE 1999 – REVISED MARCH 2000

PARAMETER MEASUREMENT INFORMATION

Y

Inputs

(see Note A)

G

G

t

PZH

V

OY

or

V

OZ

t

PZL

V

OZ

or

V

NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,

B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.

OY

pulse width = 500 ± 10 ns.

0.8 V or 2 V

G
G

Z

CL = 10 pF

(2 Places)

(see Note B)

t

PHZ

t

PLZ

2 V

1.4 V

0.8 V
2 V

1.4 V

0.8 V

100%, ≅ 1.4 V
50%

0%, 1.2 V

100%, 1.2 V
50%
0%, ≅ 1 V

49.9 Ω ± 1% (2 Places)

1.2 V

V

OYVOZ

A at 2 V, G at VCC and Input to G
or
G at GND and Input to G for ’LVDS31 only

A at 0.8 V, G at VCC and Input to G
or
G at GND and Input to G for ’LVDS31 only

Figure 4. Enable and Disable Time Circuit and Definitions

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7

SN75LVDS31, SN75LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS359A – JUNE 1999 – REVISED MARCH 2000

APPLICATIONS INFORMATION

Figure 5. T ypical Transmission Distance Versus Signaling Rate

1

1A

2

1Y

ZO = 100 Ω

ZO = 100 Ω

3

1Z

4

V

CC

G

5

2Z

6

2Y

7

2A

8

GND

3.3 V

16

V

CC

0.001 µF
(see Note A)

4A

4Y

4Z

3Z

3Y

3A

0.1 µF

15
14

13

12

G

11

10

9

(see Note A)

ZO = 100 Ω

See Note B

ZO = 100 Ω

NOTES: A. Place a 0.1 µF and a 0.001 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground

plane. The capacitors should be located as close as possible to the device terminals.

B. Unused enable inputs should be tied to VCC or GND as appropriate.

Figure 6. Typical Application Circuit Schematic

8

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TP

TP

TpBias on

Twisted-Pair A

55 Ω

55 Ω

5 kΩ

VG on

Twisted-Pair B

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

APPLICATIONS INFORMATION

1/4 ’LVDS31

’LVDS32

3.3 V

500 Ω

500 Ω

20 kΩ

20 kΩ

3.3 V

SN75LVDS31, SN75LVDS9638

SLLS359A – JUNE 1999 – REVISED MARCH 2000

Strb/Data_TX

Strb/Data_Enable

Data/Strobe

1 Arb_RX

500 Ω

500 Ω

3.3 V

7 kΩ7 kΩ

NOTES: A. Resistors are leadless thick-film (0603) 5% tolerance.

B. Decoupling capacitance is not shown but recommended.
C. VCC is 3 V to 3.6 V.
D. The differential output voltage of the ’LVDS31 can exceed that specified by IEEE1394.

Figure 7. 100 Mbps IEEE1394 Transceiver

20 kΩ

2 Arb_RX

20 kΩ

Twisted-Pair B Only

10 kΩ

Port_Status

3.3 kΩ

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9

SN75LVDS31, SN75LVDS9638
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS359A – JUNE 1999 – REVISED MARCH 2000

APPLICATIONS INFORMATION

0.01 µF

1

1A

2

1Y

ZO = 100 Ω

ZO = 100 Ω

NOTE A: Place a 0.1 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitor

should be located as close as possible to the device terminals.

3

1Z

4

V

CC

G

5

2Z

6

2Y

7

2A

8

GND

16

V

CC

15

4A

14

4Y

13

4Z

12

G

11

3Z

10

3Y

9

3A

≈3.6 V

0.1 µF
(see Note A)

See Note B

5 V

1N645

(2 places)

ZO = 100 Ω

ZO = 100 Ω

Figure 8. Operation with a 5-V Supply

related information

IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at
for more information.

For more application guidelines, please see the following documents:

D

Low-Voltage Differential Signalling Design Notes

D

Interface Circuits for TIA/EIA-644

D

Reducing EMI with LVDS

D

Slew Rate Control of LVDS Circuits

D

Using an LVDS Receiver with RS-422 Data

D

Evaluating the LVDS EVM

(SLLA030)

(SLLA033)

(LVDS) (SLLA038)

(SLLA034)

(SLLA014)

(SLLA031)

www.ti.com

10

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SN75LVDS31, SN75LVDS9638

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS359A – JUNE 1999 – REVISED MARCH 2000

MECHANICAL INFORMATION

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0.050 (1,27)

14

1

0.069 (1,75) MAX

A

0.020 (0,51)

0.014 (0,35)

0.010 (0,25)

0.004 (0,10)

DIM

8

7

PINS **

0.010 (0,25)

0.157 (4,00)

0.150 (3,81)

M

0.244 (6,20)

0.228 (5,80)

Seating Plane

0.004 (0,10)

8

14

0.008 (0,20) NOM

0°–8°

16

Gage Plane

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

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0.197

(5,00)

0.189

(4,80)

0.344

(8,75)

0.337

(8,55)

0.394

(10,00)

0.386

(9,80)

4040047/D 10/96

11

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Copyright  2000, Texas Instruments Incorporated